Paper 13103-39
Superlattice-doped PMOS imaging arrays for broadband visible applications
Abstract
This paper discusses the further development of JPL’s n-type superlattice doping (2D doping) process for sensitivity and stability enhancement of backside illuminated (BSI), p-channel CCDs and PMOS pixel CMOS imaging arrays. We discuss the results of the n-type 2D-doping of SRI’s backside illuminated PMOS pixel 4k×4k and 8k×8k CMOS imagers. We briefly describe the backside processing parameters for the optimization of the 2D-doping process and antireflection coating design. Performance characterization, including quantum efficiency (QE), dark signal, and modulation transfer function (MTF) as a function of silicon epitaxial thickness and operating temperature will be discussed. These will be compared with the performance of devices produced using SRI’s standard BSI processes.
Presenter
April D. Jewell
Jet Propulsion Lab. (United States)