This PDF file contains the front matter associated with SPIE Proceedings Volume 8326, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.

Self Aligned Double Patterning (SADP) is now widely accepted as a viable technology for the further extension of 193nm immersion lithography towards the 22nm /18nm technology nodes. SADP was primary introduced for the manufacturing of flash memory due to its 1D design geometry. However, SADP is now becoming a main stream technology for advanced technology nodes for logic product. SADP results in alignment marks with reduced image contrast after completion of spacer patterning. Consequently there is an elevated risk that the alignment performance of the cut lithography layer on the spacer [1] may be negatively impacted. Initial studies indicate that it may be necessary to consider new mark designs. In this paper, we will evaluate different types of SADP processes with the alignment system of the Nikon S620D and S621D immersion scanner. We will discuss the performances and the differences observed due to the SADP materials. Included in this study is an intensive characterization of the morphology of the spacer after SADP process. We will use for this a 3D-AFM from Insight, and characterize the spacer profile of the spacer. Using a standard AFM microscope, we can characterize the surface roughness in the inner and the outer part of the wafer. The self aligned spacer process results in asymmetric spacers. Two types of surface (inside and outside) of the spacer are formed. The impact of this asymmetry is also assessed. The roughness difference, between the two parts, will play an important roll in the alignment contrast.

Memory devices such as DRAM and NAND flash will continue to increase their capacity through scaling, which will extend to below the 10nm regime. From a device physics perspective, there are possible solutions for scaling below 10nm. However, the challenges of sub-10nm scaling will come from the productivity. In fact, major challenges for the realization of high density memory devices are lithography and vertical etching of high aspect ratio holes in DRAM and 3D flash memories. Here, status and the direction of DRAM and flash memory scaling technologies will be reviewed with a special focus on the extendibility from not only device physics but also productivity points of view.

Negative tone development (NTD) processes have been widely explored as a way to enhance the printability of dark field features such as contact holes and trenches. A key consequence of implementing NTD processes and subsequent tone reversal of dark field reticles is the significantly higher transmission of bright field masks and thus higher light intensity in the projection optics. This large increase in mask transmission coupled with the higher throughput requirements of multiple patterning and the use of freeform illumination created by source mask optimization creates a significant amount of lens heating induced aberrations that must be characterized and mitigated. In this paper, we examine the lens heating induced aberrations for high transmission reticles common to NTD using both simulations and experiments on a 193 immersion lithography tool. We observe a substantial amount of aberrations as described by even and odd order Zernike drifts during the course of a wafer exposure lot. These Zernike drifts per lot are demonstrated to have the following lithographic effects: critical dimension shifts, pitch dependent best focus shifts and image placement errors between coarse and fine patterned features. Lastly, mitigation strategies are demonstrated using various controllers and lens manipulators, including FlexWave with full Zernike control up to Z64, to substantially reduce the lens heating effects observed on-wafer.

In this work, correction techniques in the spatial and frequency domains are applied to improve the accuracy of less rigorous but more efficient mask models. This allows to reproduce the electromagnetic field (EMF) effects predicted by the rigorous model preserving the simplicity of the Kirchhoff model. In the frequency domain, two approaches are considered. First, a Jones pupil function is introduced in the projector pupil plane to describe amplitude, phase and polarization effects which are introduced by the mask. Second, a correction process performed directly on the scalar spectrum is used to tune the diffraction orders that get into the pupil of the optical projection system. Since a vector imaging description is needed to include the polarization phenomena, the spectra of the different polarization components are constructed from the scalar spectrum using correspondingly calibrated filters. In the spatial domain the well-known boundary layer model is considered.1 The bright features of the thin mask are surrounded with a semi-transparent region with a certain width, transmission and phase. Alternatively, the bright mask features of the Kirchhoff model are modified by adding delta functions to the edges of the absorber. All correction functions for spatial and frequency are obtained by a calibration with a rigorous model. The validity of these filtering techniques for different feature sizes and pitches is investigated.

3D lithography simulations capable of modeling 3D effects in all lithographic processes are becoming critical in OPC and verification applications as semiconductor feature sizes continue to shrink. These effects include mask topography, resist profile and wafer topography. In this work we present an efficient computational framework for full-chip 3D lithography simulations. Since fast modeling of mask topography effects has been studied for many years and is a relatively mature area, we will only briefly review a full-chip 3D mask model, Tachyon M3D, to highlight the importance and modeling requirements for accurate prediction of best focus variations among different device features induced by mask topography. We will focus our discussions on a full-chip 3D resist model, Tachyon R3D, its derivation and simplification from a full physical resist model. The resulting model form is fully compatible with the existing 2D resist model with added capabilities for resist profile and top loss prediction. A benchmark against the full physical model will be presented as well. We will also describe the development of a full-chip 3D wafer topography model, Tachyon W3D, and the preliminary results against rigorous simulations.

In previous work, a rigorous physical model was developed to describe a thermal freeze LPLE (Litho-Process- Litho- Etch) process. Subsequent experimental studies revealed a significant CD correlation between the CD of the litho 2 pattern and that of the litho 1 pattern, when the features are inter-digitated. Simulation of the experiment shows similar behavior, although the predicted magnitude is incorrect. Experimentation with the model reveals that the behavior is driven by three mechanisms; the mis-match of the index of refraction between the two resist, the acid/quencher diffusion boundary between the resist materials and finally optical lensing effects caused by the non-planar surface of the second resist as it covers the features defined in the first resist. Once the mechanisms are identified the model is recalibrated with significantly improved accuracy.

With the decrease of the transistors dimensions, process steps usually considered as not critical become challenging. This is the case for implant levels patterning, which can be strongly impacted by reflections from the underlying active and gate patterns, especially when no anti-reflective coating can be used. This stack effect leads to unexpected resist shape on wafer if not taken into account during OPC flow. We propose a solution to integrate stack effect onto existing OPC models by adding fictive layers at mask level in order to allow a stack-aware OPC or mask verification. This method can be implemented in a standard OPC flow offered by EDA OPC software. It provides effective results compatible with production constrains, such as stack-aware full chip simulation and run time efficiency.

Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE. This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID. Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.

Double Patterning (DP) is the most immediate lithography candidate for IC technologies requiring pitches below the single exposure capabilities of today's ArF immersion scanners. Litho-Process-Litho-Etch (LPLE) double patterning (DP) processes potentially offer substantial cost and throughput benefits over the more proven Litho-Etch-Litho-Etch (LELE) approaches. However, LPLE DP approaches typically use a different resist for each lithography step and there are many potential process and material interactions between the lithographic layers which could have an impact on proximity effects after full DP flow. In this work the impact of process and material interactions on proximity effects is investigated for a metal 1 double trench LELE process and a poly double line LPLE process. The process windows for several pitches and proximity behaviour of both pattern 1 and pattern 2 is studied. Results obtained from a single patterned wafer are compared with results from a single patterned and double patterned area on a double patterned wafer. The results reveal that for the LPLE case there are process window and proximity differences between single and double patterned wafers showing the influence of a neighbouring line from another patterning step. The process window differences do not just consist of a simple shift along the dose axis. For a few specific cases the experimental results are compared to calibrated LPL Prolith model predictions. The Prolith simulation model matches the experimental data and helps to distinguish between chemical, optical and processing effects as the root cause of the observed differences.

Self-aligned quadruple patterning (SAQP) lithography is one of the major techniques for the future process requirement after 16nm/14nm technology node. In this paper, based on the existing knowledge of current 193nm lithography and process flow of SAQP, we will process an early study on the definition of SAQP-friendly layout. With the exploration of the feasible feature regions and possible combinations of adjacent features, we will define several simple but important geometry rules to help define the SAQP-friendliness. Then, we will introduce a conflicting graph algorithm to generate the feature region assignment for SAQP decomposition. Our experimental results validate our SAQP-friendly layout definition, and basic circuit building blocks in the low level metal layer are analyzed.

Lithographic process development at small k1 factors requires source-mask optimization (SMO) for obtaining sufficient process stability. Two prerequisites must be fulfilled to directly employ the SMO solutions for the optimized source and mask layouts: i) the simulation model underlying SMO should accurately predict the printing on wafer, and ii) the mask patterns must be manufacturable. With regard to i), SMO including a properly calibrated physical resist model is assumed to be more predictive across variable source and mask shapes than SMO with a computationally fast but simplifying photoresist treatment. By coupling SMO and rigorous lithography simulations, we effectively incorporate physical resist modelling into SMO. Additionally, concerning ii), we tackle the manufacturability task by incorporating mask rule constraints already during SMO. Optimizing the mask's degrees of freedom in a mask-rule constrained space, we avoid any post-processing of the optimized mask clips and any corresponding degradation of the result quality. The concept of constrained optimization is also extended to placing and optimizing assist features during SMO. We employ virtual assist feature seeds that can only form real assists if mask rules are met. In that way assist features are simultaneously co-optimized together with the main features and the source.We discuss our approach at 2 examples, a line/space array edge and a SRAM cell, and point to reference1 for a rigorous cell optimization for DRAM.

DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features. Resolution Enhancement Techniques are used to optimize the periodic pattern process performance. This is often realized with aggressively coherent illumination sources supporting the periodic pattern pitch only and making an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from periodic patterns to non periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Non functional dummy structures are very effective to support the outermost edge but are very expensive, so their reduction or avoidance directly increases chip space efficiency. This paper focuses on how to optimize the DRAM array edge automatically in contrast to manual optimization approaches that were used effectively but at high cost. We will show how to squeeze out the masks degrees of freedom to stay within tight pattern tolerances. In that way we minimize process variations and the need of costly non-functional dummy structures. To obtain the best possible results the optimization has to account for complex boundary conditions: correct resist effect prediction, mask manufacturability constraints, low dose, low MEEF, conservation of symmetries and SRAF printing, simultaneous optimization of main features and SRAFs. By incorporating these complex boundary conditions during optimization we aim to provide first time right layouts without the need for any post processing.

This paper presents a combined source/mask/projector pupil optimization (SMPO) procedure, aiming at the maximization of the common process window of different line/space configurations. The parameters are given by a pixelated source representation, sizes of the main features and the SRAF configuration. The projector wavefront is varied through the coefficients of the Fringe/Zernike polynomials for spherical aberrations. A genetic algorithm is applied as the underlying optimization algorithm. A number of results are presented and discussed, demonstrating the feasibility and potentials of the approach.

Source Mask Optimization1 (SMO) is one of the most important techniques available for extending ArF immersion lithography. The combination of freeform source shape and complex mask pattern, determined by SMO, can extend the practical resolution of a lithography system. However, imaging with a small k1 factor (~0.3 or smaller) is very sensitive to many imaging parameters, such as illumination source shape error, lens aberration, process property, etc. As a result, the real source shape must be re-adjusted to realize the expected imaging performance as may be seen, for example, in an Optical Proximity Effect (OPE) curve. In this paper we present an illumination pupilgram re-adjustment method that can effectively control the various illumination parameters to get optimum imaging performance, which is required for the lithography process design. The modulation functions are called Zernike intensity/distortion modulations2. Since the pupilgram modulation is expressed by Zernike polynomials3, a high degree of pupilgram adjustment freedom is provided to the intelligent illuminator4 (freeform illumination) which can be effectively modeled in the optimization. Furthermore, the magnitude of each adjusting Zernike component can be restricted to prevent over modulation, which may affect imaging performance for various patterns on a mask. Furthermore, the linear impact of each term of Zernike modulation can allow us to use Zernike linear combination analysis to calculate imaging performance. Therefore, optimization using a large variety of illumination modulation terms may be possible with reasonable computation loads. The method is combined with an imaging simulator that includes resist models and optimization algorithms in pupilgram refinement software called "OPE Master". The software can take into account the scanner signature and various constraints so that the result of the optimization can be accurately realized on the scanner. The optimization can be performed based on rigorous imaging simulation and Zernike linear combination analysis, which is based on a precalculated Zernike linear sensitivity table.

Mainstream high-end lithography is currently focusing on 32 nm node and 22 nm node where 1.35 NA immersion technology is well established for the most critical layers. Double-patterning and spacer-patterning techniques have been developed and are being widely used to print the most critical layers. Further down the lithography roadmap we see 1x nm nodes coming where EUV lithography will take over critical layers from immersion. In order to enable a smooth industry-wide transition towards EUV, 1.35 NA immersion technology will continue to play a critical role in manufacturing front end layers in the coming years. Using immersion technology beyond the 22 nm node, we expect an increase in the use of double and even quadruple patterning technology for the critical layers. This demands tighter control of especially overlay and focus performance on the 1.35 NA immersion tools. Also fully flexible illumination and wave front control will be needed to optimize the contrast for these low k1 applications. In this paper we present the state-of-the-art system performance of today's 1.35 NA ArF immersion tool production workhorse, the TWINSCAN NXT:1950i. Furthermore we show the required scanner improvements on imaging, overlay and cost of ownership to enable device shrink below the 20 nm node in 2013 using immersion technology.

In state of the art production, in order to obtain the best possible overlay performance between critical layers, wafers are often dedicated to one scanner and all layers processed on that scanner, and in the case of scanners with dual stages, this often extends to stage dedication as well. Meeting the overlay performance requirements becomes even more complex with the introduction of EUV lithography into production. It will not be possible to expose all critical layers on an EUV scanner, which will only be used for some of the most critical layers, the other critical layers will remain on 193nm immersion scanners. It therefore needs to be demonstrated that the same overlay performance is achievable when tool types are mixed and matched as when we run with tool dedication. To do this it is critical that we understand the overlay matching characteristics of 193nm immersion and EUV scanners and from this learn how to control them, so that the optimum strategy can be developed and overlay errors between these tool types minimized. In this work we look at the matching performance between two generations of 193nm immersion scanner and an EUV pre-production tool. We evaluate the matching in both directions, first layer on immersion, second layer on EUV and vice-versa, and demonstrate how optimum matching can be achieved, so that insertion of an EUV scanner into production for the required imaging does not result in a degraded overlay capability. We discuss the difference in grid and intrafield signatures between the tool types and how this knowledge can be used to minimize the overlay errors between them and if there are any new concerns which impact the chosen strategy when the two tool types are mixed and matched.

Source & Mask Optimization1 (SMO) is a promising candidate to realize further reduction of k1 factor to achieve 22nm feature lithography and beyond. To make the SMO solutions feasible all imaging-related parameters should be closer to the designed parameters used in SMO process. In this paper, we discuss how we realize this in the imaging system setup on the scanner. The setup process includes freeform pupilgram generation, pupilgram adjustment and thermal aberration control. For each step the important factors are speed and accuracy.

Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without BARC, e.g., implant layer, as technology node shrinks. For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full chip OPC on implant layers.

As double patterning techniques such as spacer double/quadruple patterning mature, ArF water immersion lithography is expected to be applied down to the 1x nm hp node or beyond. This will necessitate precise process control solutions to accommodate extremely small process windows. In the case of spacer double/quadruple patterning in particular, CD uniformity of the final feature is strongly related to the lithography performance of the initial pre-spacer feature. CD uniformity of the resist image is affected by many sources. In the case of the exposure tool, CD error on the reticle, as well as exposure dose and focus errors are the key factors. For the resist process, heterogeneity of the stacked resist film thickness, post exposure bake (PEB) plate temperature, and development all have an impact. Furthermore, the process wafer also has error sources that include under-layer non-uniformities or wafer flatness. Fortunately, the majorities of these non-uniformities are quite stable in a volume production process. To improve and maintain the CD uniformity, a technique to calculate exposure dose and focus correction values simultaneously using the measured resist image feature was reported previously [1]. Further, a demonstration of a correction loop using a neural network calculation model was reported in SPIE 2010 [2], and the corrected CD uniformity was less than 1.5 nm (3 sigma) within a wafer. For further improvement, a demonstration of precise dose and focus control using high order field-by-field correction was then reported at SPIE 2011[3]. In that work, the interand intra-field CD uniformities reported were less than 1 nm (3 sigma) respectively. A key aspect of this method is the simultaneous compensation of dose and focus offsets, which successfully maximizes the process margin of a target pattern. The Nikon CDU Master then derives the optimal control parameters for each compensation function in the scanner using the exposure dose and focus correction data, with the NSR-S620 scanner having the capabilities to also control higher order dose and focus distribution. This high degree of controllability ultimately enables precise correction of the complicated CD error distribution that is caused by heterogeneities in the process. In this work, this correction concept was expanded to include contact hole CD uniformity optimization and quick correction method using the AMI-3500 auto macro inspection tool. A 3D contour analysis method is used for contact hole CDs measured by CD-SEM. The contact hole CD is then corrected directly without using any other monitor pattern features. Further, using the Nikon AMI-3500 system, it is possible to successfully extract the adjustment components using the optical diffraction image. Since the AMI measurement time is very quick (just a few minutes), a regular correction loop using the AMI may be a promising solution for system auto correction in an IC manufacturing facility.

This work describes a new photoresist imaging model that retains the fundamental physical and chemical properties of optical exposure, post-exposure bake and development. We apply dimensional reduction algorithms that reduce the imaging aspects of the problem, but preserve the imaging and thin film physics. This has the effect of simplifying the overall model and increasing the computational speed, while retaining an extremely accurate predictive capability. The model named the RoadRunner Model, gives more detail and parameter intuition than a basic threshold model and agrees well with full photoresist simulation. The model can be adapted for OPE analysis and source-mask optimization. We present an adaption of the model to incorporate relevant stochastic processes, and we discuss its use in applications such line wide roughness analysis and EUV imaging.

Double patterning (DP) is widely regarded as the lithography solution for 32 nm half pitch semiconductor manufacturing, and DP will be the most likely litho technology for the 22 nm node [1]. When using the DP technique, overlay accuracy and CD control are of critical importance [2]. We previously introduced the NSR-S620D immersion scanner, which provides 2 nm overlay capabilities. In the case of the latest generation NSR-S621D system, improvements have been developed for further overlay accuracy enhancement. In this paper, we will show the overlay accuracy and Mix-and-Match performance of the NSR-S621D. Further, the marked improvement in product overlay and the overlay result in Spacer DP as a result of enhanced alignment accuracy will also be shown.

The tightening of overlay budgets forces us to revisit the characterization and control of exposure tools to eliminate remaining systematic errors. Even though field-to-field overlay has been a known characterization and control technique for quite some time, there is still room to further explore and exploit the technique. In particular, it can be used to characterize systematic errors in a scanner's dynamic exposure behavior. In this paper we investigate the modeling of field-to-field overlay error starting from a scanner point of view. From a set of general equations we show how systematic dynamic differences between up and down scanned fields can be extracted from field-to-field overlay measurements in addition to apparent constant effects. We apply our model to characterize scan speed dependent dynamic behavior and to verify scanner setup.

In this paper we demonstrate the feasibility of Negative Tone Development (NTD) process to pattern 22nm node contact holes leveraging freeform source and model based assist features. We demonstrate this combined technology with detailed simulation and wafer results. Analysis also includes further improvement achievable using a freeform source compared to a conventional standard source while keeping the mask optimization approaches the same. Similar studies are performed using the Positive Tone Development (PTD) process to demonstrate the benefits of the NTD process.

The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask (SMO) and the use of customized illumination modes (freeform illumination sources; Flexray^TM). Also, negative tone development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and positive tone development. The use of negative tone development enables images reversal. This allows benefiting from the improved imaging performance when exposing with bright field masks. The same features can be printed in positive tone resists and with improved process latitudes. At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this architecture to obtain a first learning cycle on this approach. In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a 28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical layers as IM1, IM2, Via0 and Metal1.

As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution required and various double patterning techniques have become the main stream prior to the availability of EUV lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch (LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially for topography issues induced by the 1st mask patterning with the 2nd mask exposure. In this paper, laser parameters, topography issues with the 2nd mask exposure, and SMO effects on CD performances are described in terms of the proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic performance was calculated and used to illustrate the importance of well-controlled laser performance parameters. Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.

In this paper, we report progress in developing a scanning evanescent wave lithography (EWL) imaging head with a twostage gap control system including a DC noise canceling carrying air bearing that floats at a constant air gap with regulated air pressure, and an AC noise canceling piezoelectric transducer with real-time closed-loop feedback from gap detection. Various design aspects of the system including gap detection, prism design and alignment, software integration, feedback actuation and scanning scheme have been carefully considered to ensure sub-100 nm gapping. To validate the design concepts, a prototyped scanning EWL imaging head is integrated into a two-beam interferometer platform for gapping tests and imaging evaluation. Experimental results show successful gap gauging at sub-100 nm with gap noise root-mean-square around 1.38 nm in static gapping and 4.64 nm in linear scanning gapping. We also demonstrate scanning imaging results with NA comparable to previously reported static imaging using both fused silica prism and sapphire prism. Our gapping and imaging results confirmed the promise of scanning EWL to extend optical lithography to sub-22 nm generations.

In the last year our Solid Immersion Lloyd's Mirror Interference Lithography (SILMIL) system has proved to be a successful tool for evanescent interferometric lithography (EIL). The initial goal was to use SILMIL in conjunction with the surface plasmon polariton (SPP) surface states at the resist-metal interface. Through this resonance, we aimed to counter the decay of evanescent images created using EIL. By analyzing the theory in greater detail we were able to develop a better understanding of the resonance phenomena. In this paper, details of the design of SILMIL and how one may utilize it to produce ultra-high numerical apertures (NAs) are given, as well as an introduction to the resonance phenomena and the mechanism behind it. We introduce a new method that requires a gain medium (one that has a negative loss) to achieve significant enhancements, and present an effective gain medium by using a high-index dielectric on low-index media. We present results at λ = 405 nm using such an effective gain medium and also provide a feasible design example at the lithography standard λ = 193 nm.

We describe the theory and report the first experimental demonstration of Cavity Resonance Lithography (CRL); a double pattering (DP) technique that can generate patterns 1) with twice the spatial frequency of that of the diffraction limited lithography mask, and 2) at an offset distance that is in the farfield of the mask. CRL requires only a single exposure and development step and does not require any additional processes. With commercially available photoresists (PR) and developers, we have recorded a 32.5 nm half-pitch pattern (which is well below the diffraction limit) at an offset distance of 180 nm (which is well beyond the evanescent decay length scales) using 193 nm illumination. We also discuss strategies to improve the minimum feature size and potential implementation schemes.

As semiconductor lithography is pushed to smaller dimensions, process yields tend to suffer due to subwavelength topographical imaging effects. Three dimensional or "thick mask" effects result in such things as a pitch dependent best focus and, for alternating phase shift masks (AltPSMs), an intensity imbalance between etched and un-etched features. Corrective mask structures such as the dual trench AltPSM have been introduced to compensate for such intensity imbalances. In this work, the compensation of thick mask effects is explored using the manipulation of the pupil wavefront through the addition of spherical aberration. The wavefront has been experimentally varied through the manipulation of the lens aberration in a state of the art full field scanner. Results reveal that the influence of spherical aberration on best focus is predictable, allowing focus deviation through pitch to be tuned. Simulations further predict that aberration manipulation can provide compensation for thick mask effects by increasing the useable depth of focus for a particular set of features on both AltPSM and thicker film attenuated PSM masks. Such pupil wavefront correction has the potential to compensate for mask topography by matching thick mask effects to those of thin masks.

With 20nm production becoming a reality, research has started to focus on the technology needs for 14nm. The LELE double patterning used in 20nm production will not be able to resolve M1 for 14nm. Main competing enabling technologies for the 14nm M1 are SADP, EUV, and LELELE (referred as LE3 thereafter) triple patterning. SADP has a number of concerns of 1. density, as a layout geometry needs to stay complete as a whole, and can not be broken; 2. the complexity in SADP mask generation and debug feedback to designers; 3. the subtraction nature of the trim mask further complicates OPC and yield. While EUV does not share those concerns, it faces significant challenges on the manufacturing equipment side. Of the SADP concerns, LE3 only shares that of complexity involved in mask generation and intuitive debug feedback mechanism. It does not require a layout geometry to stay as a whole, and it benefits from the affinity to LELE which is being deployed for 20nm production. From a process point of view, this benefit from affinity to LELE is tremendous due to the data and knowledge that have been collected and will be coming from the LELE deployment. In this paper, we first recount the computational complexity of the 3-colorability problem which is an integral part of a LE3 solution. We then describe graph characteristics that can be exploited such that 3-colorability is equivalent under divide-and-conquer. Also outlined are heuristics, which are generally applied in solving computationally intractable problems, for the 3-colorability problem, and the importance in choosing appropriate worst-case exponential runtime algorithms. This paper concludes with a discussion on the new hierarchical problem that faces 3-colorability but not 2-colorability and proposals for non-3-colorability feedback mechanism.

The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A line/cut approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm.[1] Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node.[2] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the "cut" patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,4,5] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using simplified OPC beyond 20nm in small steps, eventually reaching the 16nm node. The same "cut" pattern is used for each set of simulations, with "x" and "y" locations for the cuts scaled for each step. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Experimental demonstration of the cut approach using simplified OPC and conventional illuminators will be presented with comparison to the complex OPC result. MEEF can be measured experimentally. Lines were patterned with 193nm immersion with no complex OPC. The final dimensions were achieved by applying pitch division twice.[6] Using the conditions optimized for the logic block, an SRAM block simulation and experimental results will also be presented.

Many chip design and manufacturing applications including design rules development, optical proximity correction tuning, and source optimization can benefit from rapid estimation of relative difficulty or printability. Simultaneous source optimization of thousands of clips has been demonstrated recently, but presents performance challenges. We describe a fast, source independent method to identify patterns which are likely to dominate the solution. In the context of source optimization the estimator may be used as a filter after clustering, or to influence the selection of representative cluster elements. A weighted heuristic formula identifies spectral signatures of several factors contributing to difficulty. Validation methods are described showing improved process window and reduced error counts on 22 nm layout compared with programmable illuminator sources derived from hand picked patterns, when the formula is used to influence training clip selection in source optimization. We also show good correlation with fail prediction on a source produced with hand picked training clips with some level of optical proximity correction tuning.

Although lithography conditions, such as NA, illumination condition, resolution enhancement technique (RET), and material stack on wafer, have been determined to obtain hotspot-free wafer images, hotspots are still often found on wafers. This is because the lithography conditions are optimized with a limited variety of patterns. For 40 nm technology node and beyond, it becomes a critical issue causing not only the delay of process development but also the opportunity loss of the business. One of the easiest ways to avoid unpredictable hotspots is to verify an enormous variety of patterns in advance. This, however, is time consuming and cost inefficient. This paper proposes a new method to create a group of patterns to cover pattern variations in a chip layout based on Higher-Order Local Autocorrelation (HLAC), which consists of two phases. The first one is the "analyzing phase" and the second is the "generating phase". In the analyzing phase, geometrical features are extracted from actual layouts using the HLAC technique. Those extracted features are statistically analyzed and define the "feature space". In the generating phase, a group of patterns representing actual layout features are generated by correlating the feature space and the process margin. By verifying the proposed generated patterns, the lithography conditions can be optimized efficiently and the number of hotspots dramatically reduced.

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.

Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire field through process windows. LMC is catching and reporting weak lithographic points having small process windows or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters. ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at different field locations. In this study we compare such across-field LMC verification with a reference LMC without any scanner specific data. Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots or scanner drifts and compared with wafer measurement. Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the methodology on identified critical hot spots.

Pattern selection for OPC model calibration is frequently done by image parameter space (IPS) coverage methods. These ensure that the images of the chosen test patterns cover important regions of an n-dimensional parameter space spawned by image parameters, such as minimum and maximum intensity I_min, I_max, curvature, slope and image density. But such a small number of parameters is often insufficient for finding a good set of patterns for the calibration process. We present results for the extended nPS method which ensures coverage of a high dimensional parameter space with a high number of parameters, even permitting the use of all pixels of the aerial images (n >> 1000) as parameters.

Typical OPC models focus on predicting wafer contour or CD; therefore, the modeling approach emphasizes careful determination of feature and edge locations in the photo-resist (PR) as well as the exposure threshold, so that the 'cut' model image matches the wafer SEM contours or cut-line CDs most closely. This is an exquisite approach with regard to the contour-based OPC, for the model is calibrated directly from wafer CDs. However, for other applications such as hotspot detection or assist feature (AF) printing prediction that might occur at the top or the bottom of the PR, the typical OPC model approach may not be accurate enough. Usually, these kinds of phenomenon can only be properly described by rigorous simulation, which is very time-consuming and hence not suitable for OPC. In this paper, the approach of building the OPC model with multiple image depths will be discussed. This approach references the images at the bottom and/or the top of the PR. This way, the behavior of the images which are not shown at the normal image depth can be predicted more accurately without distorting the optical model. This compromised OPC modeling approach is beneficial for runtime reduction compared to the rigorous simulation, and for better accuracy compared to conventional model. The applications for AF printing and hotspot predictions using the multiple image depth approach will be demonstrated.

Sub-Resolution Assist Features (SRAFs) are used in optical lithography to improve the manufacturing process window (PW). They are added to the mask shapes to create a denser environment that improves the printability of the target design shapes on wafer. As the critical dimensions (CDs) that need to be patterned shrink with every technology generation, SRAFs have become a critical and key component in enabling processes with manufacturable process windows. The size and placement of the SRAFs must be carefully optimized to provide the maximum benefit to the main feature while avoiding any printing on resist that could affect subsequent etching processes. The un-intended printing of assist features on wafer is a critical yield detractor and is especially pervasive in newer technology nodes, where more aggressive and more complex SRAF patterns and placement are becoming commonplace. The need for the accurate prediction of SRAF printing is therefore very important to achieve the maximum main feature process window benefit without any assist feature printing. Traditionally, the optimization of SRAF sizing and placement consisted of a set of rules obtained through the extensive analysis of wafer printability on a variety of assisted mask patterns while using Scanning Electron Microscope images of the resist surface to monitor unwanted SRAF printing. Recent advances in model-based assist feature optimization methods allow for the automated adjustment of both main feature and assist feature size and placement through simulation of the aerial image, but critically rely on the accuracy of the lithography process model to ensure non-printing of the SRAF. Lithography or Optical Proximity Correction (OPC) models usually comprising an optical and a resist model are calibrated to measurements of the resist bottom CD. These models are naturally better at predicting the printing of SRAFS that are lines in resist. When the SRAFs are holes in resist, for eg. assist features supporting main features on a dark field mask, or SRAFs supporting inverse tone features on a bright field mask, these models do not have the required accuracy in predicting SRAF printing. SRAF printability prediction has thus far been tackled by large dose adjustments to the OPC model, to match simulation to wafer results. The drawbacks of this method have been two-fold - simple dose adjustments do not accurately predict printing across various SRAF configurations and the main feature printability is compromised We present in this paper a method to calibrate and predict printing of assist features that appear as a dimpling in the resist surface, by carefully selecting the calibration data and separately tuning the model parameters for the main feature and of the SRAF printing models. With this method, we obtain a model that accurately predicts the printing of various configurations of SRAFs on wafer while still maintaining the accuracy on the main features. An analysis of the implementation of such a model in the OPC flow and the corresponding supporting results will be presented.

Photolithography simulations are widely used to predict, to analyze and to design imaging processes in scanners used for IC manufacture. The success of these efforts is strongly dependent on their ability to accurately capture the key drivers responsible for the image formation. Much effort has been devoted to understanding the impacts of illuminator and projection lens models on the accuracy of the lithography simulations [1-3]. However, of equal significance is the role of the mask models and their interactions with the illuminator models.

An enhancement to compact modeling capability to include photoresist (PR) loss at different heights is developed and discussed. A hypsometric map representing 3-D resist profile was built by applying a first principle approximation to estimate the "energy loss" from the resist top to any other plane of interest as a proportional corresponding change in model threshold, which is analogous to a change in exposure dose. The result is compared and validated with 3D rigorous modeling as well as SEM images. Without increase in computation time, this compact model can construct 3D resist profiles capturing resist profile degradation at any vertical plane. Sidewall angle and standing wave information can also be granted from the vertical profile reconstruction. Since this method does not change any form of compact modeling, it can be integrated to validation and correction without any additional work.

As modern photolithography feature sizes reduce, the use of sub-resolution assist features (SRAFs) to improve the manufacturing process window has become more prevalent. Beyond the assist features placement based on rules, a model based assist feature (MBAF) flow is needed to optimize the shape and the size of SRAFs, so that the process margin of the main features (MFs) is maximized. In the MBAF flow, a vital component is to build an accurate model that specifically checks the printability of SRAFs, which are supposed to leave no trace on wafer. Compared to the traditional optical proximity correction (OPC) model, the SRAF printability check model faces extra challenges, for example, the small size of SRAFs makes their direct transfer to the mask pattern more difficult, the SRAFs are usually not measurable on wafer and the worst-case SRAFs printability is typically at off-nominal conditions. In this paper, we propose an innovative binary modeling method for SRAF printability check model, which does not require the measurement of SRAFs' size on wafer and yet provides accurate prediction of SRAFs printing on wafer. In this modeling method, the binary determination of whether an SRAF prints/does not print (i.e., clean) on wafer was acquired by inspecting the SEMs taken from real wafer measurements. Then the local extrema of the signal intensity around the SRAFs was simulated and used to classify print/clean groups of SRAFs, and a special cost function was designed to separate the print SRAFs and clean SRAFs as much as possible during model calibration.

3D stacking technology using TSVs, as well as linewidth shrinking, is crucial for future progress in semiconductor devices. A new i-line exposure tool, the FPA-5510iV, has been developed which provides the functions necessary for implementing TSV processes. This paper reports on Canon's commitment to make advanced TSV processes a reality.

193nm ArF eximer lasers are expected to continue to be the main solution in photolithography, since advanced lithography tecnologies such as Multiple patterning and Self-aligned double patterning (SADP) are being developed. In order to appliy these tecnologies to high-volume semiconductor manufactureing, the key is to contain chip manufactureing costs. Therefore, improvement on Reliability, Availability and Maintainability of ArF excimer lasers is important.[1] We works on improving productivity and reducing downtime of ArF exmer lasers, which leads to Reliability, Availability and Maintainability improvemnet. First in this paper, our focus drilling tecnique, which increases depth of focus (DoF) by spectral bandwidth tuning is introdueced. This focus drilling enables to increase DoF for isolated contact holes. and it not degrades the wafer stage speed.[2] Second, a technique which eables to reduce gas refill time to zero is introduced. This technique reduces downtime so Availavility is expected to improve. In this paper, we report these tecniques by using simulation resutls and partially experimental resutls provided by a semiconductor manufacturer.

Deep UV (DUV) lithography is being applied to pattern increasingly finer geometries, leading to solutions like double- and multiple-patterning. Such process complexities lead to higher costs due to the increasing number of steps required to produce the desired results. One of the consequences is that the lithography equipment needs to provide higher operating efficiencies to minimize the cost increases, especially for producers of memory devices that experience a rapid decline in sales prices of these products over time. In addition to having introduced higher power 193nm light sources to enable higher throughput, we previously described technologies that also enable: higher tool availability via advanced discharge chamber gas management algorithms; improved process monitoring via enhanced on-board beam metrology; and increased depth of focus (DOF) via light source bandwidth modulation. In this paper we will report on the field performance of these technologies with data that supports the desired improvements in on-wafer performance and operational efficiencies.

Pattern shrinks using multiple patterning techniques will continue to the 22nm half pitch (HP) node and beyond. The cutting-edge Nikon NSR-S621D immersion lithography tool, which builds upon the technology advancements of the NSR-S620D [1], was developed to satisfy the aggressive requirements for the 22 nm HP node and subsequent generations. The key design challenge for the S621D was to deliver further improvements to product overlay performance and CD uniformity, while also providing increased productivity. Since many different products are made within an IC manufacturing facility, various wafer process-related issues, including the flatness or grid distortion of the processed wafers and exposure-induced heating had to be addressed. Upgrades and enhancements were made to the S620D hardware and software systems to enable the S621D to minimize these process-related effects and deliver the necessary scanner performance. To enable continued process technology advancements, in addition to pattern shrinks at the most critical layers, resolution for less critical layers must also be improved proportionally. As a result, increased demand for dry ArF instead of KrF scanners is expected for less critical layers, and dry ArF tools are already being employed for some of these applications. Further, multiple patterning techniques, such as sidewall double patterning, actually enable use of dry ArF instead of immersion scanners for some critical layers having relaxed pattern resolution requirements. However, in order for this to be successful, the ArF dry tool must deliver overlay performance that is comparable to the latest generation immersion systems. Understanding these factors, an ArF dry scanner that has excellent overlay performance could be used effectively for critical layers and markedly improve cost of ownership (CoO). Therefore, Nikon has developed the NSR-S320F, a new dry ArF scanner also built upon the proven S620D Streamlign platform. By incorporating the Streamlign innovations, sufficient overlay accuracy for critical layers, as well as maximized productivity can be achieved. Furthermore, CoO will be significantly improved, which is the vital benefit when comparing ArF dry vs. immersion scanners. In this paper / presentation the latest S621D and S320F performance data will be introduced.

Immersion lithography is being extended to 22-nm and even below. Next to generic scanner system improvements, application specific solutions are needed to follow the requirements for CD control and overlay. Starting from the performance budgets, this paper discusses how to improve (in volume manufacturing environment) CDU towards 1-nm and overlay towards 3-nm. The improvements are based on deploying the actuator capabilities of the immersion scanner. The latest generation immersion scanners have extended the correction capabilities for overlay and imaging, offering freeform adjustments of lens, illuminator and wafer grid. In order to determine the needed adjustments the recipe generation per user application is based on a combination wafer metrology data and computational lithography methods. For overlay, focus and CD metrology we use an angle resolved optical scatterometer.

The pursuit of even smaller transistors has pushed some technological innovations in the field of lithography. In order to continue following the path of Moore's law, several solutions were proposed: EUV, e-beam and double patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20nm and 14nm nodes, double patterning lithography will play an important role for these nodes. In this work, we had focused on Self- Aligned Double-Patterning processes which consist in depositing a spacer material on each side of a mandrel exposed during a first lithography stepmaking the pitch to be divided by two after transfer into the substrate, the cutting of unwanted patterns being addressed through a second lithography exposure. In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its profiles as it could induce final CD errors or even spacer collapse. In this work, we will first study with a simple model the influence of the resist profile on the post-etch spacer CD. Then we will show that the placement of Sub-Resolution Assist Features (SRAF) can influence the resist profile and finally, we will see how much control of the spacer and inter-spacer CD we can achieve by tuning SRAF placement.

Critical aspect ratio induced pattern collapse has been a concern for lithography process engineers since before the 180 nm node. This line bending can lead to pattern deformation or complete substrate adhesion failure. Several process improvements, such as surfactant-laced final rinse, have been proposed to alter surface energies and increase the critical aspect ratio for collapse. The challenge is more severe for sub-60 nm pitch ground-rules that are being developed for the 14 nm technology node, since 30nm and smaller spaces will produce extremely large capillary forces acting on very narrow resist patterns. In previous studies, an analytical model was used to predict pattern collapse of simplified line/space structures. In this work, we propose a new framework to predict pattern collapse of sub-60 nm pitch EUV resist structures by the use of a semi-empirical model. This semi-empirical model is derived from the one-dimensional analytical model, which includes a term dependent on the local pattern geometry and the physical properties of the resist and rinse solution. We calibrate/verify the model with various EUV pattern collapse data collected from onedimensional (e.g., line/space) patterns. Hotspots predicted by the semi-empirical model are compared with those obtained from EUV wafer exposures. Weaknesses in model prediction were then used to adjust the model terms. Determining pattern collapse and identifying hot-spots early in the development cycle is critical for setting restricted design rules and refining DFM/RET solutions.

Calibration of mask images on wafer becomes more important as features shrink. Two major types of metrology have been commonly adopted. One is to measure the mask image with scanning electron microscope (SEM) to obtain the contours on mask and then simulate the wafer image with optical simulator. The other is to use an optical imaging tool Aerial Image Measurement System (AIMS^TM) to emulate the image on wafer. However, the SEM method is indirect. It just gathers planar contours on a mask with no consideration of optical characteristics such as 3D topography structures. Hence, the image on wafer is not predicted precisely. Though the AIMS^TM method can be used to directly measure the intensity at the near field of a mask but the image measured this way is not quite the same as that on the wafer due to reflections and refractions in the films on wafer. Here, a new approach is proposed to emulate the image on wafer more precisely. The behavior of plane waves with different oblique angles is well known inside and between planar film stacks. In an optical microscope imaging system, plane waves can be extracted from the pupil plane with a coherent point source of illumination. Once plane waves with a specific coherent illumination are analyzed, the partially coherent component of waves could be reconstructed with a proper transfer function, which includes lens aberration, polarization, reflection and refraction in films. It is a new method that we can transfer near light field of a mask into an image on wafer without the disadvantages of indirect SEM measurement such as neglecting effects of mask topography, reflections and refractions in the wafer film stacks. Furthermore, with this precise latent image, a separated resist model also becomes more achievable.

After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle MTT and wafer intra-field MTT is shown for ENG process without polarization. The influence of different exposure conditions - with and without polarization of scanner laser source - on the average CD value for isolated and dense structures is demonstrated.

At high-utilization lithography sites, laser light source gas replenishments and gas maintenance operations typically require between 9 and 16 hours per year, during which the light source is unavailable for production. Reducing this downtime is important for increasing the productivity of the lithography cell. Light sources also require intermittent gas maintenance that must be performed manually and therefore can be subject to variability in duration and repeatability. This paper will outline the targeted improvements in availability achieved by equipping the light source with Cymer's iGLX^TM Gas Management System. The iGLX System extends the pulse-based interval between gas refills to 4 billion pulses for Cymer's XLA-series and XLR-series light sources, while maintaining existing performance. Additionally, the iGLX System automates some gas maintenance events that were previously manual, improving their speed and reducing variability. This paper will provide some performance data during extended light source operation on lithography cells equipped with the iGLX System. For high-utilization lithography cells, the iGLX System can reduce gas maintenance related downtime by up to 75%, increasing light source availability up to 12 hours per year. Total halogen gas usage can also be reduced by up to 16%, and manual gas maintenance events can be eliminated. The iGLX System has been installed on multiple high-volume scanner systems, which experienced these improvements immediately, and are continuing to operate nominally. As the iGLX System is deployed in volume, additional availability improvements can be realized by more readily synchronizing other lithography line maintenance events with gas replenishment events.

A two-step full-chip simulation method for optimization of sub-resolution assist feature placement in a random logic Contact layer using ArF immersion Lithography is presented. Process window, characterized by depth of focus (DOF) , of square or rectangular target features is subject to optimization using the optical and resist effects described by calibrated models (Calibre ® nmOPC, nmSRAF simulation platform). By variation of the assist feature dimension and their distance to main feature in a test pattern, a set of comprehensive rules is derived which is applied to generate raw assist features in a random logic layout. Concurrently with the generation of the OPC shapes for the main features, the raw assist feature become modified to maximize process window and to ensure non-printability of the assist features. In this paper, the selection of a test pattern, the generation of a set of "golden" rules of the raw assist feature generation and their implementation as well as the assist feature coverage in a random logic layout is presented and discussed with respect to performance.

In the past ZERODUR® was mainly used for mirror and substrate applications, where mechanical loads were given by its own weight. Nowadays substrates become more sophisticated and subject to higher stresses as consequences of high operational accelerations or vibrations. The integrity of structures such as reticle and wafer stages e.g. must be guaranteed with low failure probability over their full intended life time. Their design requires statistically relevant strength data and information. The usual way determining the design strength employs statistical Weibull distributions obtained from a set of experimental data extrapolating the results to low acceptable failure probability values. However, in many cases this led to allowable stress values too low for the intended application. Moreover, the experimental basis has been found to be too small for reliable calculations. For these reasons measurement series on the strength of ZERODUR® have been performed with different surface conditions employing a standardized ring-on-ring test setup. The numbers of specimens per sample have been extended from about 20 to 100 or even much more. The results for surfaces ground with different diamond grain sizes D151, D64 and D25 as well as for etched surfaces are presented in this paper. Glass ceramics like all glassy materials exhibit some strength reduction when being exposed to loads above a tensile stress threshold over long time periods. The strength change of ZERODUR® with time will be discussed on the basis of known and newly determined stress corrosion data. The results for samples with large numbers of specimens contribute new aspects to the common practice of extrapolation to low failure probability, since they provide evidence for the existence of minimum strength values depending on the structures surface conditions. For ground surfaces the evidence for minimum strength values is quite obvious. For etched surfaces minimum values are to be expected also. However, here closer observation is still needed. The systematic deviations from Weibull distributions lie below about 5 % failure probability and thus could not be seen in small samples as they were common in the past.

As mask feature sizes have shrunk well below the exposure wavelength, the thin mask of Kirchhoff approximation breaks down and 3D mask effects contribute significantly to the through-focus CD behavior of specific features. While full-chip rigorous 3D mask modeling is not computationally feasible, approximate simulation methods do enable the 3D mask effects to be represented. The use of such approximations improves model prediction capability. This paper will look at a 28nm darkfield and brightfield layer datasets that were calibrated with a Kirchhoff model and with two different 3D-EMF models. Both model calibration accuracy and verification fitness improvements are realized with the use of 3D models.

Process yield is a critical factor for a success of 300mm manufacturing. Typically, higher yield corresponds to lower defect counts within the respective processing steps (lithography, etch, plating, and CMP). Within BEOL lithographic processes, there are issues of defects within same lithographic technology and there are concerns of defects between the generation of lithographic technologies, for example, immersion, 193nm "dry", and DUV (248nm). In order to have an effective defect reduction strategy, defects have to be monitored, identified, and analyzed for points of origins. In this paper, we explore three areas of interests in the BEOL: 1) defects occur between different processing steps, specifically, after Immersion Lithography, after Reactive Ion Etch (RIE), and after Chemical Mechanical Polish (CMP), 2) defects after CMP between lithographic technologies (Immersion, Dry, and DUV), and finally 3) defects between different devices. We were able to find evidence of transferable processing defects.

Control of CD uniformity is a key aspect of IC manufacturing. Ability to accurately predict wafer-measured CD prior to exposure is critical to CDU control. In this paper we present a method to calculate a predicted CD value based on in-situ measurements, and estimate CD uniformity across the field of an exposure tool. This method is based on direct measurements of aerial image using a sensor built into the wafer stage of SMEE SSA600-series exposure scanners. Using this sensor to measure image of several features at 9 points across the exposure field, we compare predicted CD and ADI CD obtained using a standard wafer process and CD-SEM.

With the delay in commercialization of EUV and the abandonment of high index immersion, Fabs are trying to put half nodes into production by pushing the k1 factor of the existing scanner tool base as low as possible. A main technique for lowering lithographic k1 factor is by moving to very strong offaxis illumination (i.e., illumination with high outer sigma and a narrow range of illumination angles), such as Quadrapole (e.g., C-Quad), custom or even dipole illumination schemes. OPC has generally succeeded to date with rule-based techniques for dissecting edges into segments and placing target points. Very strong off-axis illumination, however, creates pronounced ringing effects on 2D layout and this makes these simpler dissection techniques problematic. In particular, it is hard to prevent overshoot of the contour around corners while simultaneously dampening out the ringing further down the feature length. In principle, a sufficiently complex set of rules could be defined to solve this issue, but in practice this starts to become un-manageable as the time needed to generate a usable recipe becomes too long. Previous implementations of inverse lithography demonstrated that good CD control is possible, but at the expense of the mask costs and other mask synthesis complications/limitations. This paper first analyzes the phenomenon of ringing and the limitations seen with existing simpler target placement techniques. Then, different methods of compensation are discussed. Finally, some encouraging results are shown with some model based techniques that the authors have investigated, some of which only demand incremental changes to the existing OPC framework. The results show that new OPC techniques can be used to enable successful use of very strong off-axis illumination conditions in many cases, to further reduce lithographic k1 limits.

Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error enhancement factor (MEEF) can be achieved. In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band were improved by 13%, 17% & 12%, respectively with the optimum SMO source. In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC. By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized source was verified on silicon.

Source optimization (SO) becomes increasingly important to resolution enhancement in sub-32 nm lithography nodes because the dense pattern configurations significantly limit the capability of mask correction. A key step in SO is the image formation by Abbe's method, which is a linear operation of integrating all source points' images incoherently to form aerial images. However, the aerial images are usually converted to resist images through the nonlinear sigmoid function. Such operation loses the merit of linearity in optimization and leads to slow convergence and time-consuming calculation. In this paper we propose a threshold-based linear resist model to replace the sigmoid model in SO. The effectiveness of our proposed model can be clearly seen from mathematical analysis. We also compare results based on linear and sigmoid models. Highly similar optimal sources are obtained, but the linear model has a significant advantage over the sigmoid in terms of convergence rate and simulation time. Furthermore, the process variations characterized by exposure-defocus (E-D) windows are still in similar trends for optimal sources based on two different resist models.

The OPC verification problems tend to get more complicated in terms of coding complexity and TAT (turnaround time) increase as the gate length get smaller. A well known example of coding complexity is waivers (OPC verification errors that are priory known to be safe on silicon) detection and elimination. Potential locations for hot spots extraction as well could be a time consuming process if executed on full chips. And finally, OPC verification flows run time is sometimes even larger than OPC runs. In this work, we introduce the use of pattern matching as a potential solution for many verification flows problems. Pattern matching offers a great TAT advantage since it is a DRC based process, thus it is much faster than time consuming LITHO operations. Also, its capability to match geometries directly and operability on many layers simultaneously eliminates complex SVRF coding from our flows. Firstly, we will use the pattern matching in order not to run OPC verification on basic designs identified by the OPC engineer to be error free, which is a very useful technique especially in Memory designs and improves the run time. Then, it will be used to detect waivers, which is hard to code, while running verification flows and eliminate it from the output, and consequently the reviewer will not be distracted by it and concentrate on real errors. And finally, it will be used to detect hot spots in a separate very quick run before standard LITHO verification run which gives the designer/OPC engineer the opportunity to fix design/OPC issues without waiting for lengthy verification flows, and that in turns further improves TAT.

Mask aligners were the dominating lithography tool for the first 20 years of semiconductor industry. In the 1980s industry changed over to projection lithography. However, mask aligners were never sorted out and still today hundreds of new mask aligners are sold each year. This continuing success of mask aligner lithography is due to two basic trends in lithography: (a) Costs for leading-edge lithography tools double approximately every 4.4 years; and (b) the number of lithography steps per wafer was increasing from a few litho layers to more than 35 layers now. This explains why mask aligners, a very cost-effective solution for uncritical litho layers, are still widely used today. In over 50 years of semiconductor industry the mask aligner system has changed tremendously. However, only little effort was undertaken to improve the shadow printing process itself. We now present a new illumination system for mask aligners, the MO Exposure Optics (MOEO), which is based on two microlens-type Köhler integrators located in Fourier-conjugated planes. The optics stabilizes the illumination against misalignment of the lamp-to-ellipsoid position. It provides improved light uniformity, telecentric illumination and allows freely shaping the angular spectrum of the illumination light by spatial filtering. It significantly improves the CD uniformity, the yield in production and opens the door to a new era of Advanced Mask Aligner Lithography (AMALITH), where customized illumination, optical proximity correction (OPC), Talbot-lithography, phase shift masks (AAPSM) and source mask optimization (SMO) are introduced to mask aligner lithography.

High quality and highly uniform illumination is a critical component for advanced lithography systems and wafer inspection tools. Homogenizer elements fabricated in calcium fluoride have demonstrated good performance for deep UV applications. Grayscale photolithography allows for the fabrication of single-sided micro lens array (MLA) elements with excellent optical performance. The MLA offers some significant advantages over crossed cylinders fabricated using grayscale photolithography processes, including the reduction in the number of fabrication steps and the added flexibility of manufacturing noncylindrical surface geometries. This research presentation reviews the fabrication process and compares grayscale crossed cylindrical arrays and MLAs in terms of their capabilities and performance.

Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated, which show that within the common resolution capability, SATP technique is the most cost effective while the EUV+SADP approach only offers limited benefits.

We present a rigorous numerical model to study the near-field characteristics of the focused spot embedded in a Super Resolution Near Field stack layer. The results indicate that a focused spot beyond the diffraction limit can be achieved and its characteristics can be modeled by proper choice of optical parameters.

Conventional top-hat model of polarized illumination loses its accuracy in lithography simulation which cannot meet the requirements of 45nm node lithography and beyond. The simulation error of top-hat model in evaluating lithography performance cannot be neglected anymore. In this paper, we apply a Gaussian model to represent the non-uniform degree of polarization (NU-DOP) distribute across the pupil and evaluate its impact on the CD uniformity under various conditions. The result shows that the model can accurately evaluate the non-uniform property of polarized illuminator. When the mean NU-DOP approaches to 1, the effect of non-uniformity becomes more pronounced. Furthermore, the non-uniform of DOP distribution causes more CD error at defocus position.

Polarization aberration is usually represented by Jones pupil with two-dimensional (2D) format in local coordinate system. People transform the 2D polarization aberration into global coordinate system for three-dimensional (3D) imaging simulation by using mathematical coordinate transformation, rather than 3D polarization aberration defined by physics, which results in a lack of precision of 3D imaging simulation. In this paper, a new representation of 3D polarization aberration is introduced. Then the 3D polarization aberration of a hyper-NA lithography optics is extracted that is available to precisely describe the polarization properties of the optics and evaluate the 3D vector imaging performance without additional mathematical coordinate transformation. 3D polarization aberration of this paper avoids the errors of transforming 2D polarization aberration into global coordinate system mathematically.

Based on the in-line metrology sampling and modeling, the Advanced Process Control (APC) system has been widely used to control the combined effects of process errors. With the shrinking of overlay budgets, the automated optimized overlay management system has already been necessary. To further improve the overlay performance of SMEE SSA600/10A exposure system, the overlay manager system (OMS) is introduced. The Unilith software package developed by SMEE included in the OMS is used for the decomposition and analysis of sampled data. Several kinds of correction methods integrated in the OMS have been designed and have demonstrated effective results in automated overlay control. To balance the overlay performance and the metrology time, the exponential weighting method for sampling is also considered.

As the technology advances, OPC run time turns to be a big concern and a great deal of our efforts is directed towards speeding up the LITHO operations. In addition, the OPC simulation consistency is sometimes deteriorated which is a critical issue especially for anchor features. On the other hand, full chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC recipes, which is evident for instance for memory design and processor chips. The model based OPC technique is not necessary for such designs provided that the equivalent mask shapes for one cell of these arrays are already known. In this work, we introduce a combined approach using model and pattern based OPC. Pattern matching is used to extract regions from full chips that match the basic designs stored in pre-created libraries. When matching occurs, OPC solution stored in these libraries is used and populated across matched areas. Special treatment for large array boundaries is applied due to proximity effects. Model based OPC is used for the rest of the chip. This approach has two main advantages. First, simulation consistency is greatly improved since the OPC solution for standard cells is priory known. Also, pattern matching is a DRC based tool and thus it is very fast compared to LITHO operations and hence TAT is further enhanced.

Immersion scanner performance is being improved generation by generation. Faster scan speed is required to increase scanner productivity. There are, however, several papers reporting defect increase with higher scan speed^{1, 2, 3}. To overcome this challenge, both material and immersion scanner requires special tuning and optimization. This high stage speed is possible by employing topcoats that have higher hydrophobicity. In general, blob defect are generated at a higher rate with increase in hydrophobicity of topcoat. Nikon and JSR have collaborated to address this challenge by using next generation scanner and a newly developed topcoat material, respectively. JSR, as a topcoat supplier, introduces a new topcoat (TCX279), which shows low blob defects even with very high hydrophobicity. Nikon's latest immersion scanner S621D, equipped with latest nozzle design for optimizing immersion water flow, and an improved tandem stage system to reduce edge particles, resulted in achieving 5x defect reduction compared to S620D. Ultimately, zero immersion defects were realized by a combination of Nikon's S621D scanner and JSR's new topcoat, TCX279.

×We report a computation of the partially coherent imaging with a polarized illumination using an improved SVD algorithm applied to the stack pupil shift matrix computation method. The case of a polarized source is taken into account by directly stacking the x-, y- and z-direction stack pupil shift operator. The polarization of the source is described with a 22 coherency matrix which is decomposed into two independent polarization modes with certain weights determined by the polarization. For each of the polarization, we compute the stack pupil shift function in each of the x-, y- and z-direction. For a fast computation the aerial image, the SVD algorithm is applied to each of the polarized directional kernel. In this way, the total complexity of the SVD computation is reduced. To compute the full mask image, we compute the sum of convolution of the eigenvectors of each of the kernels and a 2D mask. For a fast decaying spectrum of the stack pupil shift matrix, we make the truncation of the sum with an estimate of the global precision. In a test with an annular source, we design a mask pattern. The result in the zero polarization case of our computation agrees with that of a computation with the Prolith® simulator.

With ever decreasing of feature sizes, the measurement of lens aberration has become increasingly important for the imaging quality control of projection lithographic tools. In this paper, we propose a method for in-situ aberration measurement based on a quadratic aberration model, which represents the bilinear relationship between the aerial image intensity and the Zernike coefficients. The concept of cross triple correlation (CTC) is introduced, so that the quadratic model can be calculated in a fast speed with the help of fast Fourier transform (FFT). We then develop a method for the Zernike coefficients characterization using the genetic optimization algorithm from the through focus aerial images of a nine contacts mask pattern. Simulation results demonstrate that this method is simple to implement and will have potential applications for in-situ metrology of lens aberration in lithographic tools.

Optical proximity correction (OPC) and phase shifting mask (PSM) are the most widely used resolution enhancement techniques (RET) in the semiconductor industry. Recently, a set of OPC and PSM optimization algorithms have been developed to solve for the inverse lithography problem, which are only designed for the nominal imaging parameters without giving sufficient attention to the process variations due to the aberrations, defocus and dose variation. However, the effects of process variations existing in the practical optical lithography systems become more pronounced as the critical dimension (CD) continuously shrinks. On the other hand, the lithography systems with larger NA (NA>0.6) are now extensively used, rendering the scalar imaging models inadequate to describe the vector nature of the electromagnetic field in the current optical lithography systems. In order to tackle the above problems, this paper focuses on developing robust gradient-based OPC and PSM optimization algorithms to the process variations under a vector imaging model. To achieve this goal, an integrative and analytic vector imaging model is applied to formulate the optimization problem, where the effects of process variations are explicitly incorporated in the optimization framework. The steepest descent algorithm is used to optimize the mask iteratively. In order to improve the efficiency of the proposed algorithms, a set of algorithm acceleration techniques (AAT) are exploited during the optimization procedure.

Recently, a set of gradient-based optical proximity correction (OPC) and phase shifting mask (PSM) optimization methods have been developed to solve for the inverse lithography problem under scalar imaging models, which are only accurate for numerical apertures (NA) less than approximately 0.4. However, as the lithography technology node enters the 45nm realm, immersion lithography systems with hyper-NA (NA>1) are now extensively used in the semiconductor industry. For the hyper-NA lithography systems, the vector nature of the electromagnetic field must be taken into account, leading to the vector imaging models. Thus, the OPC and PSM optimization approaches developed under the scalar imaging models are inadequate to enhance the resolution in the immersion lithography systems. This paper focuses on developing gradient-based OPC and PSM optimization algorithms under vector imaging models. The mask optimization framework is first formulated, in which the imaging process of the optical lithography system is represented by an integrative and analytic vector imaging model. The steepest descent algorithm is then used to optimize the mask iteratively. Subsequently, a generalized wavelet penalty (GWP) is proposed to improve the manufacturability of the mask, and results in smaller pattern errors and CD errors than the traditional wavelet penalty (WP). Finally, a set of algorithm acceleration techniques are exploited to speed up the proposed algorithms.

State of the art Extreme Ultra Violet Lithography (EUVL) gives high hope for further shrinkage of semiconductor devices, but currently, EUVL is not ready for 2xnm node manufacturing and ArF immersion must extend its capability in manufacturing 2xnm devices. Extending the limit of ArF requires varieties of Resolution Enhancement Techniques (RET) such as inverse lithography (ILT) , double patterning (DPT), spacer patterning and so on. One of the brightest candidate for extension of ArF for contact layer is negative tone development (NTD), since this process utilizes the high contrast of the inverse tone of the mask for patterning. NTD usually results in high process margin compared to conventional positive tone development (PTD) process1. Therefore, in this paper we will study application of NTD from optical proximity correction (OPC) and simulation perspective. We will first discuss difference of NTD from PTD. We will also discuss on how to optimize NTD process in simulation perspective, from source optimization to simulation calibration. We will also discuss what to look out for when converting PTD process to NTD process, including OPC models to design rule modification. Finally, we will demonstrate the superiority of NTD process through modeling and simulation results with considering these factors mentioned above.

A typical post-out flow data path at the IC Fabrication has following major components of software based processing - Boolean operations before the application of resolution enhancement techniques (RET) and optical proximity correctin (OPC), the RET and OPC step [etch retargeting, sub-resolution assist feature insertion (SRAF) and OPC], post-OPCRET Boolean operations and sometimes in the same flow simulation based verification. There are two objectives that an IC Fabrication tapeout flow manager wants to achieve with the flow - predictable completion time and fastest turn-around time (TAT). At times they may be competing. There have been studies in the literature modeling the turnaround time from historical data for runs with the same recipe and later using that to derive the resource allocation for subsequent runs. [3]. This approach is more feasible in predominantly simulation dominated tools but for edge operation dominated flow it may not be possible especially if some processing acceleration methods like pattern matching or hierarchical processing is involved. In this paper, we suggest an alternative method of providing target turnaround time and managing the priority of jobs while not doing any upfront resource modeling and resource planning. The methodology then systematically either meets the turnaround time need and potentially lets the user know if it will not as soon as possible. This builds on top of the Calibre Cluster Management (CalCM) resource management work previously published [1][2]. The paper describes the initial demonstration of the concept.

In lithographic scanner, many different physical factors could impact to image quality and CD uniformity. In optical systems, the pupil filling quality (source shape), wavefront error and stray light can decrease the intensity contrast and shrink the process window. In mechanical domain, the vibration and scanning synchronization error have the similar effect to imaging process. Imaging in scanner is a dynamic exposure process and in this process, aerial image should keep the same relative position to the wafer. It requests the lithographic tool must have a very stable mechanical frame and very good motion control performance. In addition, the wafer stage, reticle stage's coordinate and projection lens' grid should be matched exactly, include the scanning direction and velocity ratio. The tool's alignment system can calibrate the statistic coordinate for overlay, but it cannot calibrate the dynamic coordinate in scanning direction very well because projection lens' grid has a small asymmetric signiture. This systematic error should be calibrated for CDU improvement. An imaging model considering the motion blurring is represented in this paper and based on this model, the dynamic coordinate's error could be analyzed. Furthermore, exposure method can be used to calibrate the dynamic coordinate and improve the CD uniformity. Exposure latitude will be used to check and calibrate the lithographic tool's dynamic coordinate. We designed a special calibration process to obtain the best dynamic coordinate setting for scanner. In this process, some tool's coordinate parameters (scanning skew and scale) have been changed for every field to obtain the multi-dimensions' exposure information. Exposure window can be represented from this result, and in this exposure window, the best dynamic coordinate setting could be found. After the dynamic coordinate calibrated, the CDU is improved.

The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these applications. The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust 28nm node and prepare for 20nm. These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print check, aka LFD, for 28nm P&R.

As semiconductor process technology moves to smaller dimension, RET (resolution enhancement technology) becomes more and more important, especially in low k1 processes. From 28nm node to 20nm node, the k1 becomes smaller with smaller dimension and pitch because exposure tool can provide larger NA (numerical aperture) or smaller exposure wavelength. SMO (source mask optimization) is a RET solution for low k1 process and provide better lithographic common process window in single exposure technology. Base on our studies of aerial image simulation and real wafer experiments on 20nm node, SMO could provide a better solution for 20nm node with 1.35 NA and 193nm exposure wavelength than the other RET sources (Quasar, C-Quad., Dipole). In the first step, the concerned patterns are important for the optimization because the main purpose of SMO is to obtain better performance in those. Through SMO iteration, we can find out a better source for our design rule and concerned patterns (like SRAM, and Small Island patterns). Then, we evaluate whether the simulation results can provide enough accuracy from real wafer data. Base on this study, we can develop a suitable SMO process for 20nm node. In this paper, we will show the optical theory, simulation result and wafer performance of SMO technology.

The mask error budget continues to shrink with device pitch. In advance node, mask error enhancement factor (MEEF) will increases up to over 4. The impact of assistant feature size on main feature CD variation becomes more obvious than before. Generally, sub-resolution assist feature (SRAF) use is an indispensable technique to provide adequate depth of focus (DOF) for larger pitches on layers with lithography settings that are optimized for denser pitches. But, SRAF width will be critical issue with shrinking design rule. We investigated the impact of the assist feature size on through pitch patterns. Using M3D (mask 3Dimension) model of Prolith simulation tool, we simulate the main pattern variation by adjusting assistant feature size [1]. SRAF printability also be concerned through simulation and be verified by real wafer printing result. We show that the wafer CD impact that come form mask CD variation of main feature and the influence of assistant feature size on dense main feature become more and more.

Multiple patterning is the only known way to extend current 193 nm immersion-based optical lithography beyond 40 nm half-pitch. A highly effective technique for multiple patterning uses self-aligned etched spacers to define the tightest pitch lines as critical features. However, to complete the patterning, the lines must be cut with at least one separate additional exposure. In order to reduce the costs associated with multiple cut locations, it is proposed to group the locations into portions of larger features. Specifically, the cut locations can be the intersection of the spacer lines and the overlap of at least two polygons of opposite exposure polarity. The cost reduction is determined by the reduced number of exposures, as well as the looser pitch and dimensions of the exposures. Besides cost reduction, greater immunity to exposure shot noise (if EUV or EBL is used for cutting) is provided by the use of larger polygons. The benefits of complementary polarity patterning based on these key issues will be analyzed for the 10 nm half-pitch application, and extensions to even smaller half-pitches will be discussed.

High-performance objectives pose very strict limitations on errors present in the system. External mechanical influences can induce structural vibrations in such a system, leading to small deviations of the position and tilt of the optical components inside the objective from the undisturbed system. This can have an impact on the imaging performance, causing blurred images or broadened structures in lithography processes. A concept to detect the motion of the components of an optical system is presented and demonstrated on a simulated system. The method is based on a combination of optical simulation together with mechanical simulation and inverse problem theory. On the optical side raytracing is used for the generation of wavefront data of the system in its current state. A Shack-Hartmann sensor is implemented as a model to gather this data. The sensor can capture wavefront data with high repetition rates to resolve the periodic motion of the vibrating parts. The mechanical side of the system is simulated using multibody dynamics. The system is modeled as a set of rigid bodies (lenses, mounts, barrel), represented by rigid masses connected by springs that represent the coupling between the individual parts. External excitations cause the objective to vibrate. The vibration can be characterized by the eigenmodes and eigenfrequencies of the system. Every state of the movement during the vibration can be expressed as a linear combination of the eigenmodes. The reconstruction of the system geometry from the wavefront data is an inverse problem. Therefore, Tikhonov regularization is used in the process in order to achieve more accurate reconstruction results. This method relies on a certain amount of a-priori information on the system. The mechanical properties of the system are a great source of such information. It is taken into account by performing the calculation in the coordinate system spanned by the eigenmodes of the objective and using information on the spectrum of frequencies present in the current vibration as a-priori data. The position of the individual lenses as a function of time is then calculated from several frames of the wavefront data and extrapolated to future timesteps. Information on the system gathered with this method can be useful for applying and controlling countermeasures against the vibrations during use of the objective or for designing new systems that are less influenced by vibrations.

In order to improve process control of the lithography process, enhanced On-board metrology, measuring of the light source beam parameters with software solutions for monitoring, reporting and analyzing the light source's performance has been introduced. Multiple lasers in the field were monitored after installing of a new On-board metrology product called SmartPulse. It was found that changes in beam parameters can be significantly reduced at major module change service events when new service procedures and On-board metrology were used, while significant beam parameter shift and illumination pupil changes were observed when On-board metrology was not available at service events, causing lengthy scanner illumination pupil recalibration. SmartPulse^TM software from Cymer Inc. was used to monitor the variation of light source performance parameters, including critical beam parameters, at wafer level resolution. Wafer CD was correlated to the recorded beam parameters for about a month of operation, and both wafer CD and beam parameters showed stable performance when the light source was operating at optimal conditions.

In the very low k₁ regime in optical lithography, aggressive RET such as strong off-axis illumination causes significant forbidden pitches and lithography hotspots for aggressive designs. Various lithography retargeting techniques have been introduced to mitigate these process window failures. This paper proposes to bring the lithography target optimization into the Source-Mask Optimization (SMO) flow to achieve better SMO solutions at an earlier process development stage. Through this tight integration of lithography target optimization and source mask optimization, lithography target, source, and mask can be tuned together to provide the best overall process window for the newly defined targets. This improvement is demonstrated using a simple SMO test case for the 20-nm metal layer. Then at the later development stage, retargeting rules can be extracted from these optimized lithography targets, and they can be applied in the normal mask optimization process. This lithography target optimization flow can provide a faster tuning process for the lithography target rules at an early process development stage, and can provide optimized retarget rules for mask optimization process too. New challenges for retargeting in double patterning lithography are also discussed.

OPC modeling has been complex procedure in 28nm node, and it becomes difficult to obtain enough OPC modeling accuracy if calibration is done by using only CD value. Therefore it becomes essential to take pattern shape variation into consideration especially in 2D pattern calibration. Thus utilizing SEM-contour has become important technology. In SPIE advanced lithograpy 2010 [3], Contour-based OPC-modeling by using Advanced SEM-contour which is combined with Fine SEM Edge, alignment and averaging technologies was examined, and model quality was significantly improved. Also, in SPIE advanced lithography 2011, an advanced hybrid OPC modeling which uses 1D CD measurements by CD-SEM and 2D contours created by the advanced SEM-contouring technology and panoramic Mask SEM-contour showed high predictability for both 1D and 2D, even though the relationship between 1D and 2D calibration has trade-off. In this study, weighing function of Calibre ContourCal, a product of Mentor Graphics, was evaluated using the OPC data set same as that used in SPIE2011. The weighting can be set for 1D structure and 2D structure separately. In this paper, the quality of OPC model by applying different weighting is discussed.

Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge placement control budgets for junction definition shrink with each node. In addition to the traditional proximity effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls, reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an optical model representing only implant mask proximity effects and two additional optical models which represent the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD control for complex layouts, and represents only a small impact to full-chip correction runtime.

To minimize the adverse effects of polarization aberrations in the projection optical system, methods to compensate the polarization aberrations are required for high resolution lithography. In this paper, we propose a symmetric polarization aberration compensation method based on scalar aberration control for lithographic projection lens. This method focuses on the compensation of polarization aberrations induced by radially symmetric retardances. The foundation of the compensation method is the linear relationship between conventional even aberration and polarization aberration induced by radially symmetric retardances. The compensation accuracy is dependent on the even aberration adjustment accuracy of the projection lens and the sensitivity of the mask pattern to even aberrations. By this polarization aberration compensation method, the lithographic process window can be improved obviously.

We present a novel, accurate and fast algorithm to obtain Fourier series coefficients from an IC layer whose description consists of rectilinear polygons on a plane, and how to implement it using off-the-shelf hardware components. Based on properties of Fourier calculus, we derive a relationship between the Discrete Fourier Transforms of the sampled mask transmission function and its continuous Fourier series coefficients. The relationship leads to a straightforward algorithm for computing the continuous Fourier series coefficients where one samples the mask transmission function, compute its discrete Fourier transform and applies a frequency-dependent multiplicative factor. The algorithm is guaranteed to yield the exact continuous Fourier series coefficients for any sampling representing the mask function exactly. Computationally, this leads to significant saving by allowing to choose the maximal such pixel size and reducing the fast Fourier transform size by as much, without compromising accuracy. In addition, the continuous Fourier series is free from aliasing and follows closely the physical model of Fourier optics. We show that in some cases this can make a significant difference, especially in modern very low pitch technology nodes.