This PDF file contains the front matter associated with SPIE Proceedings Volume 12497, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

Ever since IBM pioneered microelectronics packaging, IBM Research has continued to innovate to ensure that packaging and heterogeneous integration technology is available to satisfy the needs for performance, complexity, and memory and logic density with regard to high performance computing systems. In this era of ever-expanding need for high-performance computing and ever-pervasive artificial intelligence, traditional scaling economics headwinds combined with the need for versatility and fast product development mandate a system-level approach to generate the efficiencies the industry has been able to provide in the past through more traditional scaling approaches. This system-level approach renders imperative the use of chiplet-based architectures and the use of heterogeneous integration and advanced packaging to achieve the disaggregation with best-performing and most efficient IP components to sustain a viable economic model while achieving performance targets. In this talk we will discuss several key process and integration considerations that drive the use of various horizontal and vertical interconnection technology elements that must be implemented to enable the successful realization of efficient and cost-effective high-performance systems in the AI era. Future progress on these technology fronts will depend on disruptive innovation in two critical areas: (a) wafer-level and die-level processes, such as lithographic patterning, wafer-wafer bonding and debonding, bond and assembly processes, etc. that can enable packaging of these heterogeneous structures without compromising performance and reliability, (b) commensurate improvements and enablement of adequate metrology and inspection solutions to address the challenges stemming from these new chiplet-interconnecting methods and the associated topographic implications.

The availability of high-resolution and high throughput lithographic fabrication technologies such as electron-beam lithography based on Variable Shaped Beam writing and Character Projection opens the way for the flexible use of various optical nano-structures for some of the most demanding applications. The paper discusses the technical features, advantages, and limitations of these pattering approaches and will show how they can favorably be combined to realize optical nano-structures for applications, which are as diverse as gratings for ultra-short laser pulses or high resolution spectrometers, computer generated holograms for asphere testing, various optical meta-structures (lenses, gratings), or UV-polarizers.

In emerging optical applications, curvilinear features increase lithography complexity, which leads to long e-beam write times. Multi beam mask writers offer a solution for high-end masks where curvilinear features are predominant. For mid-range masks and emerging optical applications especially variable shaped beam systems still offer advantages. The challenge for optical applications is to expose large-scale non-Manhattan layouts such as slanted gratings, circle arrays, or curved geometrical structures with high fidelity in an efficient way. For arbitrary curved structures, including 3D, a novel shot count optimized and edge roughness aware approximation (JES-approximation) approach by ePLACE data preparation software package (Vistec Electron Beam GmbH, Germany) is applied. In contrast to common fracturing, both throughput and pattern fidelity in optical applications are highly increased. The optical quality by means of high sensitive haze measurements of diffractive axicons is proven. For repetitive structures such as slanted gratings or circle arrays the cell projection (CP) option is the solution of choice, but CP is also effective for arbitrarily curved gratings. Key enabler is the data preparation software ePLACE where cell dose values are calculated to meet the target layout contours precisely. Both JES-approximation as well as cell projection with target contour calculation are powerful tools for an efficient data preparation and final exposure of non-Manhattan layouts.

Multibeam Corporation has overcome the productivity limitations of conventional single-electron-beam lithography to enable high-speed, flexible, and high-resolution patterning in a range of new and existing applications. The high-productivity Multicolumn Electron Beam Lithography (MEBL) system combines a modular architecture with unique miniature e-beam columns to achieve productivity that is taking e-beam lithography from lab to fab. MEBL exhibits 10 to 100x productivity in most applications compared to conventional e-beam lithography. Beyond its superior resolution, MEBL also offers several important advantages over conventional photolithography: (1) Depth of Focus – over 100x larger than state-of-the-art optical systems. (2) Full-wafer Writing Field – the ability to write unique, seamless patterns over an entire wafer, not limited by conventional optical reticle size (typically 26 mm x 33 mm). (3) Perhaps most powerfully – direct writing is maskless. E-beam lithography is adaptable and is not constrained by the time, cost, defectivity, and security risks of the optical mask production process. The design and manufacturing capabilities that emerge from combining high-productivity with these unique e-beam lithography capabilities enable many key applications: super-large interposers for microelectronics advanced packaging (that can achieve size, weight, power, and performance close to that of wafer-scale integration); seamless patterning of readout integrated circuits (ROICs) and other larger-area devices; built-in Secure Chip IDs that ensure security and chip-level traceability; and high-mix, low-volume production (to leverage high-volume IC technology for low-volume applications). The adaptable, direct-write nature of e-beam lithography also enables early concept prototyping that accelerates technology development, production ramp-up, and system deployments. These advanced capabilities are shown using Multibeam’s high-productivity, direct-write MEBL system.

Electron Beam Direct Write (EBDW or E-Beam) Lithography is a worldwide reference technology used in laboratories, universities and pilot line facilities for Research and Developments. Due to its low writing speed, E-Beam direct write has never been recognized as an acceptable industrial solution, exception made for optical mask manufacturing. Nevertheless, its natural high-resolution capability allows low-cost patterning of advanced or innovative devices ahead of their high-volume manufacturing ramp-up. Thanks to its full versatility with almost all type of chemically amplified resists, EBDW is a perfect complementary solution to optical lithography. This paper demonstrates the compatibility of EBDW lithography with advanced Negative Tone Development (NTD) resist and the possibility to set-up an hybrid E-Beam/193i lithography process flow with high performances in terms of resolution and mix & match overlay. This high-end lithography strategy alliance offers flexibility and cost advantages for device development R&D but also powerful possibilities for specific applications such circuit encryption as discussed at the end of this work-study.

The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements.

EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.

Electron multi-beam mask writers play a key role to expand EUV lithography usage in device mass production. It was in May 2021 when the MBM^TM-2000 was released by NuFlare Technology, Inc. Since then, it has been installed at sites of mask manufactures. Accordingly, it supports their mask development and production. On top of reliable inherited mask writing technologies, newly developed technologies, which have achieved objectives, enable the multi-beam writer to make many contributions. In June 2022, the MBM^TM-2000PLUS for the 2 nm node device development eventually debuted. The increased beam current density, 3.2 A/cm² allows this latest mask writer to print a mask with productive writing time even using lower sensitivity resists. A charge effect reduction (CER) is a hardware solution to reduce amount of the resist surface charge. Thanks to adapting CER2.0, which is upgrade version of CER1.0, the image placement error caused by the resist surface charge effect in the MBM^TM-2000PLUS is reduced by 50% as compared with the MBM^TM-2000 with optics CER1.0. This successor also takes over essential functions including pixel level dose correction (PLDC), charge effect correction (CEC), and glass thermal expansion correction (GTEC) from the MBM-2000. In this paper, the current performance of MBM series mask writers and the key architectures above-mentioned have been discussed. We also explain our strategies to keep continuous throughput improvement by optimizing items such as beam size, data transfer speed, beam current density and so on. Our roadmap indicates that NuFlare Technology, Inc. makes contribution to the high-NA EUV ecosystem.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity.

Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications.

DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL an attractive solution.

The purpose of this paper is to review the performance improvements related to edge placement error (EPE) for NIL. Key EPE components include overlay, local critical dimension uniformity (LCDU) and global critical dimension uniformity (GCDU). In this work, we review each component, summarize current capability and present a roadmap for improving EPE to meet future generations of DRAM devices. In addition, we present a reverse tone pattern transfer process that has the potential to further reduce GCDU and EPE for NIL.

First, Grayscale I-Line lithography process developed in CEA-Leti allows to manufacture a variety of 3D patterns based on the well-known photolithography technology. Grayscale photolithography is an innovative and alternative approach to create 3D patterns such as microlenses for example. Exposure of a low contrast resist at different doses results in different thicknesses in the resist film. The variation of the intrinsic dose is obtained by using a binary mask that has different chromium densities, thus modulating the exposure intensity on the resist surface¹. Secondly, the NanoImprint Lithography (NIL) is a technology capable of reproducing a wide morphological range. NIL is increasingly requested for the reproduction of 3D patterns. Initially, standard NIL process uses a hard master usually composed of Si or SiO₂. The proposed work validates the quality of the replication by the NanoImprint process of a "resist master" created by grayscale lithography. This approach facilitates the manufacturing process of a master by avoiding the etching step and offering a cost-effective solution. The measurement of several types of 3D patterns are performed before and after replication during this study. CD preservation is evaluated for 32 types of microlenses simultaneously replicated. Finally, the combination of the Grayscale and NanoImprint technologies allows to considerably increasing the printing possibilities. By freeing the difficulties of multiple patterns morphology conservation during the etching, the replication of a resist master permits other potential applications, particularly in the optical field.

Micro-optics are in great demand and indispensable key enabling elements in various emerging markets. High quality wafer-level micro-optics attract huge commercial interest in prestigious applications like 3D sensing and imaging for AR/VR in smart devices and automotive lighting [1]. The consumers aspire to have comprehensive functionalities on their smart gadgets, to enhance their view of the real environment by superimposing a virtual world. 3D sensing cameras with Time-of-Flight (ToF) modules provide a revolutionary virtual reality and imaging. A typical ToF module demands various highly efficient nano and micro-optical elements [2,3]. The next generation imprint equipment provided by SUSS MicroTec offers a versatile and sophisticated imprint mechanism to resolve complex microscale structures on a single imprint equipment. The advanced technical features include enhanced imprint gap measurement and a levelling mechanism, tunable forces during imprint, advanced design of microscopes for high alignment accuracy and cost-effective UV-LED flood exposure with high intensities. These comprehensive functionalities also make it possible to manufacture larger sets of stacked micro lens arrays with low aberration and minimal distortion of lens geometry. In this talk, we will present the capabilities of SUSS equipment for imprinting micro lens arrays (MLA) with alignment accuracy ≤ 1μm and less geometry variation < 1 %, over a 200 mm wafer surface. Moreover, in a high volume manufacturing environment, key to productivity are consistent and repeatable fabrication processes and operations. Therefore, we will also show the reliability of our equipment and the repeatability of producing high quality MLAs.

Precise control on nanoscale pattern manufacturing is key to enable new-generation devices in numerous fields, such as bioelectronics or optics, among others. However, to meet the requirements of the industry, it is especially relevant to increase throughput and reduce processing costs. In this regard, Nano-Imprint Lithography (NIL) is an ideal candidate for manufacturing large volumes of devices with low cost-of-ownership, by replicating small features from high-quality masters. However, NIL faces some challenges, such as limited pattern transfer fidelity in large-area processing. Here, we show our NIL processing capabilities, in terms of both yield and transfer fidelity from original DUV manufactured masters, including features from few hundred to tens of nanometers. We present an exhaustive study on the pattern evolution through the complete process, including design, master fabrication, NIL and subsequent pattern transfer via etching. This study demonstrates the inclusion of NIL into our foundry-mature, CMOS-compatible process modules as well as the pattern evolution characterization that enable technology-aware modelling and designing.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Memory fabrication is challenging, in particular for DRAM, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL attractive solution. Logic is more challenging from a defectivity perspective, often requiring defect levels significantly lower than memory devices that incorporate redundancy. In this paper, we touch on the markets that can be addressed with NIL and also describe the efforts to further improve NIL performance. We specifically focus on performance improvements related to overlay, edge placement error and defectivity. For overlay, we present results on stability and also discuss new methods to further address high order distortion. For edge placement error (EPE), we discuss progress made towards addressing EPE budgets for memory devices. For defectivity, we review random defect generation, particle adders and mask inspection methods. NIL usability cases are also examined. In addition, we also discuss Canon’s recent involvement in the New Energy and Industrial Technology Development Organization (NEDO) project and its goals related to logic devices. As a final topic, we describe Canon’s interests in fabrication beyond traditional advanced semiconductor devices.

Nanoimprint lithography (NIL) has received attention as alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost. Application of NIL may lead to the reduction of number of process steps and cost of manufacturing of dual-damascene structure, by simultaneous fabrication of holes and trenches. Therefore, in this study, we investigated fabrication of dual-damascene structure using NIL and dry-etching. However, the difficulty in dry-etching process is high as the holes and trenches are etched together using single resist mask. Suppression of defects during the NIL process and the suppression of resist consumption and CD shift during the etching process, is critical. To address these issues, we used a high etching resistance resist, optimized the NIL process to reduce defects, and optimized the template structure and etching process to suppress resist consumption and CD shift. As a result, a dual-damascene structure with L/S = 4X/4X nm was obtained.

We propose a novel approach of combined patterning technologies to manufacture individualized micro-optical components as required for the integration of system-level optical packaging, e.g. for coupling light into on-chip level waveguides. The presented work consists of an innovative combination of inkjet printing of available optical polymers onto a prepatterned substrate and UV-replication which enables the manufacturing processes for tailor-made polymeric hybrid and biconvex micro-optical components. For this, inkjet printing of the optical polymers InkOrmo or InkEpo is used as a dispensing technique for additive manufacturing. The ink is printed into designated cavities on a patterned substrate that shows either diffractive or refractive features. After UV-induced polymerization, the cured component is separated from the soft mold substrate. This results in a combination of either a diffractive and a refractive element or two convex refractive elements in one monolithic component. The refractive part on top is self-organized by the surface energy and the shape is adjusted with the amount of dispensed ink enabling to tune the refractive power of the lens. The diffractive structure or convex shape on the opposite side of the lens is obtained by replicating the shape of the prepatterned substrate. Such advanced micro-optic components allow in principle a higher degree of system integration and thus further system miniaturization by e.g. substituting a multi lens system with a single hybrid lens. This novel manufacturing concept is composed to cost-effectively implement design requirements, making tailor-made diffractive-refractive lenses easily accessible e.g. to the MEMS/MOEMS community.

Current lithographic techniques are limited to a resolution of a few nm with poor relative precision. Scanning Tunneling Microscope (STM) based lithography[1], removes H from H-passivated Si 2x1 (100) by a mode distinct from usual imaging. This technique is generally called Hydrogen Depassivation Lithography (HDL) and since it scans a beam of electrons around on a surface exposing a resist, it is a form of E-beam Lithography. The HDL approach is not effective with standard resists and, at present, has only a limited number of pattern transfer methods. The two primary ones are patterning 2D delta doped Si devices for solid state quantum devices and selective Atomic Layer Deposition metal oxides that can be used as hard etch masks. However, electron stimulated desorption of atoms and molecules is a fairly generic process and its use can be anticipated on a wide variety of substrates. Sub-nm resolution (0.768 nm) has been demonstrated and used for numerous research purposes, such as dopant positioning for quantum devices[2]. While sub-nm resolution is easily obtainable with standard Ultra-High Vacuum (UHV) STMs, the repeatability and accuracy of the patterning has limited its applications. In this paper we report on progress to dramatically scale HDL’s throughput while maintaining sub-nm resolution.

Computational ecosystems in which classical supercomputers and general-purpose quantum computers provide a steady increase in value-creating computation capabilities have shown immense progress in recent years. Superconducting qubit technology, in particular, has emerged as a leading candidate for realizing a scalable quantum computing platform ready for paving the way to commercial quantum advantage. However, current academic approaches in fabrication and testing of quantum devices are not scalable and have already started to limit the rapid development of the field. Novel solutions are required to tackle the combined challenge of increasing the qubit count on a quantum processor and the need to further reduce the qubit’s error rates. This, in turn, will lead to a renewed acceleration in qubit manufacturing, test and diagnostics. Here we present aspects of how to move superconducting qubit manufacturing and testing from small-scale laboratory to large-scale fabrication facility environments. To enable this transfer, two key ingredients are demonstrated: (i) A foundry-compatible fabrication process of superconducting qubits that can benefit from the advanced process control in industry-scale CMOS fabrication facilities, and (ii) an acceleration of testing and cryogenic measurement throughput by using a milli-Kelvin cryo-CMOS signal multiplexer operating in near proximity to quantum devices and integrated qubit diagnostic and benchmarking tools with end-to-end data analytics. Although some of these elements have been explored independently, co-development is crucial to enable an efficient scalable development cycle for quantum computing technology. A full development cycle consisting of scalable manufacturing, testing, and benchmarking will enable the large-scale fabrication and control of quantum computing devices and thus pave the way to commercial quantum advantage.

Owing to photon shot noise and inhomogeneous distribution of the molecular components in a chemically amplified resist, resist patterns defined by extreme ultraviolet (EUV) lithography tend to suffer from stochastic variations. These stochastic variations are becoming more severe as critical dimensions continue to scale down, and can thus be expected to be a major challenge for the future use of single exposure EUV lithography. Complementing EUV lithography with directed self-assembly (DSA) of block-copolymers provides an interesting opportunity to mitigate the variability related to EUV stochastics. In this work, the DSA rectification process at imec is described for both line/space (L/S) and hexagonal contact hole (HEXCH) patterns. The benefits that rectification can bring, as well as the challenges for further improvement are being addressed based on the current status of imec’s rectification process.

Directed Self-Assembly (DSA) has been reported many times in the past decade as a technique for forming fine patterns^{1- 12}. As processes for application to the semiconductor process, the grapho-epitaxy process forms a desired pattern in an isolated area using a physical guide, and the chemical-epitaxy process forms a single pitch over a wide range using a chemical guide are typical. There are many reports regarding the line pattern formation using a lamellar phase to meet the demand for miniaturization from the mass production of semiconductors, and this is partly because the lamellar phase is relatively stable. However, for fine line pattern formation, multiplication techniques such as SADP (self-aligned double patterning) and SAQP (self-aligned quadruple patterning) have matured, and in recent years, the number of cases where EUV (extreme ultra-violet) single exposure is used is increasing. For this reason, DSA is rarely used in mass production of semiconductors. On the other hand, when miniaturizing high-density hole patterns, methods such as multiple exposure and etching, and methods of forming holes by crossing line patterns formed by SADP are relatively expensive. In addition, it is difficult to maintain the uniformity of hole CD (critical dimension) and pitch. In addition, when EUV is applied, it is not easy to suppress defects and form a wide range of patterns due to stochasticity, which has become a problem in recent years. Therefore, the formation of high-density hole patterns using DSA is attracting attention. In DSA, the hole diameter can be controlled by the molecular weight of BCP (block co-polymer), and the pitch tends to be uniform spontaneously. Also, if the chemical-epitaxy process is used, the pattern can be formed over a wide range. However, hole patterns using a cylinder phase tend to have large fluctuations in hole diameter and placement due to the high degree of freedom in placement. It is also important to what extent the established process can be extended to further miniaturization. In this presentation, we report on the hole pattern formation method by the chemo-epitaxy method and efforts to improve the fidelity for application to the semiconductor process.

For printing the most critical features in semiconductor devices, single exposure extreme ultraviolet (EUV) lithography is quickly advancing as a replacement for ArF immersion-based multipatterning approaches. However, the transition from 193 nm to 13.5 nm light is severely limiting the number of photons produced by a given source power, leading to photon shot noise in EUV patterns. In addition, inhomogeneous distribution of components inside conventional photoresists is adding to the printing variability, especially when critical dimensions continue to shrink. As a result, stochastic issues leading to rough, non-uniform, and potentially defective patterns have become a major challenge for EUV lithography. A promising solution for this top-down patterning approach is complementing it with bottom-up directed self-assembly (DSA) of block copolymers. In combination with 193i lithography, DSA of lamellae forming block copolymers has previously shown favorable results for defining dense line-space patterns using LiNe flow.¹ In this study, we investigate the complementarity of EUV + DSA for rectification of pitch 28 nm line-space patterns. Roughness and defectivity are critical factors that need to be controlled to make these patterns industrially relevant. We look at the impact of DSA material and processing parameters on line edge roughness and line width roughness in order to identify and mitigate the origins of pattern roughness. On the other hand, we also assess the different types of defect modes that are observed by means of optical defect inspection and ebeam review, and study the root causes for their formation. To wrap-up, the benefits of 1X DSA versus 3X DSA are presented by comparing EUV + DSA to LiNe flow.

Roll-to-roll nanoimprint lithography offers a method to scale functional micro and nanopatterned surfaces for a wide array of applications. However, creating a sufficiently large, seamless drum mold is still often prohibitively expensive or impossible. This patterning becomes especially difficult when the periodicity of the pattern is smaller than half the wavelength of visible light, the limit for UV interference lithography. High-speed indentation via a novel process called “Nanocoining” has been demonstrated to overcome this issue. Thus far, Nanocoining has been used to create cylindrical molds up to 6.5 inches in diameter and 6 inches in length with a patterning rate of more than one square inch per minute. The process has been demonstrated with features between 250 nm and 5 μm in pitch (center-to-center distance) and aspect ratios (height:pitch) of up to 0.6, and the resulting molds have successfully embossed into more than 500 linear feet of film. In this proceeding, we will present the background and state of the art of this technology as well as recent efforts to control feature shape for applications like microlens arrays. We’ll also introduce new concepts, including using indentation to create seamless, cylindrical photomasks for roll-to-roll patterning of resists without the residual layer that is typically left behind by nanoimprint lithography.

Hybrid Polymers are a material class established in the industry for manufacturing of high-performance optical components, mainly patterned by (nano)imprint processes. Recently, the application range of Hybrid Polymers has been extended into bonding and passivation. In this context, patterning by classical UV-lithography has come into focus as an alternative patterning method to (nano)imprinting. By applying a two-stage curing process with a high intensity, low dose patterning step and a high dose flood exposure after development, it is possible to realize previously unattainable resolutions limits for Hybrid Polymers of 6μm L/S and aspect ratios of more than 3.

Impact of mask CD errors on microlens and pillar structures fabricated using grayscale lithography technique is studied. CD errors were evaluated from the mask SEM images using contour based metrology. Mask error enhancement factor for grayscale lithography is proposed based on mask (or design) chromium density for given 3D structure to be patterned. Impact of mean-to-target CD mask error and local CD variations on target critical parameters were studied separately. For grayscale lithography, the global mask error enhancement factor calculated to study impact of mask CD errors were found to be non linear and highly dependent on the mask (or layout) chromium density. Surface topography of given grayscale target was found to be highly dependent on the local CD variations. We also found that intentional local CD variation can be used to effectively tune certain target parameters.

Maskless grayscale lithography is a key technology to create structured surfaces in photoresist, especially for micro-optic applications. It uses spatially modulated light intensity to expose a layer of low-contrast positive resist. A digital design that contains gray values or height information, corresponding to a certain target depth in the photoresist, can conveniently be exposed with a DWL 66⁺ from Heidelberg Instruments. Processes are well known for thicknesses up to 60 μm. The possibility to fabricate taller structures, are of great interest in the micro-fabrication world. Two experimental and one commercial resists have been compared to reach and exceed the 100 μm symbolic height. After a validating experiment in a single coated layer of an experimental DNQ-based photoresist, we doubled and tripled the coating cycles at relatively low velocity and quickly obtained promising results. The triple-coated film while enabling the possibility to fabricate structures 100 μm high showed some sort of delamination in the deepest region of the layer, close to the substrate’s surface. The delamination indicates the formation of N₂ bubbles, a disadvantage of DNQ-based photoresists that release nitrogen when exposed to light. Experiments with a commercially available resist seems to show similar behavior for thicknesses above 80 μm. Recent experiments using a second experimental resist, from a different supplier, showed some promising results: structures slightly higher than 100 μm without visible defect caused by nitrogen have been fabricated. Another advantage is that overall dose required to reach this depth was significantly lower than in the previous test.

Greyscale lithography for the manufacture of complex 2.5D and freeform microstructures in photoresists receives increasing attention from industry for the fabrication of advanced micro-optical elements. The thus obtained structures serve as master or template for different methods of pattern transfer into materials for final, permanent applications, such as refractive and diffractive lenses, blazed gratings, beam-shapers etc. However, many such applications require large structure heights beyond 100 μm which was not easily accessible until now. We present a novel photoresist, mr-P 22G_XP, enabling greyscale lithography of very deep patterns. Issues limiting the pattern depth caused by the photoresist chemistry were addressed. Greyscale pattern depths of 120 μm were possible with an easily accessible set-up with this prototype, with a well-considered choice of photoresist ingredients, and lithography process adjustments focusing on laser direct writing, with the prospect of even deeper patterns up to 140–150 μm.

Since its beginning in the 90’s NanoImprint Lithography (NIL) has been continuously improved to target the different industry requirements. Using an intermediate soft stamp media was one of the main improvements and has now become a standard technology. Based on that technology, EVG introduces a full wafer imprinting solution, whereas the size of the stamp corresponds to the size of the wafer to imprint. Results obtained at CEA-Leti using this solution, with respect to uniformity, sub-50nm resolution, repeatability, and high aspect ratio patterns, are today state of the art and allow NIL to be considered as an HVM technology. Nevertheless, further development is carried out on different aspects such as overlay (OVL) which is the scope of this work.

Different contributors of OVL as translation, rotation but also distortion are dissociated and analyzed. Alignment repeatability is studied. Additionally, imprint to imprint OVL correction terms are applied. A dedicated methodology has been established and allows to obtain global OVL signature. According to the above, main process contributors are highlighted and studied in the paper to separate influence of each of them. Finally, different ways to improve overlay are discussed and some of them - which could be linked to hardware, process or both - are evaluated. Overall, the OVL status obtained and first improvements bring NIL technology closer to the alignment requirements of the industry.

Amorphous metal oxides (AMO) are a class of semiconducting materials that show promising application in optoelectronics because of their high carrier mobility and optical transparency. By alloying with other metallic species and regulating the oxygen vacancies, the carrier mobility, and the optical bandgap energy of AMOs can be modified. This customizability not only broadens the operating window of AMOs in optoelectronics but also further enables other applications, such as digital memory devices and thin-film-transistors. Typically, AMO thin films are obtained by conventional chemical or physical vapor deposition; however, these processes generally require undesirable toxic gas precursors, a vacuum environment, and a long processing time. Gallium-based liquid metals (LMs) – a class of metals that exist as liquid at or near room temperature – naturally forms an ultrathin layer of AMO (~3nm) on their surface under ambient conditions. Herein, we propose a method to harness this feature to continuously deposit gallium oxide (GaOx) and gallium indium oxide (GaInOx) traces with their host LMs at or near ambient conditions.

As the critical dimension (CD) of integrated circuits (ICs) becomes smaller and smaller, traditional optical lithography has a resolution limit due to the light diffraction effect, and surface plasmon lithography (SPL) beyond the diffraction limit developed in recent years is considered to be an alternative method to break through the diffraction limit. However, the fact that transverse magnetic (TM) waves are required to excite surface plasmon polaritons (SPP or SPPs) at the interface between a metal and a dielectric limits the application of surface plasmon lithography in imaging of the two-dimensional patterns in arbitrary shapes into photoresist. As an effective means of expanding existing lithography technology, double exposure (DE) is expected to be an effective means to solve this problem. Taking the advantage of imaging principle of DE, this paper proposes for the first time to apply DE to SPL to improve the imaging quality of SPL and theoretically analyzes the effect of DE on the improvement of SPL patterning in two dimensions. Simulation is performed in commercial software of Comsol Multiphysics 6.0. The simulation result verifies and proves that, in two-dimensional patterning, DE provides better imaging quality than single exposure.

3D photolithography has been proposed using a built-in lens mask (BILM), which can form an optical image at an arbitrary focal point without using a lens by reproducing the wavefront formed in space by the complex transmittance of a glass mask, a three-dimensional structure can be formed using the multiple focus function. In this method, the 3D structure is decomposed into multiple seed patterns, and the seed images are exposed as a batch. However, the mutual interference of diffracted light to form the seed patterns causes turbulence in the image formation state, necessitating an optimized design of the mask. In this study, we conducted basic verification experiments for 3D imaging, verified the multiple focus function, reviewed the seed design including automatic optimization of the seed placement in order to first realize 3D image formation and then complex 3D image formation and verify the possibility for typical 3-D structures.

Tilted diffraction gratings with highly refractive will be an important element for smart glass to realize a metaverse such as AR (Augmented Reality)/VR (Virtual Reality). Nanoimprinting, which can directly process a variety of materials for a variety of shapes, is well suited for mass production of tilted gratings, and many approaches have been reported. In nanoimprinting, one of the keys is to release the gradient grating shape without defects. In this report, we analyzed the strain generated during peeling release and tear release by computer simulation, and investigated a low-damage peeling method for releasing the tilted structure.

The ongoing advancement of lithographic manufacturing in micro- and nanopatterning rely on the commercial availability of innovative photoresists, polymers and photopolymers as well as complementary process chemicals: This allows to enhance current micro- and nanofabrication technologies by increasing the overall pattern complexity or general process simplicity. In this contribution, we demonstrate that material innovations have a significant part in enhancing micro- and nanofabrication by outperforming generic photoresists through cross-functionality as it is increasingly required in ever growing pattern complexity (e.g. advanced mix-and-match methods) or when additional material features are set by the final application.

Zirconium oxide (ZrO₂) is an intensively studied and used material due to its many remarkable physical and chemical properties. The high performances of ZrO₂ allows its use in many applications such as coatings against corrosion, wear and oxidation, optical applications, anti-counterfeiting, or in medical applications such as dental or prosthesis. There are many methods to synthesize ZrO₂ among which we can mention reactive sputtering, chemical vapor deposition, atomic layer deposition. These techniques are well known in thin film deposition processes. However, they do not allow to easily structure the coatings to produce complex patterns (shapes, micro-nanostructures) on variable substrates in shape and size. Another process of elaboration of ZrO₂ thin films is the sol-gel method. This technique makes possible the micro-nanostructuring of the films by optical and nanoimprint-based lithography. In this paper, the authors will describe how the ZrO₂ sol-gel can be used to obtain both complex patterns (shapes, micro-nanostructures) by optical lithography (mask lithography, colloidal lithography) and by nanoimprint lithography. The authors will also show the possibility to use this versatile sol-gel and the associated structuring methods to structure complex patterns on variable substrates in their nature and geometry, as well as the possibility of using this process in optical applications. Preliminary results will be presented through several microstructured ZrO₂ demonstrators obtained from the microstructuring process on sol-gel layers. The produced layers have been characterized by Raman spectroscopy, scanning electron microscopy, atomic force microscopy. The optical properties (transmittance, reflectance) have also been investigated and a study of the influence of a thermal treatment on the refractive index and thickness of the layer has been carried out.

In this work, Lamb Wave Resonators (LWRs) based on 2 μm thin Y-cut LiNbO3 films have been fabricated using integrated fabrication process that defines IDTs (Inter Digital Transducers) on top surface and a partial Si cavity for a sacrificial layer on the bottom surface. We discuss the etch quality and its effects on the device's performance. For the first time, we present an optimized high-quality etched MEMS (Micro-electromechanical Systems) Resonator with smooth and vertical sidewalls on this material system, reporting the maximum Q-factor of 2500 at 846 MHz frequency. We observed that the resonator system has a Q-factor of 480 over the same frequency range when the etched surface has significant roughness and non-verticality. Q values of the device are greatly diminished by the presence of surface roughness and non-verticality of the etched edges. This truly highlights how important it is to have a high-quality etch profile for a piezoelectric material system like this so that the designed resonators can perform at their best.