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Proceedings Paper

Lithography Limited Yield Analysis
Author(s): Clark Beck
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Paper Abstract

A computer program has been developed for calculating statistical layout design rules for integrated circuits. The program also calculates the sampling plan required to verify the confidence levels of alignment and circuit element dimensions at develop inspection. The inherent speed and computational accuracy of the computer offers the user a choice of confidence levels depending upon circuit configuration and critical alignments in the process. Finally, the program calculates overall circuit yields as a function of lithography limited margin violations.

Paper Details

Date Published: 23 July 1985
PDF: 6 pages
Proc. SPIE 0538, Optical Microlithography IV, (23 July 1985); doi: 10.1117/12.947759
Show Author Affiliations
Clark Beck, EFOOT (United States)

Published in SPIE Proceedings Vol. 0538:
Optical Microlithography IV
Harry L. Stover, Editor(s)

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