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Proceedings Paper

Analysis of layout-dependent context effects on timing and leakage in 28nm
Author(s): Patrick McGuinness; Puneet Sharma; Philippe Hurat
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Paper Abstract

In advanced process technologies, a layout context (that is the layout surrounding a cell) can impact the timing and leakage of a cell due to stress induced by the layout features, Well Proximity Effect (WPE), and other layout-dependent effects. The Litho Electrical Analyzer (LEA) tool from Cadence® is used to perform an analysis on 28nm standard cells in order to assess the variation in the timing and leakage characteristics due to the layout-dependent effects. During the study, the substantial leakage and timing shifts due to the layout contexts were observed. Moreover, the leakage variations were measured, and different levels of correlation of shifts across the PMOS transistors and the corresponding non-correlation between the PMOS and NMOS devices were also observed. Due to cancellation of the positive and negative variations in leakage, and because the leakage variation in Silicon is large, it is recommended to include a flat leakage margin without having added complexity to the leakage analysis flow. In addition, the timing was observed that impacts the slew and load conditions and identified conditions where shifts would be the greatest. Also, several mitigations were identified to reduce the variability of timing due to a context. This paper begins with describing the tools and methodologies used for the performance and power analysis of standard cells. It also explains the delay impact analysis, present delay simulation, Silicon-based results, and proposes guidelines to mitigate the un-modeled LDEs.

Paper Details

Date Published: 14 March 2012
PDF: 7 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270I (14 March 2012); doi: 10.1117/12.916208
Show Author Affiliations
Patrick McGuinness, Freescale Semiconductor, Inc. (United States)
Puneet Sharma, Freescale Semiconductor, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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