Share Email Print

Proceedings Paper

Automated optimized overlay sampling for high-order processing in double patterning lithography
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved algorithms for this automation; both of which are described here.

Paper Details

Date Published: 1 April 2010
PDF: 10 pages
Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76381R (1 April 2010); doi: 10.1117/12.846371
Show Author Affiliations
Chiew-seng Koay, IBM Corp. (United States)
Matthew E. Colburn, IBM Corp. (United States)
Pavel Izikson, KLA-Tencor Israel (Israel)
John C. Robinson, KLA-Tencor Corp. (United States)
Cindy Kato, KLA-Tencor Japan Ltd. (Japan)
Hiroyuki Kurita, KLA-Tencor Japan Ltd. (Japan)
Venkat Nagaswami, KLA-Tencor Corp. (United States)

Published in SPIE Proceedings Vol. 7638:
Metrology, Inspection, and Process Control for Microlithography XXIV
Christopher J. Raymond, Editor(s)

© SPIE. Terms of Use
Back to Top