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Proceedings Paper

New approach for mask-wafer measurement by design-based metrology integration system
Author(s): Tatsuya Maeda; Katsuya Hayano; Satoshi Kawashima; Hiroshi Mohri; Hideo Sakai; Hiodetoshi Sato; Ryoichi Matsuoka; Makoto Nishihara; Shigeki Sukegawa
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Paper Abstract

OPC (Optical Proximity Correction) technique is getting more complicated towards 32 nm technology node and beyond, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and their manufacturing process is complicated. In order to shorten TAT (Turn around time), mask design technique needs be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so its current performance is very close to the ideal. On the other hand, when down sizing of device feature size reaches the 32nm technology node, cases begin to be reported where the feature dimension is not matched between a mask pattern and the corresponding printed pattern. Therefore, it is indispensable to understand the pattern size correlation between a mask and the corresponding printed wafer in order to improve the processing accuracy and the quality in the situation where the device size is so small that the low k1 lithography is widely used in production. One of the approaches to improve the estimated accuracy of lithography is the use of contour data extracted from mask SEM image in addition to the application of a mask model. This paper describes a newly developed integration system that aims to solve the issues above, and its applications. This is a system that integrates mask CD-SEM (Critical Dimension-Scanning Electron Microscope) CG4500, wafer CD-SEM CG4000, OPC evaluation system DesignGauge, all manufactured by Hitachi High-Technologies. The measurement accuracy improvement was examined by executing a mask-wafer same point measurement, i.e. measurement of the corresponding points, with same measurement algorithm utilizing the new system. First, we measured mask patterns and verified the validity based on the measurement value, the image, the measurement parameter and the coordinates. Then a job file was formulated for a wafer CD-SEM using the new system so as to measure the corresponding patterns that were exposed using the mask. In addition, the average CD measurement was tried in order to improve the capability. Furthermore, in order to estimate the pattern shape with high accuracy, a contour was calculated from a mask SEM image, and the result was used with the design data in a litho simulation. This realizes a verification that includes mask fabrication error. This system is expected to be beneficial for both mask makers and device makers.

Paper Details

Date Published: 23 March 2009
PDF: 10 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72722D (23 March 2009); doi: 10.1117/12.813916
Show Author Affiliations
Tatsuya Maeda, Hitachi High-Technologies Corp. (Japan)
Katsuya Hayano, Dai Nippon Printing Co., Ltd. (Japan)
Satoshi Kawashima, Dai Nippon Printing Co., Ltd. (Japan)
Hiroshi Mohri, Dai Nippon Printing Co., Ltd. (Japan)
Hideo Sakai, Hitachi High-Technologies Corp. (Japan)
Hiodetoshi Sato, Hitachi High-Technologies Corp. (Japan)
Ryoichi Matsuoka, Hitachi High-Technologies Corp. (Japan)
Makoto Nishihara, Hitachi High-Technologies Corp. (Japan)
Shigeki Sukegawa, Hitachi High-Technologies Corp. (Japan)

Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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