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Proceedings Paper

Architectural design for a low cost FPGA-based traffic signal detection system in vehicles
Author(s): Ignacio López; Rubén Salvador; Jaime Alarcón; Félix Moreno
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Paper Abstract

In this paper we propose an architecture for an embedded traffic signal detection system. Development of Advanced Driver Assistance Systems (ADAS) is one of the major trends of research in automotion nowadays. Examples of past and ongoing projects in the field are CHAMELEON ("Pre-Crash Application all around the vehicle" IST 1999-10108), PREVENT (Preventive and Active Safety Applications, FP6-507075, and AVRT in the US (Advanced Vision-Radar Threat Detection (AVRT): A Pre-Crash Detection and Active Safety System). It can be observed a major interest in systems for real-time analysis of complex driving scenarios, evaluating risk and anticipating collisions. The system will use a low cost CCD camera on the dashboard facing the road. The images will be processed by an Altera Cyclone family FPGA. The board does median and Sobel filtering of the incoming frames at PAL rate, and analyzes them for several categories of signals. The result is conveyed to the driver. The scarce resources provided by the hardware require an architecture developed for optimal use. The system will use a combination of neural networks and an adapted blackboard architecture. Several neural networks will be used in sequence for image analysis, by reconfiguring a single, generic hardware neural network in the FPGA. This generic network is optimized for speed, in order to admit several executions within the frame rate. The sequence will follow the execution cycle of the blackboard architecture. The global, blackboard architecture being developed and the hardware architecture for the generic, reconfigurable FPGA perceptron will be explained in this paper. The project is still at an early stage. However, some hardware implementation results are already available and will be offered in the paper.

Paper Details

Date Published: 10 May 2007
PDF: 10 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900M (10 May 2007); doi: 10.1117/12.721694
Show Author Affiliations
Ignacio López, Univ. Politécnica de Madrid (Spain)
Rubén Salvador, Univ. Politécnica de Madrid (Spain)
Jaime Alarcón, Univ. Politécnica de Madrid (Spain)
Félix Moreno, Univ. Politécnica de Madrid (Spain)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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