Share Email Print
cover

Proceedings Paper

OPC to reduce variability of transistor properties
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric yield. The process variations consist of systematic components and random components. Systematic variations are caused by predictable design and process procedures, therefore systematic variations should be removed from process corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The method of calculating distorted transistor properties without slicing into individual rectangular transistors has been previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated, reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate length distribution and layout parameters, and found that parameter fitting by average and &sgr; of gate length distribution of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however, property priority required for each transistor is different. Therefore performance improvement of the whole circuit and chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.

Paper Details

Date Published: 21 March 2007
PDF: 9 pages
Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 65210J (21 March 2007); doi: 10.1117/12.711812
Show Author Affiliations
Kaoru Koike, Sony Corp. (Japan)
Kohichi Nakayama, Sony Corp. (Japan)
Kazuhisa Ogawa, Sony Corp. (Japan)
Hidetoshi Ohnuma, Sony Corp. (Japan)


Published in SPIE Proceedings Vol. 6521:
Design for Manufacturability through Design-Process Integration
Alfred K.K. Wong; Vivek K. Singh, Editor(s)

© SPIE. Terms of Use
Back to Top