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Proceedings Paper

100-nm CMOS gates patterned with 3 sigma below 10 nm
Author(s): Hua-Yu Liu; Carlos H. Diaz; Chiu Chi; R. Kavari; Peng Cheng; Min Cao; Robert E. Gleason; Brian S. Doyle; Wayne M. Greene; G. Ray
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Paper Abstract

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.

Paper Details

Date Published: 5 June 1998
PDF: 7 pages
Proc. SPIE 3331, Emerging Lithographic Technologies II, (5 June 1998); doi: 10.1117/12.309593
Show Author Affiliations
Hua-Yu Liu, Hewlett-Packard Labs. (United States)
Carlos H. Diaz, Hewlett-Packard Labs. (United States)
Chiu Chi, Hewlett-Packard Labs. (United States)
R. Kavari, Hewlett-Packard Labs. (United States)
Peng Cheng, Intel Corp. (United States)
Min Cao, Hewlett-Packard Labs. (United States)
Robert E. Gleason, Hewlett-Packard Labs. (United States)
Brian S. Doyle, Intel Corp. (United States)
Wayne M. Greene, Hewlett Packard (United States)
G. Ray, Hewlett-Packard Labs. (United States)

Published in SPIE Proceedings Vol. 3331:
Emerging Lithographic Technologies II
Yuli Vladimirsky, Editor(s)

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