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Proceedings Paper

Real-time scene generator
Author(s): Eric Lord; David J. Shand; Allan J. Cantle
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Paper Abstract

This paper describes the techniques which have been developed for an infra-red (IR) target, countermeasure and background image generation system working in real time for HWIL and Trial Proving applications. Operation is in the 3 to 5 and 8 to 14 micron bands. The system may be used to drive a scene projector (otherwise known as a thermal picture synthesizer) or for direct injection into equipment under test. The provision of realistic IR target and countermeasure trajectories and signatures, within representative backgrounds, enables the full performance envelope of a missile system to be evaluated. It also enables an operational weapon system to be proven in a trials environment without compromising safety. The most significant technique developed has been that of line by line synthesis. This minimizes the processing delays to the equivalent of 1.5 frames from input of target and sightline positions to the completion of an output image scan. Using this technique a scene generator has been produced for full closed loop HWIL performance analysis for the development of an air to air missile system. Performance of the synthesis system is as follows: 256 * 256 pixels per frame; 350 target polygons per frame; 100 Hz frame rate; and Gouraud shading, simple reflections, variable geometry targets and atmospheric scaling. A system using a similar technique has also bee used for direct insertion into the video path of a ground to air weapon system in live firing trials. This has provided realistic targets without degrading the closed loop performance. Delay of the modified video signal has been kept to less than 5 lines. The technique has been developed using a combination of 4 high speed Intel i860 RISC processors in parallel with the 4000 series XILINX field programmable gate arrays (FPGA). Start and end conditions for each line of target pixels are prepared and ordered in the I860. The merging with background pixels and output shading and scaling is then carried out in the FPGA's on a line by line basis. The whole process is carried out at 4 * 4 super-sampled rates to minimize spatial aliasing. Other techniques such as real time selective image filtering will be described and a video will be shown to demonstrate the successful application of these in HWIL and Trials proving.

Paper Details

Date Published: 24 May 1996
PDF: 12 pages
Proc. SPIE 2741, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing, (24 May 1996); doi: 10.1117/12.241097
Show Author Affiliations
Eric Lord, British Aerospace Dynamics Ltd. (United Kingdom)
David J. Shand, British Aerospace Dynamics Ltd. (United Kingdom)
Allan J. Cantle, Nallatech Ltd. (United Kingdom)

Published in SPIE Proceedings Vol. 2741:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing
Robert Lee Murrer Jr., Editor(s)

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