I am a Senior Applications Engineer at ASML Netherlands.
I got my Master degree in Material Science at the University of Milano-Bicocca in Italy Magna Cum Laude in March 2005. My final assignment was the base for a Journal Paper publication (Article DOI: 10.1021/jp045581j)
I started working in the semiconductors industry at STMicroelectronics Italy in 2005 as a technology development engineer. my main tasks were related to the optimization of exposure tools for extreme resolution patterning, scanner control, process development, OPC characterization, proximity matching, overlay optimization. I took part into the development of 90, 65, 45 and 32nm technology nodes for NOR, NAND and PCM flash memories. In addition, I worked on BCD-HVG processes. during the development of 32nm node I also contributed to a publication (doi: 10.1117/12.772795)
In 2008, I moved to the Netherlands to join ASML as an Applications Engineer. In the past 10 years at ASML I covered several roles.
I started as a customer support engineer focusing on supporting the customers on their production issues, performing analysis, propose action plans and coordinating with equipment support. Furthermore, I made sure that customer requirements are considered when developing new products.
I then focused on On-product overlay root cause analysis and optimization through advanced modeling. I developed methodologies for on product overlay analysis. During this period, I also worked on YieldStar metrology applications - micro diffraction based overlay.
During the past 4 years, aside of my technical contribution, I also led several projects spanning from on-product performance optimization at customers for the main aspects of the lithography process (Overlay, Imaging, Focus, Metrology and Automation) to new product development and introduction for control loops software and metrology.