Light Constructions - Micromechanical memory on chips allows single wafer computers
At Carnegie Mellon Univ. researchers are trying to design a micromechanical memory that will allow an entire computer system -- central processing unit, random access memory, in/out channels and hard drive -- to be implemented on a single wafer. In particular, they have concentrated on building a hard disk that is large enough to be worthwhile (initially 2 GB) and yet can still be integrated with the rest of the system. The memory works by using hundreds of micromechanical probes that each interrogate a small array of positions on a magnetic medium. Though they have yet to construct a prototype, their work represents a new approach to the next stage of computer miniaturization.
Conventional chip-based memories rely on improvements in lithography for miniaturization. Essentially, they consist of small circuits that have to be at least a few times the minimum lithographic linewidth in height and width. According to the Silicon Industry Roadmap, which forecasts the progress in computing technology, lithography will not produce 2-GB chips until 2011 at the earliest. Today's commercial process, at 180 nm, can only provide densities up to a few tens of MB per square centimeter.
However, micromechanical-probe memories -- where a small cantilever tip is used to address a point on some sensitive material -- can already reach useful densities for miniature hard disks, at least in theory. Probe tips can be used to detect individual features as small as 30 nm. If this power is used effectively, the areal density could be 1 GB per cm2 or more. The problem is how to exploit the technology in a fast, single-chip configuration.
The Carnegie Mellon team1 has come up with a scheme that, they hope, will take care of using the full area of the memory material, keep the speed high, and allow for various alignment problems. The basic idea is shown in Figure 1. An array of read/write tips is fabricated onto the top of a chip that has the rest of the computer system laid down around and underneath it. A second wafer, with its bottom surface covered by some magnetic medium, is suspended above the probes.
In order to use every bit of the memory, the probe tip must be scanned over the same area within the memory as the probe circuit takes up within its array. The CMU scheme achieves this by scanning the entire medium (the top wafer, known as a "media sled") over the bottom, using the mechanism shown in Figure 2. Moving the individual probes by this much -- 100 µm -- would not be possible, as actuation distances are typically just 10 percent of the actuator footprint. For the purpose of addressing individual bits, therefore, the probes are essentially passive. All the necessary movement is performed by the medium.
However, the probe tips are also micro-actuated in two dimensions as a means of keeping the system aligned. In particular, two distortions need to be compensated for: thermal variations in the chips and curvature of the two wafers (but particularly that carrying the medium). According to researchers, a difference of 5 deg. across an 8 X 8-mm media sled can produce an error of a few hundred nanometers, which must be removed. In one proposed design, shown in Figure 3, comb drives provide the lateral displacement in the x direction to compensate for this. In the y direction, any errors are removed through electronic signal tracking. A second actuator, this time in the z direction, compensates for curvature and mechanical instability.
Recent designs include analysis of power requirements, materials, and processes. These efforts are part of CMU's Center for Highly Integrated Information and Storage Systems, the goals of which are to develop technology for nonvolatile, rewriteable, low-cost IC-based mass storage devices, and to consider applications for the systems they enable.
L. Richard Carley, James A. Bain, Gary K. Fedder, David W. Greve, David F. Guillou, Michael S. C. Lu, Tamal Mukherjee, and Suresh Santhanam, Single-chip computers with microelectromechanical systems-based magnetic memory, Journal of Applied Physics 87 (9), pp. 6680-6685, 1 May 2000.