Nanoimprint lithography and nanodefect management for semiconductor fabrication

Nanoimprint technology combined with defect management could significantly reduce the cost of lithography for fabricating semiconductor devices.
07 April 2016
Tatsuhiko Higashiki

Many industry experts believe that continuous shrinkage of semiconductor device design rules (DRs)—the parameters for checking lithographic mask correctness—is unsustainable. Nevertheless, DR shrinkage is still increasingly required for devices that use dynamic random-access memory (DRAM), negative-and (NAND) flash, 3D memory, resistive random-access memory (ReRAM), and systems-on-chip (SOCs) (see Figure 1). Furthermore, the arrival of big data will likely cause an information explosion that will prompt an exponential increase in demand for maximum memory capacity. 3D memory has very high potential to meet targets for both capacity and cost. However, at present its processing costs still exceed those of 2D memory. Therefore, the market requires a non-volatile semiconductor memory device that has improved reliability for data retention, and which will meet the rapidly increasing demand for storage.

Figure 1. Trends in lithography and the memory market, 2013–2019 and beyond. NAND: Negative-and memory. ArF im: Argon fluoride laser immersion.

The cost of implementing pattern-shrinking technologies, such as multi-patterning and extreme UV lithography (EUVL), is expected to grow substantially through 2019. Therefore, to significantly reduce lithography investment costs, researchers have been developing nanoimprint lithography (NIL).1 One of the most significant challenges in implementing this technology is achieving nanodefect management (NDM), which includes inspection of templates, imprinted wafers, and resist material for defects, and then undertaking appropriate mitigation. Enabling these processes has required intensive collaboration between providers of templates, nanoimprint lithography equipment, resists, metrology, and inspection and cleaning equipment. In addition, computational lithography technology enables prediction and correction of specific problems with nanoimprints. Furthermore, high-precision resist pattern etching at 20nm and below is critical for NIL and EUVL, and resist defects are generated after etching. Therefore, innovation in resist materials is required for all developing lithography technologies.

We used NIL technology to improve current devices,2 and we are now verifying the technologies and the compatibility of NIL to fabrication with silicon, in preparation for the production line.3 We need to solve the unique challenges of defectivity, overlay accuracy, and productivity. Specifically, we have to understand new phenomena in lithography, such as the influence of polymer rearrangement on liquid resist nanofluid mechanisms, and the effect of nanobubbles on metal ions in the material. Polymer rearrangement occurs at the wall of a channel, and causes the boundary layer between the wall and the resist to be stagnant. It also alters the viscosity of the resist close to the wall. Figure 2 shows the overlay accuracy on the wafer edge according to the resist layer thickness, which also influences the resist viscosity. This in turn deforms the template, and the polymer rearrangement on the wafer. For overlay accuracy, we need to consider rearrangement of the polymer in the resist design. Moreover, this template innovation will lead to new NIL technology, enabling NIL to sub-20nm single patterning, which would improve template performance in terms of resolution, defectivity, critical dimension uniformity, and internal placement.

Figure 2. Edge placement overlay accuracy depends on residual layer thickness. Si: Silicon. Ai, A1, A2, A3: Resist samples.

In summary, the intensive pursuit of large-scale integration downscaling to sub-2nm precision requires both pattern shrinking and cost reduction to enable manufacturing. Nanoscaled defects and particles are increasingly the main contributors to yield losses, and the developer's greatest concern will be management of these. To address this challenge, we will in future use advanced metrology and inspection, such as electron beam (EB) inspection of wafers for multi-critical-dimension scanning electron microscopy. We will also need to adapt resists and materials, using, for example, etching resistance improvement and EB cure technology for templates. These processes will require super clean tools and clean-room environments to mitigate defects and/or particles for all unit processes.

Tatsuhiko Higashiki
Toshiba Corporation
Kawasaki, Japan

Tatsuhiko Higashiki is a senior fellow in Semiconductor & Storage Products, where he supervises advanced mask and lithography technology. His current research interests are advanced lithography and mask technologies, such as multi-patterning, extreme UV lithography, nanoimprint lithography, directed self-assembly, and nanodefect management.

1. T. Higashiki, T. Nakasugi, I. Yoneda, Nanoimprint lithography and future patterning for semiconductor devices, J. Micro/Nanolith. MEMS MOEMS 10, p. 043008, 2011.
2. T. Higashiki, Device fabrication using nanoimprint lithography and challenges for template process technologies, Proc. Bay Area Chromium Users Soc., p. 9635, 2015.
3. T. Higashiki, Device fabrication using nanoimprint lithography and challenges in nano-defect management. Presented at SPIE Advanced Lithography 2016.
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