Manipulating properties of nanowire transistors

Depositing metal nanoparticles onto nanowire channels offers cost-effective and reliable control of their electronic behavior.
11 March 2014
Ning Han and Johnny C. Ho

Silicon technology has dominated the current semiconductor industry for decades, but work to miniaturize devices is fast approaching the ultimate physical limit of sub-10nm device channel length, which results from silicon's relatively poor carrier mobility. Surpassing this limit would enable higher electronic calculation speeds and storage capacity, but the extraordinarily high cost of the required reduction in device size serves as a strong motivation for developing materials that electronically outperform silicon. III-V semiconductor nanowire materials are among the prospective candidates offering superior carrier mobility1, 2 as well as the ability to integrate successfully with current silicon technology.3, 4 However, there is currently no simple, reliable way to manipulate the electrical properties (threshold voltage, carrier concentration, and mobility) of nanowire devices. This means that there are still significant challenges to overcome to construct large-scale and complex commercial devices, such as central processing units or analog-to-digital signal converters.

Purchase SPIE Field Guide to Optical Fiber TechnologyEmploying metal electrodes with different workfunctions, Tomioka and coworkers have reported the fabrication of III-V—that is, indium gallium arsenide (InGaAs)—nanowire transistors with controllable device performance on silicon.3 However, this complicated device design and fabrication scheme suffers from substantial processing costs, which would potentially restrict practical implementation. To realize the cost-effective manipulation of electronic transport properties in nanowire devices, we have developed a ‘metal cluster decoration’ method, simply depositing various metal nanoparticles on top of the nanowire channels to manipulate the electrical properties of the device.5 More importantly, we have used this approach to construct nanowire circuits and demonstrate the versatility of the technique.

Metal cluster decoration is based on conventional Schottky-Mott theory. When they come into contact, metals with higher workfunctions than semiconductors deplete electrons from semiconductors. In contrast, metals with lower workfunctions donate electrons to semiconductors. In this way, the electron concentration can be effectively tuned by metal clusters with different workfunctions deposited on the III-V nanowire surface.

For instance, we adapt solid-source chemical vapor deposition to synthesize various III-V nanowires, contact-print the nanowires onto silicon/silicon oxide substrates, and fabricate field-effect transistors. We then deposit different types of metal clusters with controllable dimensions onto the nanowire channels by thermal evaporation. We employ indium arsenide (InAs) as representative III-V nanowires (diameter ∼30nm, workfunction ∼5.0eV) and gold (Au) metal clusters (diameter ∼5nm, workfunction ∼5.4eV) to illustrate the effectiveness of this approach: see Figure 1(a) and (b). The corresponding transfer characteristics (current-voltage or IDS-VGS curves) clearly demonstrate the positive device threshold voltage shift, transforming the device from depletion mode (i.e., threshold voltage <0V) into enhancement mode (i.e., threshold voltage >0V): see Figure 1(c). Metal clusters with different workfunctions, such as nickel, Ni (∼5.1eV), chromium, Cr (∼4.6eV), and aluminum, Al (∼4.2eV) are also deposited with the same procedures on InAs nanowire devices. All these experimentally confirm the reliable control of threshold voltage by selecting metal clusters with the appropriate workfunction: see summary in Figure 1(d).

Figure 1. Metal cluster decoration on an indium arsenide (InAs) nanowire (NW) field-effect transistor. (a) Typical scanning electron microscopy image and schematic view of a device with InAs nanowires decorated with gold (Au). (b) Transmission electron microscopy image of the InAs nanowire after the decoration. (Inset) Distribution of diameters of decorated Au clusters. (c) Current-voltage (IDS-VGS) curves of the device before and after Au cluster decoration. (d) Summary of the threshold voltage shift as a function of the workfunction difference between the metal and InAs. Al2O3: Aluminum oxide. Al: Aluminum. Cr: Chromium. Ni: Nickel. SiO2/p+Si: Highly p-doped silicon wafer with 50nm-thick silicon oxide on the surface. IDS: Source-drain current. VGS: Source-gate voltage. Vth,M-Vth: Source-gate voltage. WM, WS: Workfunction of metal and semiconductor. (Reprinted with permission.5)

Moreover, this metal cluster decoration approach can also be applicable to other III-V nanowires, such as indium phosphide (InP) and InGaAs nanowires.5 Again, all results indicate excellent threshold voltage modulation depending on the difference between workfunctions of the deposited metals and the semiconductors of the nanowires.

To further elucidate the reliable control of the threshold voltage achieved in this technique, we have also constructed functional digital nanowire circuits.5 We fabricated n-channel metal-oxide-semiconductor (NMOS) inverters that use a gold-decorated enhancement-mode InAs device driver and an original depletion mode InAs device load with gate and source/drain terminals connected as depicted in Figure 2. The transfer curve clearly shows that the input signal is inverted with a high gain (−dVOUT/dVIN) of ∼13. Notably, this inverter can also be operated efficiently with a 100Hz, 5V square waveform input, highlighting the promise of this fabrication method in future nanoelectronic design and device integration.

Figure 2. The voltage transfer characteristics (black line) and the corresponding gain (red line) of the representative n-channel metal-oxide-semiconductor (NMOS) inverter. The inset is the schematic circuit diagram of the inverter. VDD: Drain voltage. VSS: Source voltage of the inverter. (Reprinted with permission.5)

In summary, we have presented a simple and reliable approach to tailor the device operation of III-V nanowire devices via metal cluster decoration. This effectively modulates the transistor threshold voltage by controlling the difference in workfunction between metal clusters and nanowires. We are now extending this technique to other nanowire material systems as well as other device structures to realize high-performance complementary metal-oxide-semiconductor nanowire circuits.

This work was supported by the General Research Fund of the Research Grants Council of Hong Kong SAR, China (projects CityU 101210 and CityU 101111), the National Natural Science Foundation of China (grant 51202205), and the Science Technology and Innovation Committee of Shenzhen Municipality (grant JCYJ20120618140624228).

Ning Han, Johnny C. Ho
Physics and Materials Science
City University of Hong Kong
Hong Kong, China

Ning Han received his PhD in chemical engineering from the Institute of Process Engineering, Chinese Academy of Sciences. He is now a postdoctoral researcher.

Johnny C. Ho received his PhD in materials science and engineering from the University of California, Berkeley. He is now an assistant professor. His research focuses on the synthesis and heterogeneous integration of multifunctional nanostructured materials for technological applications.

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2. J. J. Hou, N. Han, F. Y. Wang, F. Xiu, S. P. Yip, A. T. Hui, T. F. Hung, J. C. Ho, Synthesis and characterizations of ternary InGaAs nanowires by a two-step growth method for high-performance electronic devices, ACS Nano 6, p. 3624-3630, 2012.
3. K. Tomioka, M. Yoshimura, T. Fukui, A III-V nanowire channel on silicon for high-performance vertical transistors, Nature 488, p. 189-193, 2012.
4. Z. Fan, J. C. Ho, T. Takahashi, R. Yerushalmi, K. Takei, Y. L. Chueh, A. Javey, Towards the development of printable nanowire electronics and sensors, Adv. Mater. 21, p. 3730-3743, 2009.
5. N. Han, F. Y. Wang, J. J. Hou, S. P. Yip, H. Lin, F. Xiu, M. Fang, Tunable electronic transport properties of metal-cluster-decorated III-V nanowire transistors, Adv. Mater. 25, p. 4445-4451, 2013.
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