Highly efficient nanofocusing for integrated on-chip nanophotonics
In the last 30 years, rapid advances in integrated circuit (IC) design have revolutionized computing, communications, and data management. In that time, digital electronic devices such as computers and mobile phones have become an indispensable part of our society. As electronic device applications continue to expand, device bandwidth must be increased. Within 10 years, interchip optical communication is expected to operate at modulation speeds of over 70 gigahertz (GHz) while consuming less than 10 femtojoules per bit.1 To meet this demand, the limits imposed by the large interconnect delays and power consumption inherent in IC technologies2, 3 must be overcome.
Photonic integrated circuits (PICs) present an alternative to ICs toward this goal.4, 5 Some PIC approaches have shown excellent improvement over conventional CMOS ICs, with approximately 20GHz of bandwidth and about 1 picojoule per bit. If fully realized, this technology could present a 10,000-fold improvement, particularly for power consumption. However, PIC performance still falls short of the bandwidth and energy efficiencies that will be required for future computing and communication technologies.6 Unfortunately, due to the limits put in place by optical diffraction, it is impractical to pursue the performance improvement of dielectric-based PIC components by producing smaller optical modal volumes.
Nanoscale plasmonic devices have recently been explored as a feasible mechanism for overcoming the diffraction limits that currently prevent the improvement of PICs.7–9 Perpendicularly confined propagating electromagnetic surface waves at the metal-dielectric interface, called surface plasmon polaritons (SPPs), can be exploited for this purpose. These SPPs enable the guiding, controlling, and confining of electromagnetic waves on the nanometer scale,7 which could lead to the efficient manipulation of light within sub-100nm spaces inside nanoplasmonic light sources and detectors. Reduced physical dimensions and subsequently smaller optical modal volumes could enable on-chip integration densities easily surpassing those of current state-of-the-art PICs, superior modulation speeds and bandwidths, and lower power consumption. Efficiently focusing and confining light in deep sub-wavelength spaces is still a major challenge, however, even for nanoplasmonic devices. This is because of the large resistive and scattering losses associated with the plasmonic light focusing and confining process: due to their nature, SPPs suffer intrinsic resistive losses, while the coupling of optical modes of different sizes/scales results in unavoidable scattering. Furthermore, physically adjusting and optimizing the structural geometries of on-chip plasmonic devices for different applications are not trivial tasks, given the fabrication challenges associated with their tiny nanoscale dimensions.
As a potential solution to these challenges, we have demonstrated the design, fabrication, and characterization of a highly efficient on-chip 3D metal–insulator–metal (MIM) nanoplasmonic photon compressor (NPC) (see Figure 1). Our device can be readily integrated with other on-chip nanophotonic components.10 Among various nanofocusing approaches, we have further developed the linearly tapered MIM concept proposed by Conway and Yablonovitch,11 and Pile and Gramotnev.12 An optimized MIM-gap plasmon waveguide with a linearly tapered tip theoretically reduces the excessive losses that occur during nanofocusing processes. Based on our simulations, the coupling loss and maximum E2 (field intensity) enhancement of the 3D NPC are predicted to be 2.5dB and 3.0×104, respectively, for a case in which light is compressed from a 200×500nm2 area into a 2×5nm2 area. We produced the 3D NPC on a chip by electron beam-induced deposition (EBID). In addition, we have demonstrated highly localized light confinement using two-photon photoluminescence (TPPL) techniques: see Figure 2(a–e). From the TPPL measurements, we experimentally estimated an intensity enhancement of 400 within a 14×80nm2 cross-sectional area and a coupling efficiency of −1.3dB (or 74% transmittance).
The tip behaves as a nanoscale optical resonance cavity due to its sub-100nm finite size—see Figure 2(f–g)—and could serve as the core of a nanophotonics device, such as a nanoscale LED or sensor. By carefully optimizing the cavity properties (such as the radiation or absorption rates), low impedances (or loss rates) can be realized that match and dramatically increase the electromagnetic energy that is coupled from the microscale body of the waveguide into the nanoscale tip, for maximum field enhancement. To accomplish this delicate tuning task, we investigated the integration of the 3D NPC structure with MIM plasmonic crystals.13, 14 These crystals possess properties similar to those of photonic crystals. Our preliminary simulation results show that this arrangement represents a simple yet highly effective engineering approach to further improve the degree of energy concentration within an extremely small volume with excellent energy coupling efficiency.
In summary, we have demonstrated a highly efficient approach to both realizing and tuning 3D on-chip nanofocusing. Using simulations, optimal tapering angles and lengths were found to minimize the intrinsic scattering and resistive absorption losses observed during nanofocusing. The optimized design was realized on a chip by employing an EBID technique. The implemented 3D NPC showed highly localized light confinement. We believe that this highly efficient 3D NPC will be useful in a variety of on-chip nanoscale photonic and plasmonic applications. We are currently designing and fabricating an on-chip nanoscale tunable optical cavity, which will allow us to adjust the amount of power that flows in and out of the cavity to optimize its properties for different applications.