A high-extinction-ratio optical polarizer based on advanced CMOS technology
The development of image sensors that incorporate metal-wire-grid polarizers is being explored with CMOS technologies. Although this approach shows promise for on-chip polarization image sensing, the sensors have yet to match the performance of those that use off-chip polarizers. This is because conventional CMOS fabrication techniques do not allow a sufficiently fine grid design. The recently developed, deep-submicron forms of CMOS-integrated circuits could potentially address this problem, since the metal wire structures made from this advanced form of technology are smaller than the wavelengths of visible light. As such, it is possible to directly integrate a nanophotonic wire structure onto a CMOS image-sensing chip for the purpose of detecting light in the visible to near-IR regions.
The production of image-sensing circuits with directly integrated imaging devices is achieved via established CMOS fabrication processes. A particular advantage of such mixed-signal circuits is that they enable real-time signal processing of polarized images: this a feature that off-chip polarizers cannot offer.1, 2 On-chip polarizers are also well suited to conducting large-scale optical measurements in parallel.
Using a 65nm CMOS process, we designed and fabricated a image sensor that contained a polarizer composed of a grid of metal wire arranged in a parallel array. The metal grid was positioned on top of the image-sensing pixel (see Figure 1).3–5 With a pixel size of 20 × 20μm2 and a photodiode area of 13:2 × 13:2μm2, the fill factor corresponded to 43.6%. Others have reported that the extinction ratio of polarizers constructed from similar metal wire grids increases with decreasing grid pitch. The extinction ratio relates the transmission of the unwanted component to the wanted component. For the metal wire layers in our 65nm CMOS image sensor, we found that the grid pitch was sufficiently small to detect the wavelengths of visible light. This occurred even though the spaces between the metal wires were filled with insulating dielectric material. We measured an extinction ratio of approximately 20dB at a wavelength of 750nm (see Figure 2). With linearly polarized illumination, we observed a striped imaged as a result of perpendicular polarization between each column, as expected (see Figure 3).
Next, we designed a dual-layer polarizer to investigate the effect of mutiple layers of metal grids on the extinction ratio of our image sensor. Others have shown that the use of multi-layered metal grids leads to improved extinction ratios,6 which is now a common strategy in CMOS technologies. Each layer in a multi-layered polarizer partially reflects incident light. As such, the transmission spectrum depends on the position of the layers, meaning that the multi-layer structure effectively works as a color filter. We found that our dual-layer polarizer achieved an extinction ratio of 19.2dB at 780nm along with a grid pitch greater than the single-layer polarizer.
We found that our dual-layer polarizer only demonstrated a high extinction ratio in the red to near-IR region. We believe this is a result of the standard CMOS fabrication process, which uses copper to construct the layers of deep-submicron-sized metal grids. Constructing the metal wire grid from aluminum layers would lift this limitation. Although the operational wavelengths of our dual-layer polarizer are limited to the near-IR region, we envisage that our device would still have useful application in cases where a wide spectrum of measurement is not required. This includes applications such as optical rotation measurements of optically active materials,7, 8 and electro-optic imaging of radio frequency/terahertz waves.9–11
In conclusion, we developed a CMOS image sensor with an on-chip, metal-wire-grid polarizer that gave an extinction ratio of ∼20 dB. By using a 65nm CMOS fabrication technology, we showed that it is possible to produce nanophotonic devices that incorporate metal wire layers of deep-submicron dimensions. In the future, we plan to develop a variety of photonic devices with nanometal structures.
This work was partly supported by the Japan Society for the Promotion of Science through a grant-in-aid for scientific research (B) 24310101 and a grant-in-aid for scientific research on innovative areas 24106729 and 24651163. This work was also supported by the Very Large Scale Integration Design and Education Center, University of Tokyo, in collaboration with Cadence Design Systems Inc.
Kiyotaka Sasagawa is an assistant professor at the Nara Institute of Science and Technology. His research interests include CMOS image sensor technologies as well as the development of imaging devices and systems for neural activities, fluorescent molecules, and electromagnetic fields.