Semiconductor research and development options for rapid commercialization

New capabilities at the College of Nanoscale Science and Engineering are aimed specifically at bridging the gap between academic research and introduction into manufacturing.
27 December 2010
Michael Liehr

Development of commercial CMOS-based technologies and derivatives is aimed at high-volume production objectives that justify the very significant development and capital expenditures required. Novel materials and device concepts developed at universities, on the other hand, typically lack access to state-of-the-art 300mm wafer-processing capabilities required for rapid insertion of such ideas into mainstream manufacturing. The College of Nanoscale Science and Engineering (CNSE) in Albany (New York) provides an environment that bridges the gap between university research opportunities and manufacturing implementation. Here we describe two new options for commercial engagement at CNSE. Over the past decade, New York State has executed a strategic investment plan to position itself as a global leader in nanotechnology commercialization.

Figure 1.Main cleanroom facility at the College of Nanoscale Science and Engineering (CNSE), featuring >50,000ft2contiguous ballroom-style cleanroom.

Currently, the main cleanroom (see Figure 1) is populated with a complete tool set capable of developing both CMOS technologies with feature sizes of 15nm and low-volume early-user hardware production at more mature technology nodes (e.g., 65nm). Our lithography tool set features production-grade equipment, including immersion single-pass (ASML 1700i), immersion double-patterning (ASML 1950i), extreme-UV (EUV), e-beam, and imprint lithography. CNSE features an ASML Alpha Demo Tool (ADT). A future expansion that will include manufacturing-grade EUV tools is under consideration. This will take the college's production-worthy lithography capability beyond the 15nm node.

While leading-edge process elements are being developed at the 22nm technology node and beyond, we are also offering customized research and development of process features and derivatives, integrated into a fully design-enabled CMOS process flow. Toward this end, CNSE is using a low-power, industry-standard bulk 65nm technology (see Table 1). This node currently attracts most commercial design attention. The technology features dual-poly gates with multiple threshold-voltage options and a thick oxide compatible with 1.8 to 3.3V circuit operation. Back-end-of-the-line metallurgy is copper based and allows use of low-permittivity materials for insulators. The technology is enhanced with radio-frequency (RF) passive elements, such as resistors, capacitors, and inductors, using existing back-end metallurgy with minimal to no added manufacturing cost.

Table 1.Bulk CMOS capability at CNSE (courtesy of IBM). LP: Low power. STI: Shallow-trench isolation. NiSi: Nickel monosilicide. OPC: Optical proximity-effect correction. PSM: Phase-shift mask. BEOL: Back-end-of-line. Cu: Copper. LM: Layers of metal.
Technology node65nm LP
Substrate450 rotated
Gate dielectricNitrided oxide
Gate electrodeDual poly (N+/P+)
Stress engineeringTensile nitride liner
Gate litho193nm OPC/PSM
BEOL metalCu (9LM)
BEOL dielectric (k)Low k (3.0)

Unique opportunities exist to develop process features that require introduction of novel materials, a typically difficult challenge in more traditional manufacturing environments. While CNSE follows industry-standard procedures for contamination control, the facility's research and development nature lends itself to explore integration of unique process elements involving materials not proven compatible with standard CMOS, such as resistive random-access memory or spin-based memory elements. For example, and part of an ongoing, more future-oriented research project, CNSE is introducing graphene into the cleanroom, which involves addressing contamination-control issues because of the nature of the catalytic-growth conditions used to grow graphene.

In 2010, the college is expanding its facilities and partners to build a packaging center on campus that will initially focus on development of 300mm wafer-scale 3D integration. This capability allows heterogeneous integration of micro-electromechanical systems (MEMS) sensors, optical components, and RF applications.

Use of 65nm bulk CMOS in this application enables prototype 3D application development on industry-standard CMOS technologies with subsequent seamless product transfer into foundry-based volume manufacturing. The program is enhanced with a multiproject-wafer approach, which allows technology access while maintaining a financially attractive infrastructure.

The 0.3NA (numerical aperture) Albany Exitech micro-exposure tool (eMET) and the 0.25NA ADT provide imaging support to joint development and research partners. The eMET is ideally suited for contrast-curve generation and was developed as a screening tool to allow resist manufacturers to do coarse screening of large quantities of samples. Today, the eMET can easily accomplish a coarse screen of five or more samples, allowing testing of the best candidates for maximum resolution on the Lawrence Berkeley National Laboratory micro-exposure tool. This system is capable of imaging in the 22nm range and below.

CSNE has developed and built a state-of-the-art outgassing test stand. With this equipment, resists and materials are qualified before use on the EUV exposure systems.1,2 Once the best candidates in terms of resolution, linewidth roughness (LWR), and photospeed have been identified, the materials are typically tested on the full-field ADT. CNSE and SEMATECH staff handle all imaging and wafer processing and may also analyze and provide the data to facility users. A typical user will receive outgassing results, contrast-curve information, process-window data, ultimate resolution, critical-dimension uniformity, and LWR.

So far this year, more than 2000 wafers have been exposed on the eMET tool. The eMET is delivering 90% availability (24 hours, 7 days a week). This performance has allowed characterization of hundreds of resist and underlayer samples. The eMET can now image 24nm routinely and shows modulation at 22nm (see Figure 2). Future planned upgrades will drive resolution to sub-20nm levels.

Figure 2.Exitech micro-exposure-tool (eMET) imaging at 24nm with modulation at 22nm. UL: Underlayer. STM: Scanning-tunneling microscope. Si: Silicon. BF: Best focus. W: Wafer. PAB, PEB: Post-apply, post-exposure bake (in °C). Dev: Developer. MF26A: Type of developer. Exp: Exposure. E-MET: Exitech micro-exposure tool. NA: Numerical aperture. QUAD: Quadrupole. HMDS: Hexamethyldisilazane. σ, σ00, σout: Degree of partial coherence (angle of illumination), on-axis (coherent) illumination, outermost illumination of the four quadrupoles.

The author acknowledges the consortia and funding partners that have contributed to the development of the technology described in this paper, including the Department of Defense, the National and Air Force Research Laboratories, SEMATECH, IBM, ASML, GlobalFoundries, Tokyo Electron Limited, Applied Materials, the New York State Energy Research and Development Authority, the New York State Foundation for Science, Technology, and Innovation (NYSTAR), and the State University of New York Research Foundation. The author also acknowledges contributions of CNSE staff and faculty to this paper.

Michael Liehr
College of Nanoscale Science and Engineering
Albany, NY

Michael Liehr is associate vice-president. He was an IBM Distinguished Engineer responsible for strategic production and a member of the IBM Academy of Technology, holds a PhD in physics, and is Project Management Institute certified.

1. G. Denbeaux, Extreme ultraviolet resist outgassing and its effect on nearby optics, Proc. SPIE 6921, pp. 69211G, 2008. doi:10.1117/12.772670
2. G. Denbeaux, Quantitative measurement of EUV resist outgassing, Proc. SPIE 6533, pp. 653318, 2007. doi:10.1117/12.737192