The road to extreme-ultraviolet lithography

Extreme ultraviolet lithography promises to be the key enabler for patterning semiconductor devices of the future, but a number of challenges remain.
16 March 2007
Bruno La Fontaine

Optical lithography will reach its resolution limit for semiconductor processing at the generation where half of the pitch between lines is about 40nm. This expectation assumes a single exposure per level, using a water-based immersion system with an optical numerical aperture (NA) of 1.35. Various double-exposure and double-patterning techniques are being developed to extend this resolution limit. However, this approach to extending optical lithography is perceived to have significant disadvantages in throughput and pattern layout flexibility. Other challenges for hyper-NA lithography and double-patterning approaches include the control of focus and overlay.

Extreme ultraviolet lithography (EUVL), with a much shorter wavelength of 13.5nm, can provide imaging with a higher contrast and larger depth of focus than even hyper-NA argon fluoride (ArF) lithography with a 193nm wavelength. The higher imaging contrast achievable with EUVL is illustrated by the simulated aerial images shown in Figure 1. The Rayleigh depth of focus of 32nm 1:1 lines is significantly larger for EUVL than for ArF immersion lithography, by a factor of about 4.

Figure 1. Simulated best-focus images of 32nm half-pitch features show the improvement going from optical—panel (a): λ = 193nm (argon fluoride immersion), NA = 1.55, k1 = 0.256, extreme dipole illumination, high-n fluid and polarized light—to extreme ultraviolet (EUV) illumination—panel (b): λ = 13.4nm, NA = 0.25, k1 = 0.6, conventional (s=0.5), with flare.

The primary challenge for EUVL is not imaging, but developing the supporting infrastructure. This requires that development fabs use this technology through a sufficient number of learning cycles before it is introduced into manufacturing. Special attention will need to be paid to EUV masks, resists, and sources.

EUV masks

The masks for EUVL are very different from those used for optical lithography. EUV masks are reflective, and are illuminated at oblique angles of incidence. This leads to shadowing effects that vary across the field and with the type of features to be printed. Mask corrections such as biasing will be required to compensate for these effects. Advanced Micro Devices (AMD) has been investigating different EUV mask architectures that might minimize the shadowing effects, reduce the need for mask corrections, and improve the achievable process latitude. Improved masks include those patterned by etching the multilayer reflector and those with thin absorber stacks.1

More recently, AMD has developed effective EUV phase-shift mask prototypes, as illustrated in Figure 2. Such masks are useful for monitoring scanner parameters such as aberrations and focus uniformity. They could also be used as resolution enhancement techniques to extend EUVL beyond the 32nm half-pitch node.2

Figure 2. EUV phase-shift masks can be made by controlled etching of a multilayer stack, as shown schematically in (a). Such a mask was used on the 0.3NA micro-exposure tool at the Lawrence Berkeley National Laboratory to print 35nm lines and spaces, as shown in (b).

In addition, since EUV light is strongly absorbed by practically all materials, it is not believed possible to use pellicles to protect EUV masks. Therefore, it is essential that masks be free of defects and remain clean throughout their lifetime. The Sematech laboratories in Albany have made great progress in producing mask blanks with a very low number of defects. Assuming continued progress, this effort is expected to generate defect-free masks with a high yield by the time they are needed for the 32nm half-pitch node.3,4 However, devices and protocols for handling masks and keeping them clean will also be required. In particular, we will need to pay special attention to controlling contaminants that could lead to loss of reflectivity.

EUV resists

EUV imaging can undoubtedly produce aerial images with exceedingly small dimensions. Effectively recording these images in resist materials is more difficult. Competing mechanisms make optimization of resolution, sensitivity, and line-edge roughness (LER) extremely complex. For instance, improving sensitivity can lead to loss of resolution. This is particularly true for chemically amplified resists, which are thermally activated. The larger the heat required for processing the resist, the further optically generated acid can diffuse during the deprotection process, leading to degradation of the image in the resist and loss of resolution.

LER is another important parameter that is related to the dose used to expose the resist. As this dose decreases, the uncertainty in the number of photons incident at the edge of a feature increases, according to Poisson statistics. This is a very important consideration for scaling this technology beyond 32nm half-pitch.

For chemically amplified resists, shot-noise effects will manifest themselves on a characteristic length defined by the diffusion of the acids in the resist. Any process occurring on a finer scale inside the resist film will get blurred by the diffusion-deprotection process. The scaling of shot-noise effects can be estimated by requiring that the diffusion length remain smaller than about a quarter of the pitch to be resolved.

As AMD has extensively demonstrated,5 LER depends on the gradient of the resist latent image, which is influenced by two main factors: the aerial image log slope and the diffusion-deprotection blur. When all these effects are considered, a simple relationship between the achievable LER and the corresponding dose to clear can be expressed as: Assuming a requirement of LER = 1.6nm (3s), comparable to the ITRS target for the 32nm node, the resist sensitivity should be larger than about 20mJ/cm2. This estimate is consistent with data we have collected using the micro-exposure tool (MET) at the Lawrence Berkeley National Laboratory, using a large sample of EUV resists with different sensitivity values.6

EUV sources

The implication of this dose/LER relationship on the power requirement for EUV sources is significant. If the LER levels truly need to be kept below 1.6nm (3s), the power required for manufacturing at the 32nm half-pitch node will be larger than the current targets indicate.7 In addition, as the technology progresses to the 22nm half-pitch node and beyond, the power must continue to increase to avoid the shot-noise limit for LER. This will undoubtedly require innovative EUV source solutions.


The very large nonrecurring engineering costs associated with the development of EUVL are possibly the single most important challenge facing this technology. AMD has been, and remains, one of the leaders in the development of EUVL. Since 1996, we have been engaged in several consortia and joint development activities, such as the EUV-LLC, Sematech, SRC, the NSF Engineering Research Center for EUV Science and Technology, and the INVENT Program in Albany, NY. Over the next few years, it will be essential not only to continue but to expand such programs to make this technology successful.

Given the tremendous progress made to date and assuming continued support from industry, all these engineering and financial challenges should be addressed within a few years.

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