The European project PLATON blends plasmonics with silicon nanophotonics to provide the first proof of low-energy and Tb/s-scale plasmonic switching.
PLATON envisions the deployment of Tb/s “Router-on-Chip” platforms for data center (DC) and high-performance computing (HPC) systems to exploit the best of all chip-scale technology worlds: plasmonics for low-energy switching, silicon nanophotonics for low-loss optical motherboard, and electronics for intelligent decision-making.
PLATON’s ‘Router-on-Chip’ deployment can lead to energy consumption as low as 0.1 mW/Gb/s/hop, reducing power needs by more than 50 times compared to current DC and HPC routing machines.
PLATON addresses power and size bottlenecks
Power consumption and size appear as the main set of barriers in next-generation DC and HPC environments. The limited capacity and physical quantity of electrically wired interconnects contrasts with the increased clock speeds and wiring densities inside machines, forming the main source of the bottleneck in information exchange across all hierarchical communication levels: rack-to-rack, backplane, chip-to-chip, and even on-chip.
At the same time, parallelization in processing brings completely new requirements with respect to the traffic amounts that need to be exchanged within DCs and HPCs, essentially transforming computing into a shrinked-networking environment.
As the system’s overall power consumption has to remain below the 20MW benchmark1, the upper bound for the per-bit consumed energy in end-to-end data transmission across the system cannot exceed 50mW/Gb/s. Taking into account that these systems will incorporate hundreds of thousands of nodes, each packet will pass through 30 hops on average before reaching its final destination2.
These numbers necessitate a 1.67mW/Gb/s hop-power efficiency, well below the respective metrics of today’s state-of-the-art datacom switching technologies3.
With electrical wiring the main source of the problem, the solution extends along a clearly shaped roadmap to finally bring optics “into the box” and replace electrical with optical interconnect technologies4.
The mainstream photonic route with high integration and low-cost perspectives relies currently on the silicon-on-insulator nanophotonics platform. The growing maturity of this platform is soon expected to release Tb/s-scale data transmission and switching capabilities in datacom and computercom units, ensuring low latency, low power consumption, and chip-scale integration credentials5.
At the same time, the emerging discipline of plasmonics holds great promise for additional reductions in circuit size and increases in energy efficiency. Exploiting the propagation of electromagnetic waves known as surface plasmon polaritons (SPPs) along a metal-dielectric interface, plasmonics allow for deployment of optical structures with sub-wavelength dimensions, thereby breaking the size barriers of traditional diffraction-limited optics6.
Plasmonics also enable seamless interfacing of optical beams with electronic control signals through the underlying metallic film, providing a natural energy-efficient platform for merging broadband optical links with intelligent electronic processing.
PLATON7aims at combining the benefits of silicon photonics and plasmonics towards realizing a 4x4 “Router-on-Chip” platform with Tbps-scale data capacity and ultra-low energy requirements for use in DC and HPC communication systems.
PLATON, funded by the 7th Framework Programme for Research (FP7), has been the first research project attempting to elevate plasmonics from component-demonstration level into practical system-level applications through their interconnection with silicon photonics.
PLATON expects to provide the first ‘tangible’ experimental proof of plasmonics’ low energy data-transfer and switching potential.
The 4x4 “Router-on-Chip” envisioned in PLATON is shown in Fig. 1 and incorporates a Si motherboard hosting all various optical and electrical circuitry. The heart of this router chip is a 4x4 switching matrix employing 2x2 thermo-optic plasmonic switches that rely on the dielectric-loaded surface plasmon polariton (DLSPP) waveguide platform.
Fig. 1: Layout of the 4x4 Tb/s scale router composed of silicon, plasmonic, and electronic components placed on an SOI motherboard
This novel silicon-plasmonic ‘Router-on-Chip’ architecture intends to combine the low optical loss of the Si-waveguide motherboard for its passive interconnection parts, the high-energy efficiency of plasmonics in the router’s active parts, and the intelligence provided by electronics for its decision-making mechanisms.
The project has still one year to go but has already reached a number of technology firsts, turning the promise of plasmonics into real system-level application benefits.
PLATON’s first milestones
Two key advances of the project are:
• Wavelength division multiplexing- (WDM) enabled transmission of 480Gb/s (12x40Gb/s) aggregate traffic through a 60µm-long DLSPP straight waveguide heterointegrated with Si-photonic waveguides
• The first demonstration of low-power active on/off plasmonic switching, exploiting the thermo-optic effect in a hybrid silicon-plasmonic asymmetric Mach-Zehnder interferometer (A-MZI)
The high-throughput WDM-supportive capabilities of the DLSPP waveguide platform comprise the first milestone towards their use in true interconnect applications with high-capacity data-transport requirements. We have verified the potential of DLSPP waveguides to sustain signal integrity and successfully transmit up to 480 Gb/s total WDM traffic (12 channels x 40Gb/s) through a 60-µm-long Poly-Methyl-Methacrylate (PMMA)-loaded plasmonic waveguide integrated on a SOI rib waveguide platform, depicted in Fig. 2a8.
In- and out-coupling of optical fiber allowing for the 480Gb/s WDM data-signal insertion was ensured through SOI-based transverse-magnetic (TM) grating couplers placed at both input and output chip ports (Fig. 2b). The WDM signal was formed by multiplexing 12 channels spaced by 200GHz within the 1542-1560nm spectral window, each one modulated by 40 Gb/s nonreturn-to-zero (NRZ) data signal.
Performance of the 480 Gb/s WDM data transmission over the DLSPPW was evaluated via bit-error rate (BER) measurements and the respective BER curves for all 12 channels are illustrated in Fig. 2c. Error-free operation was obtained for six out of the 12 channels (1-5 and 12) with small power-penalty values ranging between 0.2 and 1 dB at 10–9 error rate, while channels 6-11 exhibited an error floor at 10–7.
The BER performance and the eye diagrams of the best- (ch#1) and worst-performing (ch. #8) channels are depicted in Figs. 2d and 2e, respectively.
In principle, error-free performance with uniform power penalty distribution among all channels should be expected by using a 12-channel spectrum that resides completely within the wavelength-independent spectral region of the TM-grating couplers.
Fig. 2: (a) Microscope image of the hybrid Siplasmonic waveguide; (b) layout of the Si-DLSPP waveguide with the input/ output TM grating couplers; (c) BER measurements for all 12 channels; (d) BER of best-performing channel, #1; (e) BER of worst-performing channel, #8
Disruptive technology and real data switching
Switching with real data in an active plasmonic device was demonstrated for the first time using a thermo-optic A-MZI-based hybrid silicon-plasmonic switch. Here silicon waveguides are used for the passive in- and out-coupling stages of the interferometric layout and DLSPP waveguides serve as the active, electrically controlled A-MZI sections.
The A-MZI comprised two PMMA-loaded SPP waveguides, each only 90µm long, following the plasmonic waveguide geometry also employed in the WDM experiment. The plasmonic waveguide in the lower A-MZI arm was modified in order to induce a default asymmetry of a close to ∏/2 differential phase shift between the two A-MZI optical paths, providing natural MZI biasing at the quadrature point.
A schematic layout of the hybrid A-MZI is illustrated in Fig. 3a. Switching operation was obtained upon applying electrical current to one of the two A-MZI plasmonic branches, enforcing a temperature change in the plasmonic sections and consequently a phase shift due to the thermo-optic effect9.
The Si couplers placed at the A-MZI input/output stages had a coupling ratio of 95:5 due to an unfortunate design error, restricting the device operation from high quality 2x2 switching, which should be, in principle, expected in the case of perfect 3dB couplers.
The performance of the switch in a realistic data-switching scenario has been tested with 10Gb/s NRZ optical input signals and 15µs electrical control pulses at 20KHz repetition rate for controlling device operation, with respective results shown in Fig. 3.
Figures 3b and 3c depict the on/off rise and fall times of the switched waveform that were measured to be 2.8µs and 4.6µs, respectively.
Figure 3d presents a snapshot of the signal’s trace exiting the CROSS port compared to the applied control pulses (red dashed line), while Fig. 3e shows the corresponding trace for the BAR port. The eye diagrams of the CROSS and BAR output signals are shown in Figs. 3f and 3g, respectively, illustrating an extinction ratio of 6dB for the CROSS port and 1dB for the BAR port.
Symmetric values of ER for BAR and CROSS ports could be obtained with perfect 3dB instead of the 95:5 Si couplers.
The electrical current flowing through the DLSPP waveguide required for this switching operation was 30mA, corresponding to a total power consumption of only 10.8mW. This implies a switching power of 1.08mW/Gb/s, which can be dramatically reduced when exploiting the inherent broadband characteristics of the MZI layout for high-aggregate rate WDM signal switching.
Fig. 3: (a) Layout of the thermo-optic A-MZI switch; (b-c) rise and fall times; (d) 10Gb/s data trace at the CROSS port; (e) 10Gb/s data trace at the BAR port; (f) 10Gb/s eye diagram at the CROSS port; (g) 10Gb/s eye diagram at the BAR port
Prototype is next PLATON goal
An additional factor of switching-energy reduction can be gained through the replacement of the PMMA loading with another polymer material of higher thermo-optic coefficient, an approach already identified and tackled within PLATON. The UV-curable cycloaliphatic acrylate polymer, having a three times higher Thermo-Optic Coefficient (TOC) than PMMA, has been already successfully applied as the polymer loading in DLSPP switching structures10.
Though not yet optimized for low-energy switching operation, this route is expected to decrease the required energy levels by a factor of three while sustaining high-performance switching.
All this effort indicates that PLATON has already set the cornerstones for turning plasmonics into practical elements for interconnect and datacom applications, raising significant hope for the realization of a 4x4 PLATON ‘Router-on-Chip’ prototype with 1Tbp/s capacity that will consume lower than 0.011mW/Gb/s/hop for switching.
We are currently working on demonstrating WDM data switching of reduced energy consumption in the new class of plasmonic switches that use a higher TOC polymer loading, with the next goal being the integration of the complete silicon-plasmonic ‘Router-on-Chip’ prototype.
More about PLATON at SPIE Photonics Europe 2012
At least three papers about the technologies involved with the PLATON project are scheduled to be delivered at SPIE Photonics Europe in Brussels in April.
• Paper 8424-6, 16 April, “Dielectric loaded surface plasmon waveguides for datacom applications”
• Paper 8431-15, 17 April, “Design, fabrication, and characterisation of fully etched TM grating coupler for photonic integrated system-in-package”
• Paper 8424-48, 19 April, “Hybrid silicon-plasmonics: efficient waveguide interfacing for low-loss integrated switching components”
Read more about PLATON and other European research projects in this issue of SPIE Professional:
N. Pleros is with the Department of Informatics, Aristotle University of Thessaloniki, Greece, and the Informatics and Telematics Institute.
• K. Vyrsokinos is with the Informatics and Telematics Institute, Center for Research and Technology Hellas, Thessaloniki, Greece.
• D. Apostolopoulos is with the National Technical University of Athens, School of Electrical Engineering and Computer Engineering, Athens.
• A. Dereux is with the Institut Carnot de Bourgogne, University of Burgundy, France.
• S. Bozhevolnyi is with the Faculty of Engineering/Institute of Sensors, Signals and Electrotechnics at University of Southern Denmark.
• M. Waldow and T. Wahlbrink are with AMO Gesellschaft für Angewandte Mikro- und Optoelektronik GmbH, Germany.
• T. Tekin is with the Fraunhofer IZM in Berlin.
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