SPIE Fellow Anthony Yen of Taiwan Semiconductor Manufacturing Co. (TSMC) is hoping to convince attendees at SPIE Advanced Lithography 2016 that EUV lithography is on the threshold of becoming a mainstream patterning technology for sub-10nm chips.
Yen, a former symposium chair and the director of TSMC’s Nanopatterning Technology Infrastructure Division, is one of three veterans from the semiconductor lithography community scheduled for plenary talks 22 February in San Jose, CA (USA).
Yen will present recent progress on the performance of EUV exposure tools, technology infrastructure, and patterning capability and explain why it has taken 30 years for EUV lithography to mature.
Another former chair of SPIE Advanced Lithography, SPIE Fellow Harry J. Levinson of GLOBALFOUNDRIES (USA), will review the evolution of lithographic technologies in his plenary talk, covering everything from the earliest simulation software to EUV.
Richard A. Gottscho, executive vice president of global products at Lam Research (USA), will discuss how to minimize process-induced variability in multiple patterning during his plenary talk.
The 41st annual SPIE event on semiconductor lithography, 21-25 February, will offer about 500 presentations in seven conferences; two poster sessions; 15 courses; a two-day exhibition, and an all-symposium welcome reception Monday night.
The seven conferences are:
- EUV Lithography
- Alternative Lithographic Technologies
- Metrology, Inspection, and Process Control for Microlithography
- Advances in Patterning Materials and Processes
- Optical Microlithography
- Design-Process-Technology Co-optimization for Manufacturability
- Advanced Etch Technology for Nanopatterning
SPIE Fellow Mircea V. Dusa of ASML US is symposium chair. SPIE Fellow Bruce Smith, director of microsystems engineering at Rochester Institute of Technology (USA), is cochair.
Special events include a 30th anniversary celebration for the Metrology, Inspection, and Process Control Conference with a “Wheel of Fortune” game; awarding of the 2016 SPIE Frits Zernike Award for Microlithography; and a panel discussion on fundamental technology challenges in metrology, lithography, and design as critical dimensions for integrated circuits shrink to near-atomic scales.