Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

Pieter Wöltgens; Alberto Colina; David Rio; Maxence Delorme; Tatiana Kovalevich; Arame Thiam; Frieda van Roey; Odysseas Zografos

doi:10.1117/12.2614260

26 May 2022 Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid

Pieter Wöltgens, Alberto Colina, David Rio, Maxence Delorme, Tatiana Kovalevich, Arame Thiam, Frieda van Roey, Odysseas Zografos

Author Affiliations +

Proceedings Volume 12051, Optical and EUV Nanolithography XXXV; 120510I (2022) https://doi.org/10.1117/12.2614260
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

In order to improve logic via printing we propose staggered vias to effectively regularize randomly placed vias in a typical logic design. We accomplish this (i) by forcing via placement on a staggered sub-grid of the standard manhattan grid and (ii) by placing smaller fixed-size via Sub-Resolution Assist Features (SRAFs) on all remaining empty positions of the staggered grid. We devised a methodology to create such staggered via placement in a standard Place&Route (PNR) design flow and evaluated the concept on a 64-bit (64b) ARM core implementation through a PowerPerformance-Area (PPA) analysis. From a PNR run-time perspective and PPA analysis this looked a very viable implementation with little to no disadvantages compared to standard via placement. Finally, to experimentally test and compare staggered vias and against standard manhattan vias, we designed a via mask with both staggered and standard manhattan vias patterns and exposed them on an 0.33NA NXE3400 EUV lithography system. Analysis of experimental results on a 38nm via pitch show 40% smaller best-focus shift across the slit, and 20% smaller via-via CD variation for staggered vias compared to Manhattan vias with regular SMO.

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Pieter Wöltgens, Alberto Colina, David Rio, Maxence Delorme, Tatiana Kovalevich, Arame Thiam, Frieda van Roey, and Odysseas Zografos "Logic via printability enhancement using restricted via placement and exhaustive SRAF placement on a staggered grid", Proc. SPIE 12051, Optical and EUV Nanolithography XXXV, 120510I (26 May 2022); https://doi.org/10.1117/12.2614260

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KEYWORDS

SRAF

Logic

Semiconducting wafers

Lithography

Critical dimension metrology

Optical proximity correction

Photomasks

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