Automated identification of repeated chip layout patterns

Resolution Enhancement Techniques (RETs) such as OPC and ILT are indispensable for achieving lithographic printability of almost all modern chip products. RETs are immensely computing-intensive, often necessitating thousands to millions of CPU hours for a single diffusion/poly/metal/contact layer. A significant portion of this computational load stems from redundant computations on recurring layout patterns, which can account for 20%-80% of all layout polygons of a chip design. Efforts to mitigate this computing burden entail the identification and avoidance of redundant computations on repeated layout patterns. However, existing techniques have been notably scarce and are usually very restrictive in their usage. We developed an adaptive geometric clustering-based approach, called CARPI, to automatically identify repeated chip layout patterns that facilitate the improvement of RET computing efficiency. Experimental results on industrial designs show that our approach can identify all repeated layout patterns and our clustering technique significantly outperforms alternative methods.