Recently, soft bioelectronics has attracted significant attention because of its potential applications in biointegrated healthcare devices and minimally invasive surgical tools. Mechanical mismatch between conventional electronic/optoelectronic devices and soft human tissues/organs, however, causes many challenges in materials and device designs of bio-integrated devices. Intrinsically soft hybrid materials comprising twodimensional nanomaterials are utilized to solve these issues. In this paper, we describe soft bioelectronic devices based on graphene synthesized by a chemical vapor deposition process. These devices have unique advantages over rigid electronics, particularly in biomedical applications. The functionalized graphene is hybridized with other nanomaterials and fabricated into high-performance sensors and actuators toward wearable and minimally invasive healthcare devices. Integrated bioelectronic systems constructed using these devices solve pending issues in clinical medicine while providing new opportunities in personalized healthcare.

Device fabrication based on top-down approach will reach its limit due to difficulties in patterning and processes below 10 nm node. The bottom-up approach using self-assembled materials and processes can be a viable candidate for further device scaling, but the fabrication processes are mostly not compatible with current device fabrication. In this presentation, device fabrication strategy for next-generation data-storage devices will be discussed in detail based on self-assembled materials and processes. The emphasis is placed on compatibility with current device fabrication strategies. Ordered array of various materials and systems based on bottom-up nanotechnology can be utilized as the charge storage layer for memory devices and the templates for nanoscale device fabrication. Novel device applications, for example, printed/flexible/transparent electronic devices, will be explored based on the self-assembly processes.

High Performance organic field-effect transistor (OFET) memory devices were successfully prepared using new dielectric materials, poly(N-(hydroxymethyl)acrylamide-co-5 -(9-(5-(diethylamino)pentyl)-2-(4-vinylphenyl)-9H-fluorene (P(NMA-co-F6NSt)), which contained chemical cross-linkable segment (NMA) and hole trapping building block (F6NSt). The high k characteristics of P(NMA-co-F6NSt)) led to a low voltage operation, a small power consumption, and a good digital information storage capacity. Such P(NMA-co-F6NSt) dielectrics in OFET memories with variant NMA/F6NSt molar ratios (100/0 (P1), 95/5 (P2), 80/20 (P3), and 67/33 (P4)) showed excellent insulating properties and good charge storage performance under a low operating voltage below ±5V, due to the tightly network structures after crosslinking and well-dispersed trapping cites (i.e. fluorene moieties). P3-based memory device, in particular, exhibited largest memory window of 4.13 V among the studied polymers, and possessed stable data retention stability over 104 s with a high on/off current ratio (i.e. 104) and good endurance characteristics of more than 200 write-read-write-erase (WRER) cycles. The above results suggested that a high-performance OFET memory device could be facilely achieved using the novel synthesized high-k copolymers.

Resistive random-access memory (RRAM) is a candidate next generation nonvolatile memory due to its high access speed, high density and ease of fabrication. Especially, cross-point-access allows cross-bar arrays that lead to high-density cells in a two-dimensional planar structure. Use of such designs could be compatible with the aggressive scaling down of memory devices, but existing methods such as optical or e-beam lithographic approaches are too complicated. One-dimensional inorganic nanowires (i-NWs) are regarded as ideal components of nanoelectronics to circumvent the limitations of conventional lithographic approaches. However, post-growth alignment of these i-NWs precisely on a large area with individual control is still a difficult challenge. Here, we report a simple, inexpensive, and rapid method to fabricate two-dimensional arrays of perpendicularly-aligned, individually-conductive Cu-NWs with a nanometer-scale CuxO layer sandwiched at each cross point, by using an inorganic-nanowire-digital-alignment technique (INDAT) and a one-step reduction process. In this approach, the oxide layer is self-formed and patterned, so conventional deposition and lithography are not necessary. INDAT eliminates the difficulties of alignment and scalable fabrication that are encountered when using currently-available techniques that use inorganic nanowires. This simple process facilitates fabrication of cross-point nonvolatile memristor arrays. Fabricated arrays had reproducible resistive switching behavior, high on/off current ratio (Ion/Ioff) ~10 6 and extensive cycling endurance. This is the first report of memristors with the resistive switching oxide layer self-formed, self-patterned and self-positioned; we envision that the new features of the technique will provide great opportunities for future nano-electronic circuits.

The commercial interest in Radio Frequency Identification (RFID) tags keeps growing, as new application sectors, spanning from healthcare to electronic article surveillance (EAS) and personal identification, are constantly emerging for these types of electronic devices. The increasing demand for the so-called “smart labels” necessitates their high throughput manufacturing, and indeed on thin flexible substrates, that will reduce the cost and render them competitive to the currently widely employed barcodes. Adhesion Lithography (a-Lith) is a novel patterning technique that allows the facile high yield fabrication of co-planar large aspect ratio (<100,000) metal electrodes separated by a sub-20 nm gap on large area substrates of any type. Deposition of high mobility semiconductors from their solution at low, compatible with plastic substrates, temperatures and application of specific processing protocols can dramatically improve the performance of the fabricated Schottky diodes. It will be shown that in this manner both organic and inorganic high speed diodes and rectifiers can be obtained, operating at frequencies much higher than the 13.56 MHz benchmark, currently employed in passive RFID tags and near filed communications (NFC). This showcases the universality of this method towards fabricating high speed p- and n-type diodes, irrespective of the substrate, simply based on the extreme downscaling of key device dimensions obtained in these nanoscale structures. The potential for scaling up this technique at low cost, combined with the significant performance optimisation and improved functionality that can be attained through intelligent material selection, render a-Lith unique within the field of plastic electronics.

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A “plastic wafer” is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

Wireless sensing has broad applications in a wide variety of fields such as infrastructure monitoring, chemistry, environmental engineering and cold supply chain management. Further development of sensing systems will focus on achieving light weight, flexibility, low power consumption and low cost. Fully printed electronics provide excellent flexibility and customizability, as well as the potential for low cost and large area applications, but lack solutions for high-density, high-performance circuitry. Conventional electronics mounted on flexible printed circuit boards provide high performance but are not digitally fabricated or readily customizable. Incorporation of small silicon dies or packaged chips into a printed platform enables high performance without compromising flexibility or cost. At PARC, we combine high functionality c-Si CMOS and digitally printed components and interconnects to create an integrated platform that can read and process multiple discrete sensors. Our approach facilitates customization to a wide variety of sensors and user interfaces suitable for a broad range of applications including remote monitoring of health, structures and environment. This talk will describe several examples of printed wireless sensing systems. The technologies required for these sensor systems are a mix of novel sensors, printing processes, conventional microchips, flexible substrates and energy harvesting power solutions.

The optical data transfer is considered as the future of signal transfer due to its various advantages compared to conventional copper-based technologies. The Aerosol Jet Printing (AJP) technology offers the opportunity to print materials with high viscosities, such as liquid transparent polymer adhesives (epoxy resins), on almost any possible substrate material and even in third dimension. This paper introduces a new flexible and comparatively cost-effective way of generating polymer optical waveguides through AJP. Furthermore, the conditioning of the substrate material and the printing process of planar waveguides are presented. In the first step, two lines with hydrophobic behavior are applied on foil material (PMMA, PVC, PI) by using a flexographic printing machine. These silicone based patterns containing functional polymer form barriers for the core material due to their low surface energy after curing. In the second step, the core material (liquid polymer, varnish) is printed between the barrier lines. Because of the hydrophobic behavior of the lines, the contact angle between the substrate surface and the liquid core material is increased which yields to higher aspect ratio. The distance between the barrier lines is at least 100 μm, which defines the width of the waveguide. The minimum height of the core shall be 50 μm. After UV-curing of the core polymer, the cladding material is printed on the top. This is also applied by using the AJP technology. Various tests were performed to achieve the optimal surface properties for adequate adhesion and machine process parameters.

Printed electronics has a number of significant challenges, including spatial resolution, pattern registration, and printed circuit performance. In this talk, I will describe a multi-pronged approach to address these challenges that may bring roll-to-roll printed electronics closer to reality. To begin, I will show that innovations in materials allow the fabrication of printable, low voltage thin film transistors (TFTs), the key building blocks of flexible circuits, and that these can be incorporated into simple printed circuit demonstrations involving two dozen TFTs and an equivalent number of printed resistors and capacitors. The second half of the talk will describe a novel liquid-based fabrication approach that we term SCALE, or Self-Aligned Capillarity-Assisted Lithography for Electronics. The SCALE process employs a combination of digital printing and in-substrate capillary flow to produce self-aligned devices with feature sizes that are currently as small as 1 micron. The talk will finish with a discussion of the new opportunities in flexible microelectronics afforded by liquid-based processing.