The use of optical multiple patterning, necessitated by persistent delays in the readiness of EUV lithography, has resulted in very little increase in the write time per mask, but there has been a significant increase in the write time for an entire mask set, because of the large increase in the number of masks per set. Although operating lithographic processes near the physical resolution limit of optics, final dimensions continue to scale through the use of multiple patterning, and process control requirements are based on these final dimensions. This results in the need for tight critical dimension control and registration on masks. Although reduction of cost per transistor node-to-node can be continued by the use of multiple patterning, manufacturing cycle times are lengthened appreciably, which has economic impact. With EUV lithography, there are additional mechanisms for overlay errors resulting from non-telecentricity, and corrections will need to be included as part of RET and OPC generation. EUV masks will also need to be very flat or corrections will be required when masks are written. A limited number of small defects can be tolerated on EUV masks by the use of pattern shift methods to cover mask defects with absorber. Interconnect resistance and transistor performance are also significant challenges for enabling future scaling.

EUV lithography for resolution below 8 nm half pitch requires the numerical aperture (NA) of the projection lens to be significantly larger than the current state-of-the-art 0.33NA. In order to be economically viable, a throughput in the range of 100 wafers per hour is needed. As a result of the increased NA, the incidence angles of the light rays at the mask increase significantly. Consequently the shadowing and the variation of the multi-layer reflectivity deteriorate the aerial image contrast to unacceptably low values at the current 4x magnification. The only solution to reduce the angular range at the mask is to increase the magnification. Simulations show that we have to double the magnification to 8x in order to overcome the shadowing effects. Assuming that the mask infrastructure will not change the mask form factor, this would inevitably lead to a field size that is a quarter of the field size of current 0.33NA step and scan systems. This would reduce the throughput of the high-NA scanner to a value significantly below 100 wafers per hour unless additional measures are taken. This paper presents an anamorphic step and scan system capable to print fields that are half the field size of the current full field. The anamorphic system has the potential to achieve a throughput in excess of 150 wafers per hour by increasing the transmission of the optics as well as increasing the acceleration of the wafer stage and mask stage. This makes it an economically viable lithography solution. The proposed 4x/8x magnification is not the only logical solution. There are potentially other magnifications to increase the scanner performance while at the same time reducing the mask requirements.

Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target. Strictly speaking this quantity is not directly measurable in the fab, and furthermore it is not ultimately the most important metric for chip yield. What is of vital importance is the relative EPE (rEPE) between different design layers, and in the era of multi-patterning, the different constituent mask sublayers for a single design layer. There has always been a strong emphasis on measurement and control of misalignment between design layers, and the progress in this realm has been remarkable, spurned in part at least by the proliferation of multi-patterning which reduces the available overlay budget by introducing a coupling of alignment and CD errors for the target layer.

In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes.

This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.

193nm immersion lithography is the mainstream production technology for the 22nm half pitch (HP) DRAM manufacturing. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error may be a significant error contributor [3]. The International Technology Roadmap for Semiconductors (ITRS [1]) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 22nm HP node, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. DRAM makers moved several years ago to 6F2 (figure 1, [2]) cell design and thus printing tilted lines at 15 or 30 degree. Overlay of contact layer over buried line has to be well controlled.

However, measuring mask registration performance accurately on tilted lines was a challenge. KLA Tencor applied the model-based algorithm to enable the accurate registration measurement of tilted lines on the Poly layer as well as the mask-to-mask overlay to the adjacent contact layers. The metrology solution is discussed and measurement results are provided.

The understanding and control of the intra-field overlay budget becomes crucial particularly after the introduction of multi-patterning applications. The intra-field overlay budget is built-up out of many contributors, each with its own characteristic. Some of them are (semi-)static like the reticle writing error (RWE) fingerprint, the scanner lens fingerprint, or the intra-field processing signature. Others are more dynamic. Examples are reticle heating and lens heating due to the absorption of a small portion of the exposure light. Ideally, all overlay contributors that are understood and known could be taken out of the feed-back control loop and send as feed-forward corrections to the scanner. As a consequence, only non-correctable overlay residuals are measured on the wafer.

In the current work, we have studied the possibility to characterize the reticle writing error fingerprint by an off-line position measurement tool and use this information to send feed-forward corrections to the ASML TWINSCAN^TM exposure tool. The current work is an extension of the work we published earlier. To this end, we have selected a reticle pair out of 50 production reticles that are used to manufacture a 28-nm technology device. These two reticles are special in the sense that the delta fingerprint contains a significant higher order RWE signature. While previously only the linear parameters were sent as feed-forward corrections to the ASML TWINSCAN^TM exposure tool, this time we additionally demonstrate the capability to correct for the non-linear terms as well. Since the concept heavily relies on the quality of the off-line mask registration measurements, a state-of-the-art reticle registration tool was chosen. Special care was taken to eliminate any effects of the tool induced shifts that may affect the quality of the measurements. The on-wafer overlay verification measurements were performed on an ASML YieldStar metrology tool as well as on a different vendor tool.

In conclusion, we have extended and proven the concept of using off-line reticle registration measurements to enable higher order feed-forward corrections the ASML TWINSCAN^TM scanner. This capability has been verified by on-wafer overlay measurements. It is demonstrated that the RWE contribution in the overlay budget can be taken out of the feedback control loop and sent as feed-forward corrections instead. This concept can easily be extended when more scanner corrections become available.

The authors present a detailed observation of the charge-induced pattern positioning errors (CIPPEs) in a variableshape e-beam writer on an opaque-MoSi-over-glass (OMOG) mask by directly measuring the pattern shifts using a mask registration tool. The CIPPEs are found to have one short-range, that is exponentially decaying in space, and the other constant offset components. The exponential term that decays slowly in time, whereas the constant offset fast diminishes. By applying a charge dissipation layer (CDL), the authors experimentally verify that the exponential component results from the charges in resist. On the other hands, the constant offset that can not be eliminated by the CDL is speculated to be charges in the substrate according to the Monte Carlo simulation.

The industry is transitioning EUV lithography from feasibility phase to technology development. EUV mask infrastructure needs to be prepared to support the technology development and ready to enable the implementation of EUV lithography for production. In this paper, we review the current status and assess the readiness of key infrastructure modules in EUV mask fabrication, inspection and control, and usage in a mask cycle: blank quality and inspection, pattern inspection, defect disposition and repair, pellicle integration, and handling of pelliclized masks.

In this paper, the fabrication and initial characterization of an unsupported membrane composed of a single ultrathin silicon nitride (SiNx) layer with potential application as a EUV pellicle is described in detail. A full size free-standing pellicle with inner film area equal to 113x145mm and champion EUV transparency equal to 89.5% (single pass) is demonstrated utilizing the methodology presented in this study. The exemplary EUV transparency of the reported pellicle was achieved by limiting the membrane thickness to 16nm, while the intrinsic mechanical stability for the silicon nitride film was realized by adjusting the Si:N ratio to provide a non-stoichiometric layer featuring low tensile stress. The pellicle thickness, elemental composition and mass density were used to calculate the expected EUV transparency, which was found to be in good agreement with experimental EUV transmission measurements. Additionally, careful consideration was given to process-induced mechanical instabilities exerted on the ultrathin pellicle during the wet etch, rinsing and drying fabrication steps, and a unique yet simple set of ancillary hardware, materials and processing techniques was introduced to minimize such disturbances and yield large-area pellicles that are free of visible defects and wrinkles. In the absence of commercially available actinic inspection tools, a distinctive advantage of the SiNx membrane versus a Silicon-based EUV pellicle solution is the demonstrated ArF transmission, making it attractive for through-pellicle mask defect inspection and advanced metrology work utilizing available 193nm excimer laser and detection systems. A preliminary heat load test indicates that the SiNx-based EUV pellicle would be marginally compatible with an equivalent 80W EUV source.

A learning system has been exploited for the mask inspection tool with the Projection Electron Microscope (PEM). The defect is identified by the PEM system using the "defectivity". The detection capability for hp11nm EUV masks is demonstrated. The learning system for PEM consists of the library of the registered defects. The learning system totally optimizes detection capability reconciling the previously registered defects and the newly registered defect. We have verified the effectiveness of the learning system. We can provide a user-friendly mask inspection system with the higher throughput by PEM and with the smaller cost of ownership by the development.

EUV masks include many different layers of various materials rarely used in optical masks, and each layer of material has a particular role in enhancing the performance of EUV lithography. Therefore, it is crucial to understand how the mask quality and patterning performance can change during mask fabrication, EUV exposure, maintenance cleaning, shipping, or storage.

SPM (Sulfuric acid peroxide mixture) which has been extensively used for acid cleaning of photomask and wafer has serious drawback for EUV mask cleaning. It shows severe film loss of tantalum-based absorber layers and limited removal efficiency of EUV-generated carbon contaminants on EUV mask surface.

Here, we introduce such novel cleaning chemicals developed for EUV mask as almost film loss free for various layers of the mask and superior carbon removal performance. Combinatorial chemical screening methods allowed us to screen several hundred combinations of various chemistries and additives under several different process conditions of temperature and time, eventually leading to development of the best chemistry selections for EUV mask cleaning.

Recently, there have been many activities for the development of EUV pellicle, driven by ASML and core EUV scanner customer companies. It is still important to obtain film-loss free cleaning chemicals because cleaning cycle of EUV mask should be much faster than that of optic mask mainly due to EUV pellicle lifetime. More frequent cleaning, combined with the adoption of new materials for EUV masks, necessitates that mask manufacturers closely examine the performance change of EUV masks during cleaning process.

We have investigated EUV mask quality changes and film losses during 50 cleaning cycles using new chemicals as well as particle and carbon contaminant removal characteristics. We have observed that the performance of new chemicals developed is superior to current SPM or relevant cleaning chemicals for EUV mask cleaning and EUV mask lifetime elongation.

In this paper, we present a detail study of the impact of material-induced phase effect on the EUV mask absorber defect through-focus behavior. Illumination, material properties, and defect size are shown to have different impacts on the behavior. Also, we study the possibility of using alternative absorber materials to reduce the phase effects on the defect. Based on the mask near field distribution, energy confinement and phase accumulation can be reduced with new absorber materials. The defect sensitivity is reduced and the peak signal position is closer to the best focus due to less material-induced phase. Moreover, the novel pupil engineering method can utilize the phase induced by the material to improve the defect sensitivity of absorber defect by adding lens phase shifts in the pupil plane. At least 29% enhancement of the absorber defect signal at focus can be achieved by optimum lens phase shifts.

Self-aligned multiple patterning (SAMP), due to its low overlay error, has emerged as the leading option for 1D gridded back-end-of-line (BEOL) in sub-14nm nodes. To form actual routing patterns from a uniform "sea of wires", a cut mask is needed for line-end cutting or realization of space between routing segments. Constraints on cut shapes and minimum cut spacing result in end-of-line (EOL) extensions and non-functional (i.e. dummy fill) patterns; the resulting capacitance and timing changes must be consistent with signoff performance analyses and their impacts should be minimized.

In this work, we address the co-optimization of cut mask layout, dummy fill, and design timing for sub-14nm BEOL design. Our central contribution is an optimizer based on integer linear programming (ILP) to minimize the timing impact due to EOL extensions, considering (i) minimum cut spacing arising in sub-14nm nodes; (ii) cut assignment to different cut masks (color assignment); and (iii) the eligibility to merge two unit-size cuts into a bigger cut. We also propose a heuristic approach to remove dummy fills after the ILP-based optimization by extending the usage of cut masks. Our heuristic can improve critical path performance under minimum metal density and mask density constraints.

In our experiments, we study the impact of number of cut masks, minimum cut spacing and metal density under various constraints. Our studies of optimized cut mask solutions in these varying contexts give new insight into the tradeoff of performance and cost that is afforded by cut mask patterning technology options.

We evaluate the performance of several phase retrieval algorithms using through-focus aerial image measurements of patterned EUV photomasks. Patterns present a challenge for phase retrieval algorithms due to the high- contrast and strong diffraction they produce. For this study, we look at the ability to correctly recover phase for line-space patterns on an EUV mask with a TaN absorber and for an etched EUV multilayer phase shift mask. The recovered phase and amplitude extracted from measurements taken using the SHARP EUV microscope at Lawrence Berkeley National Laboratory is compared to rigorous, 3D electromagnetic simulations. The impact of uncertainty in background intensity, coherence, and focus on the recovered field is evaluated to see if the algorithms respond differently.

Mask topography contributes to phase at the wafer plane, even for OMOG binary masks currently in use at the 22nm node in deep UV (193nm) lithography. Here, numerical experiments with rigorous FDTD simulation are used to study the impact of mask 3D effects on aerial imaging, by varying the height of the absorber stack and its sidewall angle. Using a thin mask boundary layer model to fit to rigorous simulations it is seen that increasing the absorber thickness, and hence the phase through the middle of a feature (bulk phase) monotonically changes the wafer-plane phase. Absorber height also influences best focus, revealed by an up/down shift in the Bossung plot (linewidth vs. defocus). Bossung plot tilt, however, responsible for process window variability at the wafer, is insensitive to changes in the absorber height (and hence also the bulk phase). It is seen to depend instead on EM edge diffraction from the thick mask edge (edge phase), but stays constant for variations in mask thickness within a 10% range. Both bulk phase and edge phase are also independent of sidewall angle fluctuation, which is seen to linearly affect the CD at the wafer, but does not alter wafer phase or the defocus process window. Notably, as mask topography varies, the effect of edge phase can be replicated by a thin mask model with 8nm wide boundary layers, irrespective of absorber height or sidewall angle. The conclusions are validated with measurements on phase shifting masks having different topographic parameters, confirming the strong dependence of phase variations at the wafer on bulk phase of the mask absorber.

In this paper, a quantitative method to analyze the effective range of fogging effect from massive data is presented. According to the calculated effective range, we use two approaches to correct the pattern-dependent CD error that come from e-beam writing. One is the fogging effect correction(FEC), which uses a Gaussian distributed model to describe FE. Second, we implement dosage modulation based on the assumption that the error caused by FE is linearly proportional to the pattern density of a mask. In summary, we are able to successfully predict the map of CD error for various layouts, and correct the error caused by FE in mask-making.

EUV reticles need to be considered as complex optical elements in the beam path with considerable impact on lithography. Here we present a work flow for absorber optimization by applying a complementary approach of investigating lithographic metrics and mask-topography induced phase aberrations.

In the first part this complementary approach is applied to find an optimum thickness of a typical Ta-based absorber for imaging horizontal spaces through pitch. And although an absorber thickness of around 70 nm is found to be preferable for this particular application, the thickness choice leads to conflicting results for the general printability of 10 nm technology node features. Hence we show that a moderate reduction of the absorber thickness can be allowed when the mask bias of these features is optimized appropriately. The moderate thickness reduction already allows for the mitigation of some of the conflicting imaging aspects.

In the second part we expand the workflow by analyzing phase aberrations in n & k material space. This phase-based optical property screening shows that an alternative absorber based on materials such as Ni with k higher than Ta show superior best focus and contrast metrics. These alternative absorber embodiments would allow the overall reduction of M3D effects and adverse application dependencies of current Ta-based absorbers due to a combination of thickness reduction and enhancement of absorption.

As Extreme Ultraviolet (EUV) lithography has matured, numerous imposing technical challenges have been the focus of intense scrutiny, including the EUV radiation source, reflective optics, and fundamental mask fabrication. There has been a lurking question on the state of mask defectivity that has been almost unanswerable until the recent relative maturation of the rest of the infrastructure. Without readily available actinic blank or patterned inspection systems, EUV blank and mask manufacturers must continue to rely on relatively low resolution optical systems for blank characterization. Despite best efforts, detectable defects still exist; these can be classified into three types: small defects that can be avoided through pattern-shift, medium defects that can be repaired, and large defects which must be suppressed during manufacture. To successfully intercept high-volume-manufacturing (HVM) for the 7nm node, aggressive, continued industry focus is required to ensure that these three defect types are addressed. Without actinic mask inspection, an unknown element with EUV lithography continues to be the presence of nondetected printable defects – defects that print on wafer despite being undetected during mask or blank fabrication. Another risk is that until recently, focus has been on developing techniques to identify catastrophic defects, while past manufacturing experience tells us that much more subtle defects (<10% CD variation) can have significant impact on yield and performance. Using information from many characterization sources, including blank inspections, patterned inspection, atomic-force microscopy (AFM), scanning-electron microscopy (SEM), as well as 36nm and 32nm pitch wafer printing results, we will try to address what the real current state of mask defectivity is. We will discuss techniques to answer the key questions of: “What defects print, what defects do not, and what might our inspections methods be missing?” From this vantage point, we will analyze the current mask defectivity rates and sources, and assess the gap in capability to support full HVM support.

Extreme ultraviolet lithography (EUV) advances printability of small size features for both memory and logic semiconductor devices. It promises to bring relief to the semiconductor manufacturing industry, removing the need for multiple masks in rendering a single design layer on wafer. However, EUV also brings new challenges, one of which is of mask defectivity. For this purpose, much of the focus in recent years has been in finding ways to adequately detect, characterize, and reduce defects on both EUV blanks and patterned masks.

In this paper we will present an efficient way to classify and disposition EUV mask defects through a new algorithm developed to classify defects located on EUV photomasks. By processing scanning electronmicroscopy images (SEM) of small regions of a photomask, we extract highdimensional local features Histograms of Oriented Gradients (HOG). Local features represent image contents compactly for detection or classification, without requiring image segmentation. Using these HOGs, a supervised classification method is applied which allows differentiating between nondefective and defective images. In the new approach we have developed a superior method of detection and classification of defects, using mask and supporting mask printed data from several metallization masks. We will demonstrate that use of the HOG method allows realtime identification of defects on EUV masks regardless of geometry or construct.

The defects identified by this classifier are further divided into subclasses for mask defect disposition: foreign material, foreign material from previous step, and topological defects. The goal of disposition is to categorize on the images into subcategories and provide recommendation of prescriptive actions to avoid impact on the wafer yield.

Several challenges hinder EUV photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. By using known defect locations on a blank, the mask design can be intentionally shifted to avoid patterning directly over a defect. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for various measurement errors, based on the latest HVM inspection and write tool capabilities, is first established and then verified post-patterning. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed using OPC’d 7 nm node fully functional chip designs that were also recently used to fabricate working 7 nm node devices. Probability of defect-free masks are explored for various 7 nm mask levels, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks for the 7 nm node.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The purpose of this paper is to describe the technology advancements made to both wafer imprint and mask replication systems that will be applied for the fabrication of advanced devices such as NAND Flash memory and DRAM. Overlay of better than 5nm (mean + 3sigma) has been demonstrated, and throughputs of better than 10 wafers per imprint station are now routinely achieved. Defectivity has been reduced by more than two orders of magnitude and particle adders within the tool have come down by approximately four orders of magnitude. A pilot line tool, the FPA- 1100 NZ2, was used to generate most of the results in this work. Additionally, particle control in a mask replication tool is addressed, with the purpose of extending the

Mask inspection tool with DUV laser source has been used for Photo-mask production in many years due to its high sensitivity, high throughput, and good CoO. Due to the advance of NGL technology such as EUVL and Nano-imprint lithography (NIL), there is a demand for extending inspection capability for DUV mask inspection tool for the minute pattern such as hp4xnm or less. But current DUV inspection tool has sensitivity constrain for the minute pattern since inspection optics has the resolution limit determined by the inspection wavelength and optics NA.

Based on the unresolved pattern inspection capability study using DUV mask inspection tool NPI-7000 for 14nm/10nm technology nodes, we developed a new optical imaging method and tested its inspection capability for the minute pattern smaller than the optical resolution. We confirmed the excellent defect detection capability and the expendability of DUV optics inspection using the new inspection method. Here, the inspection result of unresolved hp26/20nm pattern obtained by NPI-7000 with the new inspection method is descried.

Simulations of the optical intensity within Nano Imprint Lithography (NIL) mask features have been made for patterned quartz masks having ultrathin film coatings with different indices of refraction. Fractionally fluorine terminated surfaces, previously proposed for improving the yield of NIL processes, are briefly reviewed. Optical intensity solutions within the feature were obtained using Panoramictech Maxwell solver software for variances in the optical constants of the coating films, aspect ratio, feature size, and wavelength.. The coated masks have conformal surface, higher index of refraction under-layer coating and a fractional terminated fluorine hydrocarbon (FHC) monomolecular layer. The values of optical constants for the FHC layers are unknown, so a range of ad-hoc values were simulated. Optical constants for quartz mask and Al₂O₃, TiO2 and Si under-layer films are taken from the literature. Wavelengths were varied from 193nm to 365nm. The question of photo-dissociation of the FHC layer for higher energy photons is addressed from first principles, with the result that the F-terminated layers are stable at higher wavelengths. Preliminary simulations for features filled with resist over various substrates are dependent on the antireflection character of the underlying film system. The optical intensity is generally increased within the simulated mask feature when coated with a higher index/FHC films relative to the uncoated reference quartz mask for ~5nm physical feature sizes.

Process matching is the ability to precisely reproduce the signature of a given fabrication process while using a different one. A process signature is typically described as systematic CD variation driven by feature geometry as a function of feature size, local density or distance to neighboring structures. The interest of performing process matching is usually to address differences in the mask fabrication process without altering the signature of the mask, which is already validated by OPC models and already used in production. The need for such process matching typically arises from the expansion of the production capacity within the same or different mask fabrication facilities, from the introduction of new, perhaps more advanced, equipment to deliver same process of record masks and/or from the re-alignment of processes which have altered over time. For state-of-the-art logic and memory mask processes, such matching requirements can be well below 2nm and are expected to reduce below 1nm in near future. In this paper, a data preparation solution for process matching is presented and discussed. Instead of adapting the physical process itself, a calibrated model is used to modify the data to be exposed by the source process in order to induce the results to match the one obtained while running the target process. This strategy consists in using the differences among measurements from the source and target processes, in the calibration of a single differential model. In this approach, no information other than the metrology results is required from either process. Experimental results were obtained by matching two different processes at Photronics. The standard deviation between both processes was of 2.4nm. After applying the process matching technique, the average absolute difference between the processes was reduced to 1.0nm with a standard deviation of 1.3nm. The methods used to achieve the result will be described along with implementation considerations, to help assess viability for model driven data solutions to play a role in future, critical mask matching efforts.

The value of using multiple dose levels for individual shots on VSB (Variable Shaped Beam) mask writers has been demonstrated earlier [1][2]. The main advantage of modulating dose on a per shot basis is the fact that higher dose levels can be used selectively for critical features while other areas of the mask with non-critical feature types can be exposed at lower dose levels. This reduces the amount of backscattering and mask write time penalty compared to a global overdose-undersize approach.

While dose assignment to certain polygons or parts of polygons (VSB shots) can easily be accomplished via DRC rules on layers with limited shape variations like contact or VIA layers, it can be challenging to come up with consistent rules for layers consisting of a very broad range of shapes, generally found on metal layers.

This work introduces a method for fully model-based modulation of shot dose for VSB machines supporting between two and eight dose levels and demonstrates results achieved with this method.

It became more challenging to guarantee the overall mask Critical Dimension (CD) quality according to the increase of hot spots and assist features at leading edge devices. Therefore, mask CD correction methodology has been changing from the rule-based (and/or selective) correction to model-based MPC (Mask Process Correction) to compensate for the through-pitch linearity and hot spot CD errors.

In order to improve mask quality, it is required to have accurate MPC model which properly describes current mask fabrication process. There are limits on making and defining accurate MPC model because it is hard to know the actual CD trend such as CD linearity and through-pitch owing to the process dispersion and measurement error. To mitigate such noises, we normally measure several sites of each pattern types and then utilize the mean value of each measurement for MPC modeling. Through those procedures, the noise level of mask data will be reduced but it does not always guarantee improvement of model accuracy, even though measurement overhead is increasing. Root mean square (RMS) values which is usually used for accuracy indicator after modeling actually does not give any information on accuracy of MPC model since it is only related with data noise dispersion.

In this paper, we reversely approached to identify the model accuracy. We create the data regarded as actual CD trend and then create scattered data by adding controlled dispersion of denoting the process and measurement error to the data. Then we make MPC model based on the scattered data to examine how much the model is deviated from the actual CD trend, from which model accuracy can be investigated. It is believed that we can come up with appropriate method to define the reliability of MPC model developed for optimized process corrections.

In a previous work [1] we demonstrated that current OPC model assuming the mask pattern to be analogous to the designed data is no longer valid. Indeed as depicted in figure 1, an extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason an accurate mask model, for a 14nm logic gate level has been calibrated. A model with a total RMS of 1.38nm at mask level was obtained. 2D structures such as line-end shortening and corner rounding were well predicted using SEM pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular, as depicted in figure 2.

EUV mask protection during handling and exposure remains a challenge for high volume manufacturing using EUV scanners. A thin, transparent membrane can be mounted above the mask pattern so that any particle that falls onto the front of the mask is held out of focus and does not image. The fluoropolymer membranes that are compatible with 193nm lithography absorb too strongly at the 13.5nm EUV exposure wavelength to be considered. Initially, the industry planned to expose EUV masks without any pellicle; however, the time and cost of fabricating and qualifying an EUV mask is simply too high to risk decimating wafer yield each time a particle falls onto the mask pattern. Despite the challenges of identifying a membrane for EUV, the industry has returned to the pellicle concept for protection. EUVL pellicles have been in development for more than a decade and reasonable options exist. Meeting all pellicle requirements is difficult, so this type of risk-mitigation effort is needed to ensure that there is a viable high-volume manufacturing option. This paper first reviews the desired membrane properties for EUVL pellicles. Next, candidate materials are introduced based on reported properties and compatibility with fabrication. Finally a set of candidate membranes are fabricated. These membranes are screened using a simplified set of tests to assess their suitability as an EUV pellicle. EUV transmission, film stress, and film durability data are included. The results are presented along with general guidelines for pellicle membrane properties for EUV manufacturing.

Patterned mask inspection for an etched multilayer (ML) EUV mask was investigated. In order to optimize the mask structure from the standpoint of not only a pattern inspection by using a projection electron microscope (PEM), but also by considering the other fabrication processes using electron beam (EB) techniques such as CD metrology and mask repair, we employed a conductive layer between the ML and substrate. By measuring the secondary electron emission coefficients (SEECs) of the candidate materials for conductive layer, we evaluated the image contrast and the influence of charging effect. In the cases of 40-pair-ML, 16 nm sized extrusion and intrusion defects were found to be detectable more than 10 sigma in hp 44 nm, 40 nm, and 32 nm line and space (L/S) patterns. Reducing 40-pair-ML to 20-pair-ML degraded the image contrast and the defect detectability. However, by selecting B₄C as a conductive layer, 16 nm sized defects remained detectable. These defects were also detected after the etched part was refilled with Si. Moreover, the simulation shows a high sensitivity for detecting the residual-type defects (etching residues). A double layer structure with 2.5-nm-thik B₄C on metal film used as a conductive layer was found to have sufficient conductivity and also was found to be free from the surface charging effect and influence of native oxide.

Traditional EUV masks, with absorber on top of the multi-layer (ML) mirror, generally suffer from mask 3D effects: H/V shadowing, best focus shifts through pitch and pattern shifts through focus. These effects reduce the overlapping process window, complicate optical proximity correction and generate overlay errors. With further pitch scaling, these mask 3D effects are expected to become stronger, increasing the need for a compensation strategy.

In this study, we have proven by simulations and experiments that alternative mask technologies can lower mask 3D effects and therefore have the potential to improve the imaging of critical EUV layers.

We have performed an experimental imaging study of a prototype etched ML mask, which has recently become available. This prototype alternative mask has only half the ML mirror thickness (20 Mo/Si pairs) and contains no absorber material at all. Instead, the ML mirror is etched away to the substrate at the location of the dark features. For this etched ML mask, we have compared the imaging performance for mask 3D related effects to that of a standard EUV mask, using wafer exposures at 0.33 NA. Experimental data are compared to the simulated predictions and the benefits and drawbacks of such an alternative mask are shown. Besides the imaging performance, we will also discuss the manufacturability challenges related to the etched ML mask technology.

No abstract available.

To prevent catastrophic failures in wafer manufacturing lines from reticle defects, mask manufacturers employ sophisticated reticle inspection systems to examine every shape on every reticle for defects. The predominant inspection systems in use today compare the reticle directly with the design database using high-NA optics (typically 3x higher resolution at the reticle plane than advanced wafer scanners).

High-NA optical inspection with its high signal to noise ratio (SNR) can readily detect small defects before they have lithographic impact, thus ensuring reticle quality. However, when inspecting certain aggressive OPC, high-NA inspection can overload on small OPC defects which do not have lithographic impact and thus, should generally be ignored.

Whereas, inspecting a reticle as imaged in the wafer plane (low-NA in the reticle plane) will generally ignore such small OPC defects; however, the SNR is often too low for certain defect types to provide the needed defect detection sensitivity to ensure reticle quality.

This paper discusses the design and performance of a novel reticle inspection method using high-NA and low-NA dual optical imaging and processing. This method offers the high defect sensitivity of high-NA inspection with the OPC tolerance of low-NA inspection. These two imaging methods are blended together into a seamless inspection mode suitable for aggressive OPC of the 14nm generation and beyond. The test reticles include 14nm logic designs containing aggressive OPC and native defects, as well as a 14 nm test reticle containing relevant programmed defects. Defect lithographic significance is judged using a Zeiss AIMS™ system.

A programmed phase defect Extreme Ultraviolet (EUV) mask was fabricated and measurement repeatability of the defect size using a scanning probe microscope (SPM) was evaluated. The SPM measurement results indicated that the defect size variation as registered by the measurement repeatability were much smaller than the defect-to-defect variations. It means the defect-to-defect variation in size actually does exist. Some defects were found where their sizes before a multilayer coating (on quartz) were all the same but after the coat their sizes varied quite significantly when observed on the multilayer. This result indicated that it is difficult to estimate the phase defect size on quartz, whereas they can be accurately measured on multilayer. Influences of the defect size variation on defect detection signal intensity (DSI) using an actinic blank inspection (ABI) system were examined; their influences on the wafer printability were also examined. The DSI was strongly correlated with defect depth on the multilayer, and it was also indicated that the ABI can detect small variations in defect sizes. It was also confirmed that the impact of the phase defects on wafer printed CDs were proportional to the DSIs, and that the ABI has a potential to detect phase defect that could cause 5 % of the CD error when printing 16 nm dense lines.

Improving our collective understanding of extreme ultraviolet (EUV) photomask defects and the imaging properties of available defect imaging tools is essential for improving EUV mask defectivity, defect repair and mitigation, and for high-level strategic decision-making. In this work, we perform a qualitative comparison of twenty-five defects imaged with mask scanning electron microscopy (SEM), EUV actinic mask imaging, and wafer SEM imaging. All but two of the defect locations were first identified by non-actinic mask blank inspection, prior to patterning. The others were identified as repeating defects on the wafer. We find that actinic defect imaging is predictive of the wafer prints, with small-scale features clearly replicated. While some mask defect SEM images match the wafer prints, others print with a larger outline indicating the presence of sub-surface disruptions hidden from the SEM’s view. Fourteen other defects were subjected to an aerial image phase measurement method called Fourier Ptychography (FP). Although phase shifts were observed in the larger defects, the smaller defects in the dataset showed no significant phase shifting. We attribute this discrepancy to non-actinic mask blank inspection’s limited ability to detect small phase defects under normal operating conditions.

A sensitivity analysis (SA) algorithm was developed and tested to comprehend the influences of different test pattern sets on the calibration of a point spread function (PSF) model with complementary approaches. Variance-based SA is the method of choice. It allows attributing the variance of the output of a model to the sum of variance of each input of the model and their correlated factors.¹ The objective of this development is increasing the accuracy of the resolved PSF model in the complementary technique through the optimization of test pattern sets. Inscale® from Aselta Nanographics is used to prepare the various pattern sets and to check the consequences of development. Fraunhofer IPMS-CNT exposed the prepared data and observed those to visualize the link of sensitivities between the PSF parameters and the test pattern. First, the SA can assess the influence of test pattern sets for the determination of PSF parameters, such as which PSF parameter is affected on the employments of certain pattern. Secondly, throughout the evaluation, the SA enhances the precision of PSF through the optimization of test patterns. Finally, the developed algorithm is able to appraise what ranges of proximity effect correction is crucial on which portion of a real application pattern in the electron beam exposure.

While the industry is making progress to offer EUV lithography schemes to attain ultimate critical dimensions down to 20 nm half pitch, an interim optical lithography solution to address an immediate need for resolution is offered by various integration schemes using advanced PSM (Phase Shift Mask) materials including thin e-beam resist and hard mask. Using the 193nm wavelength to produce 10nm or 7nm patterns requires a range of optimization techniques, including immersion and multiple patterning, which place a heavy demand on photomask technologies. Mask schemes with hard mask certainly help attain better selectivity and hence better resolution but pose integration challenges and defectivity issues. This paper presents a new photomask etch solution for attenuated phase shift masks that offers high selectivity (Cr:Resist > 1.5:1), tighter control on the CD uniformity with a 3sigma value approaching 1 nm and controllable CD bias (5-20 nm) with excellent CD linearity performance (<5 nm) down to the finer resolution. The new system has successfully demonstrated capability to meet the 10 nm node photomask CD requirements without the use of more complicated hard mask phase shift blanks. Significant improvement in post wet clean recovery performance was demonstrated by the use of advanced chamber materials. Examples of CD uniformity, linearity, and minimum feature size, and etch bias performance on 10 nm test site and production mask designs will be shown.

In order to maintain the lithographic margin and to have sufficient image resolution, attenuated phase shift masks are widely used as a resolution enhancement technique. To improve the radiation durability of the phase shift film, we have developed low oxidation MoSi shifters, such as A6L2, as one option for improving radiation durability. But to provide the best radiation durability, we have developed a new approach eliminating the molybdenum from the phase shift film and introduced a Silicon-Nitride (Si-N) based attenuated phase shift film. Traditionally the transmittance of the phase shift layer is usually around 6%. In the case of a pure Si3N4 film, the transmittance with 180 degree phase shift is around 18%. But, by controlling film structure with a combination of Si-N the transmittance can be tuned to the customers desired transmission value for high durability Mo free attenuated phase shift films.

A variety of repairs on EUV multilayer were conducted including protection against pattern degradation in manufactural use in order to evaluate feasibility of multilayer repair and the protection schemes. The efficacy of post-repair protection techniques are evaluated to determine the lifetime of multilayer repairs. Simulations were used to select the optimal material thicknesses for repair protection, and the simulation results are verified with the lithographic results. The results showed a high correlation coefficient. Finally, all repaired sites were cleaned multiple times to quantify repair durability and impact on wafer CD. Aerial imaging of the repair sites before and after cleans shows a dramatic degradation of wafer CD post-cleaning. However, we show that applying a surface protection material after multilayer repair successfully mitigates the influence of multilayer degradation during extensive manufacturing operations.

A proper surface treatment, such as O2 plasma, helps to improve particle removal efficiency (PRE) because of the formation of hydrogen bonding between particles, water and the mask surface after treatment. The effectiveness of surface treatments cannot be determined only by the static wettability after processes. More key indexes should be considered. In this paper, we report our findings on the relationship between surface treatments on photomasks and the resulting wettability. In addition, added defects after the treatment and the cleaning process were inspected with a 193- nm KLA inspector on 193-nm immersion and EUV photomasks, which consist of SiO₂, MoSi, Cr, Ta-based absorber and Ru. Based on our work, three indexes can be built for determining the effectiveness of surface treatments. The first is to check whether the surface becomes super-hydrophilic after treatment. The second is to determine the efficiency of surface treatments on enhancing wettability. The last is to quantify the added watermark count after the surface treatment and the cleaning process. With a proper surface treatment, watermarks can be greatly eased. These three indexes can quickly determine possible effective methods for treating the surfaces of different materials.

Defects on a reticle are inspected, reviewed, and repaired by different tools. They are located by automated optical inspection (AOI); however, if the characteristic size of defects is similar to that of light and electron beam wavelengths, they are often unclassified or misclassified by AOI. Atomic force microscopes (AFM) along with electron microscopes are used for investigating defects located by AOI to distinguish false defects from real defects and effectively classify them. Both AFM and electron microscopes provide high resolution images. However, electron microscopy is known to be destructive and have less accuracy in 3rd dimension measurement compared to AFM [1]. On the other hand, AFM is known to have low throughput and limited tip life in addition to requiring significant effort to finding the defects. These limitations emanate from having to perform multiple large scans to find the defect locations, to compensate for stage coordinate inaccuracies, and to correct the mismatch between the AFM and the AOI tools.

In this work we introduce automatic defect review (ADR) AFM for defect study and classification of EUV mask reticles that overcomes the aforementioned limitations of traditional AFM. This metrology solution is based on an AFM configuration with decoupled Z and XY scanners that makes it possible to collect large survey images with minimum out of plane motion. To minimize the stage errors and mismatch between the AFM and the AOI coordinates, the coordinates of fiducial markers are used for coarse alignment. In addition, fine alignment of the coordinates is performed using enhanced optical vision on marks on the reticle. The ADR AFM is used to study a series of phase defects identified by an AOI tool on a reticle. Locating the defects, imaging, and defect classification are performed using the ADR automation software and with the throughput of several defects per hour. In order to preserve tip life and data consistency, AFM imaging is performed in non-contact mode. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for defect review and classification. Therefore this technology can be used for in-line defect review and classification for mask repair.

In the absence of pellicle a EUVL reticle is expected to withstand up to 100x cleaning cycles. Surface damage upon wet and dry cleaning methods has been investigated and reported in recent years. [1] Thermal stress, direct photochemical oxidation and underlying Silicon layer oxidation are reported as the most relevant root-causes for metal damage and peeling off. [2,3] An investigation of final clean performance is here reported as a function of operating pH; the results show increased Ruthenium durability in moderately alkaline environment. The electrochemical rationale and the dependency of the reducing strength of the media with the pH will be presented as possible explanations for reduced damage.

With shrinking pattern size at 0.33NA EUV lithography systems, mask 3D effects are expected to become stronger, such as horizontal/vertical shadowing, best focus shifts through pitch and pattern shift through focus. Etched multilayer EUV mask structures have been proposed in order to reduce mask 3D effects. It is estimated that etched multilayer type mask is also effective in reducing mask 3D effects at 0.33NA with lithographic simulation, and it is experimentally demonstrated with NXE3300 EUV Lithography system. We obtained cross-sectional TEM image of etched multilayer EUV mask pattern. It is observed that patterned multilayer width differs from pattern physical width. This means that effective reflecting width of etched multilayer pattern is smaller than pattern width measured by CD-SEM. In this work, we evaluate mask durability against both chemical and physical cleaning process to check the feasibility of etched multilayer EUV mask patterning against mask cleaning for 0.33NA EUV extension. As a result, effective width can be controlled by suitable cleaning chemicals because sidewall film works as a passivation film. And line and space pattern collapse is not detected by DUV mask pattern inspection tool after mask physical cleaning that includes both megasonic and binary spray steps with sufficient particle removal efficiency.

Key enabler of the successful introduction of EUV lithography into volume production is the EUV mask infrastructure. For the production of defect free masks, actinic review of potential defect sites to decide on the need for repair or compensation is required. Also, the repair or compensation with the ZEISS MERiT electron beam repair tool needs actinic verification in a closed loop mask repair solution. For the realization of actinic mask review, ZEISS and the SEMATECH EUVL Mask Infrastructure consortium started a development program for an EUV aerial image metrology system, the AIMS^TM EUV, with realization of a prototype tool. The development and prototype realization of the AIMS^TM EUV has entered the tool calibration and qualification phase utilizing the achieved capabilities of EUV aerial image acquisition and EUV mask handling. In this paper, we discuss the current status of the prototype qualification and show recent measurement results.

To evaluate defects on extreme ultraviolet (EUV) masks at the blank state of manufacturing, we developed a micro coherent EUV scatterometry microscope (micro-CSM). The illumination source is coherent EUV light with a 140-nm focus diameter on the defect using a Fresnel zoneplate. This system directly observes the reflection and diffraction signals from a phase defect. The phase and the intensity image of the defect is reconstructed with the diffraction images using ptychography, which is an algorithm of the coherent diffraction imaging. We observed programmed phase defect on a blank EUV mask. Phase distributions of these programmed defect were well reconstructed quantitatively. The micro-CSM is very powerful tool to review an EUV phase defect.

Extreme ultraviolet (EUV) lithography is considered as one of the viable solutions for production of the next generation integrated devices. EUV mask defect control becomes more critical issue in order to sustain the quality of wafer fabrication process. Since pellicle is the essential component to prevent patterning deformations caused by particle defects on EUV mask[1-2], EUV OPC (optical proximity correction) that takes into account for pellicle effects on imaging quality is required for achieving better pattern fidelity and critical dimension control. In this study, image blurring effect induced by the EUV mask pellicle on mask pattern structures was investigated and it was found that the localized short-range OPC using commercial software performed as desired considering transmission intensity loss due to pellicle. For experiment, edge placement error differences of the same 2D logic patterns with 16 nm half pitch with and without pellicle were compared. Finally, a method was suggested how patterning throughput loss caused by the transmission loss can be compensated by EUV OPC, which may allow pellicle transmission even below 90%.

Demand for mask process correction (MPC) is growing facing the 14nm era. We have developed model based MPC and can generate mask contours by using this mask process model. This mask process model consists of EB (development) and etch, which employs a threshold (level set) model and a variable bias model respectively. The model calibration tool accepts both CD measurement results and SEM images. The simulation can generate mask image (contour), runs with distributed computing resources, and has scalable performance.

The contour simulation shows the accuracy of the MPC correction visually and provides comprehensive information about hot spots in mask fabrication. Additionally, it is possible to improve lithography simulation quality by providing a simulated mask contour.

In this paper, accuracy and computational performance of mask process simulation are shown. The focus is on the difference between the calibration methods using CDs or images.

Implant layers must cover both logic and SRAM devices with good fidelity even if feature density and pitch differ very much. The coverage design rules of implant layers for SRAM and logic to active layer can vary. Lithography targeting could be problematic, since it may cause issues of either over exposure in logic area or under exposure in SRAM area. The rule-based (RB) re-targeting in the SRAM issue features is to compensate the under exposure in SRAM area. However, the global sizing in SRAM may introduce some bridge issues. Selective targeting and communicating with active layer is necessary. Another method is to achieve different mean-to-nominal (MTN) in some special areas during the reticle process. Such implant wafer issues can also be resolved during the lithography and mask optimized data preparing flow or named as lithography tolerance mask process correction (MPC).

In this manuscript, this conventional issue will be demonstrated which is either over exposure in logic area or under exposure in bitcell area. The selective rule-based re-targeting concerning active layer will also be discussed, together with the improved wafer CDSEM data. The alternative method is to achieve different mean-to-nominal in different reticle areas which can be realized by lithography tolerance MPC during reticle process. The investigation of alternative methods will be presented, as well as the trade-off between them to improve the wafer uniformity and process margin of implant layers.

The fine pattern exposure techniques are required for Flat Panel display applications as smart phone, tablet PC recently. The attenuated phase shift masks (PSM) are being used for ArF and KrF photomask lithography technique for high end pattern Semiconductor applications. We developed CrOx based large size PSM blanks that has good uniformity on optical characteristics for FPD applications. We report the basic optical characteristics and uniformity, stability data of large sized CrOx PSM blanks.

As the mask specifications become tighter for low k1 lithography, more aggressive repair accuracy is required below sub 20nm tech. node. To meet tight defect specifications, many maskshops select effective repair tools according to defect types. Normally, pattern defects are repaired by the e-beam repair tool and soft defects such as particles are repaired by the nanomachining tool. It is difficult for an e-beam repair tool to remove particle defects because it uses chemical reaction between gas and electron, and a nanomachining tool, which uses physical reaction between a nano-tip and defects, cannot be applied for repairing clear defects.

Generally, film deposition process is widely used for repairing clear defects. However, the deposited film has weak cleaning durability, so it is easily removed by accumulated cleaning process. Although the deposited film is strongly attached on MoSiN(or Qz) film, the adhesive strength between deposited Cr film and MoSiN(or Qz) film becomes weaker and weaker by the accumulated energy when masks are exposed in a scanner tool due to the different coefficient of thermal expansion of each materials. Therefore, whenever a re-pellicle process is needed to a mask, all deposited repair points have to be confirmed whether those deposition film are damaged or not. And if a deposition point is damaged, repair process is needed again. This process causes longer and more complex process.

In this paper, the basic theory and the principle are introduced to recover clear defects by using nanomachining tool, and the evaluated results are reviewed at dense line (L/S) patterns and contact hole (C/H) patterns. Also, the results using a nanomachining were compared with those using an e-beam repair tool, including the cleaning durability evaluated by the accumulated cleaning process. Besides, we discuss the phase shift issue and the solution about the image placement error caused by phase error.

Higher resolution is eagerly requested to the electron beam resist for the next generation photomask production as well as higher sensitivity. The performance of a polymer resist is mainly characterized by its chemical structure and molecular weight. Positive tone polymer resists with various molecular weights ranging from 60 k to 500 k are synthesized and the molecular weight dependence on exposure characteristics is examined by fabricating line-and-space patterns. The molecular weight dependence of sensitivity for amyl acetate developer is small in the molecular weight range in this study. In a low molecular weight resist, the cross-section profile of the resist pattern becomes rounder and then the disconnections are observed in the 20-nm line-and-space pattern. Although the pattern width change by changing the exposure dose for each resist is quite similar, the exposure dose margin of pattern formation becomes wider with the higher molecular weight. The line width roughness is smaller in a high molecular weight resist than in a low molecular weight resist. The shift amount of the pattern width from the design value for various line-and-space patterns and the dry etching resistance to CF₄ plasma are also presented.

6-inch size (known as 6025QZ) binary Cr mask is widely used in the semiconductor lithography for over 20years. Recently for the 450mm wafer process, high grade 9-inch size mask is expected. For this application, we have studied and developed new grade 9-inch size mask blanks for recent 450mm wafer process requirement. There are three types of glass substrates material use and select as 9inch size mask blanks and for required applications by the users. Each glass material has advantage and disadvantage for lithography process as well as wafer process. By knowing the each glass substrate material characteristics and quality level the users enable to select the proper 9inch mask blanks for their targeting applications. At present, ULCOAT has produced 9-inch size mask blanks by the most advanced chrome sputtering equipment use for 6025QZ.

Opaque Mosi on Glass (OMOG) photomask, significantly less prone to mask degradation, has been applied in leading-edge photolithographic flows on 20 nm and 14 nm node. Mask defect problem occurs at any time, rooted in various causes; therefore, defect printability disposition and verification need to be evaluated for new developing process. A series of programmed defects with typical sizes and shapes have been established for different mask patterns on OMOG masks and investigated for the defect printability influences through the CDSEM, AIMS and inspection tools. The results are compiled to produce the defect specifications that can be implemented on OMOG mask fabrication.

The abnormal growing defect (we called this defect 'scum haze defect') in the photomask which is generated during the wafer lithography process is very important issue on semiconductor industry. Because wafer yield loss could be caused by the mask CD variation and the transmittance loss due to the growing defects on the photomask, many studies have been done about the mechanism and the solution of the general type growing defects such as haze and Cr migration so far, However we still need to clarify some abnormal types of the growing defects such as scum haze defect. In this paper, we investigated the generation mechanism and prevention techniques of the scum haze defect on the attenuated phase shift mask. This defect composed of CrOx is caused by the increase of the accumulated exposure energy on photomask. This phenomenon is remarkably similar to the Cr migration on binary mask. But, the apparent difference is that this scum type defect is observed on the attenuated phase shift mask which mainly consists of MoSiON film, and it is difficult to control this defect because of its irregular generation characteristic. Additionally, this defect is not generally removed through the conventional wet cleaning process but it only could be removed by a kind of plasma treatment. In this study, the difference of generation mechanism between the scum haze defect and the general haze was discussed, and the optimal process for controlling scum haze defect in the mask manufacturing was described.

Mask repair is an essential step in the mask manufacturing process as the extension of 193nm technology and the insertion of EUV are drivers for mask complexity and cost. The ability to repair all types of defects on all mask blank materials is crucial for the economic success of a mask shop operation. In the future mask repair is facing several challenges. The mask minimum features sizes are shrinking and require a higher resolution repair tool. At the same time mask blanks with different new mask materials are introduced to optimize optical performance and long term durability. For EUV masks new classes of defects like multilayer and phase defects are entering the stage. In order to achieve a high yield, mask repair has to cover etch and deposition capabilities and must not damage the mask. We will demonstrate in this paper that low energetic electron-beam (e-beam)-based mask repair is a commercially viable solution. Therefore we developed a new repair platform called MeRiT^® neXT to address the technical challenges of this new technology. We will analyze the limits of the existing as well as lower energetic electron induced repair technologies theoretically and experimentally and show performance data on photomask reticles. Based on this data, we will give an outlook to future mask repair technology.

Die-to-die reticle inspections are among the simplest and most sensitive reticle inspections because of the use of an identical-design neighboring-die for the reference image. However, this inspection mode can have two key disadvantages: (1) The location of the defect is indeterminate because it is unclear to the inspector whether the test or reference image is defective; and (2) nuisance and false defects from mask manufacturing noise and tool optical variation can limit the usable sensitivity. The use of a new sequencing approach for a die-to-die inspection can resolve these issues without any additional scan time, without sacrifice in sensitivity requirement, and with a manageable increase in computation load.

In this paper we explore another approach for die-to-die inspections using a new method of defect processing and sequencing. Utilizing die-to-die double arbitration during defect detection has been proven through extensive testing to generate accurate placement of the defect in the correct die to ensure efficient defect disposition at the AIMS step. The use of this method maintained the required inspection sensitivity for mask quality as verified with programmed-defectmask qualification and then further validated with production masks comparing the current inspection approach to the new method. Furthermore, this approach can significantly reduce the total number of defects that need to be reviewed by essentially eliminating the nuisance and false defects that can result from a die-to-die inspection. This "double-win" will significantly reduce the effort in classifying a die-to-die inspection result and will lead to improved cycle times.

According to the ITRS roadmap, semiconductor industry drives the 193nm lithography to its limits, using techniques like Double Pattern Technology (DPT), Source Mask Optimization (SMO) and Inverse Lithography Technology (ILT). In terms of considering the photomask metrology, full in-die measurement capability is required for registration and overlay control with challenging specifications for repeatability and accuracy.

Double patterning using 193nm immersion lithography has been adapted as the solution to enable 14nm technology nodes. The overlay control is one of the key figures for the successful realization of this technology. In addition to the various error contributions from the wafer scanner, the reticles play an important role in terms of considering lithographic process contributed errors. Accurate pattern placement of the features on reticles with a registration error below 4nm is mandatory to keep overall photomask contributions to overlay of sub 20nm logic within the allowed error budget.

In this paper, we show in-die registration errors using 14nm DPT product masks, by measuring in-die overlay patterns comparing with regular registration patterns. The mask measurements are used to obtain an accurate model to predict mask contribution on wafer overlay of double patterning technology.

As DRAM semiconductor manufacturing approaches high volume for 1x nm nodes with immersion lithography, an increased emphasis is being placed on reducing the influence of the systematic wafer-level contribution to the on-product overlay budget. The cost of the needed metrology has hitherto been challenging. However, it will be shown that the availability of fast, accurate diffraction based metrology integrated within the Lithography cluster can enable cost-effective solutions. Together with applications software we will use any relevant context information to optimize control of all exposure-tool actuators during lot processing, to deliver the needed on-product performance.

Current process corrections typically are done based on feedback per lot and per exposure chuck. Wafers exposed on the same chuck, belonging to the same lot get exactly the same process corrections. In current HVM processing however, an important contribution to the wafer variation is the differences in processing of the individual wafers. These differences can be related to variations in the usage of the processing tools (e.g. different etch chambers). An extension of the process corrections from chuck-based to process-context based can help in reducing the systematic wafer-level variation. With Integrated Metrology the sampling of wafers through the lot can be adjusted to make sure all different processing-contexts are covered in the measurements.

Finally, the impact on Litho process cycle time of the total metrology effort required to enable these performance improvements, will be evaluated, and a proposal will be made on the optimum strategy to enable high-volume manufacturing.

As the design rule of the semiconductor shrinks, the CD MTT (Critical Dimension Mean-to-Target) specification for photomask becomes tighter. So, more precise control of CD MTT is required. We have investigated the CD MTT control and applied it to the attenuated PSM (Phase Shift Mask) successfully for several years. We can control the CD MTT of MoSi pattern by measuring Cr/MoSi pattern to estimate MoSi pattern CD and additional etch to shrink MoSi pattern as reported in previous study. At first, the MoSi pattern CD can be estimated with the Cr/MoSi pattern CD because the CD gap between MoSi pattern and Cr/MoSi pattern is relatively constant. Additional MoSi etch is performed to shrink the MoSi pattern CD after then. The CD gap alwasys exists and the variation of the CD gap is enough small to be not considered in conventional photomask production until now. However, the variation of the CD gap is not ignorable in case of sub-20 nm tech.

In this study, we investigated new method to measure MoSi pattern CD before Cr strip process to eliminate the CD gap between MoSi pattern and Cr/MoSi pattern. To eliminate the CD gap, we attempt three solutions – 1) Optimize etch process to perform perfect Cr/MoSi pattern profile without the CD gap, 2) Improve CD measurement accuracy by developing new SEM measuring mechanism, 3) Develop of new process to modify Cr/MoSi pattern profile to be measured without the CD gap. It was found that the CD gap can be eliminated and MoSi pattern CD can be measured perfectly. Finally, MoSi pattern CD control was improved because of CD gap elimination.

We can control the pattern on wafer without optimization of layout design if we understand reticle cd behavior

Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria.

In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

Even small defects on the main patterns can create killer defects on the wafer, whereas the same defect on or near the decorative patterns may be completely benign to the wafer functionality. This ambiguity often causes operators and engineers to put a mask "on hold" to be analyzed by an AIMS™ tool which slows the manufacturing time and increases mask cost. In order to streamline the process, mask shops need a reliable way to quickly identify the wafer impact of defects during mask inspection review reducing the number of defects requiring AIMS™ analysis.

Source Mask Optimization (SMO) techniques are now common on sub 20nm node critical reticle patterns These techniques create complex reticle patterns which often makes it difficult for inspection tool operators to identify the desired wafer pattern from the surrounding nonprinting patterns in advanced masks such as SMO, Inverse Lithography Technology (ILT), Negative Tone Development (NTD).

In this study, we have tested a system that generates aerial simulation images directly from the inspection tool images. The resulting defect dispositions from a program defect test mask along with numerous production mask defects have been compared to the dispositions attained from AIMS™ analysis. The results of our comparisons are presented, as well as the impact to mask shop productivity.

The 1Xnm technology node lithography is using SMO-ILT, NTD or more complex pattern. Therefore in mask defect inspection, defect verification becomes more difficult because many nuisance defects are detected in aggressive mask feature. One key Technology of mask manufacture is defect verification to use aerial image simulator or other printability simulation. AIMS™ Technology is excellent correlation for the wafer and standards tool for defect verification however it is difficult for verification over hundred numbers or more.

We reported capability of defect verification based on lithography simulation with a SEM system that architecture and software is excellent correlation for simple line and space.[1]

In this paper, we use a SEM system for the next generation combined with a lithography simulation tool for SMO-ILT, NTD and other complex pattern lithography. Furthermore we will use three dimension (3D) lithography simulation based on Multi Vision Metrology SEM system. Finally, we will confirm the performance of the 2D and 3D lithography simulation based on SEM system for a photomask verification.

Defect verification has become significantly difficult to higher technology nodes over the years. Traditional primary method of defect (include repair point) control consists of inspection, AIMS and repair steps. Among them, AIMS process needs various wafer lithography conditions, such as NA, inner/outer sigma, illumination shape and etc. It has a limit to analyze for every layer accurately because AIMS tool uses the physical aperture system. And it requires meticulous management of exposure condition and CD target value which change frequently in advanced mask.

We report on the influence of several AIMS parameters on the defect analysis including repair point. Under various illumination conditions with different patterns, it showed the significant correlation in defect analysis results. It is able to analyze defect under certain error budget based on the management specification required for each layer. In addition, it provided us with one of the clues in the analysis of wafer repeating defect. Finally we will present 'optimal specification' for defect management with common AIMS recipe and suggest advanced mask process flow.

Mask pattern measurement becomes one of the main challenges for the quality evaluation of the mask which is applied with complex lithography optical effect correction. Traditional straight edge mask pattern is evaluated with 1-dimension Critical Dimension (CD) method. But for 2-dimension pattern especially the mask full filled with complex shapes OPC pattern, many special approaches are studied attempt to characterize 2D pattern from different points of view ^[1-5]. A simple CD’s information and the traditional mask performance evaluation parameters, such as CD mean-to-target and CD uniformity, are no longer suitable to such 2D pattern due to lacking of the pattern’s character descriptions. Therefore the CD performances may not represent the actual wafer printing result in many cases. In addition, non-straight pattern edge induces significant CD measure error which makes it difficult to clarify the real mask pattern making quality.

This paper investigates a pattern contour based solution for 2D structure performance evaluation. The basic contours of GDS and CD-SEM image are extracted, overlapped and processed and then the edge roughness of SEM contour and the bias between the above two kinds of contour are adopted on 2D individual pattern performance’s statistics. By utilizing this solution, the 2D pattern quality can be described quantitatively as two main aspects, shape and size with the results of edge roughness and bias. Generalize this solution, the 2D pattern’s uniformity, mean size, or other performances, can be evaluated quantitatively in the similar way as well. This solution calculation bases on pattern contour, therefore the measure pattern is not restricted by its shape.

The blank mask defect review process involves detailed analysis of defects observed across a substrate’s multiple preparation stages, such as cleaning and resist-coating. The detailed knowledge of these defects plays an important role in the eventual yield obtained by using the blank. Defect knowledge predominantly comprises of details such as the number of defects observed, and their accurate sizes. Mask usability assessment at the start of the preparation process, is crudely based on number of defects. Similarly, defect size gives an idea of eventual wafer defect printability. Furthermore, monitoring defect characteristics, specifically size and shape, aids in obtaining process related information such as cleaning or coating process efficiencies.

Blank mask defect review process is largely manual in nature. However, the large number of defects, observed for latest technology nodes with reducing half-pitch sizes; and the associated amount of information, together make the process increasingly inefficient in terms of review time, accuracy and consistency. The usage of additional tools such as CDSEM may be required to further aid the review process resulting in increasing costs.

Calibre® MDPAutoClassify™ provides an automated software alternative, in the form of a powerful analysis tool for fast, accurate, consistent and automatic classification of blank defects. Elaborate post-processing algorithms are applied on defect images generated by inspection machines, to extract and report significant defect information such as defect size, affecting defect printability and mask usability. The algorithm’s capabilities are challenged by the variety and complexity of defects encountered, in terms of defect nature, size, shape and composition; and the optical phenomena occurring around the defect [1].

This paper mainly focuses on the results from the evaluation of Calibre® MDPAutoClassify™ product. The main objective of this evaluation is to assess the capability of accurately estimating the size of the defect from the inspection images automatically. The sensitivity to weak defect signals, filtering out noise to identify the defect signals and locating the defect in the images are key success factors. The performance of the tool is assessed on programmable defect masks and production masks from HVM production flow. Implementation of Calibre® MDPAutoClassify™ is projected to improve the accuracy of defect size as compared to what is reported by inspection machine, which is very critical for production, and the classification of defects will aid in arriving at appropriate dispositions like SEM review, repair and scrap.

As one of the most promising next generation lithography technologies, multiple patterning lithography (MPL) plays an important role in the attempts to keep in pace with 10 nm technology node and beyond. With feature size keeps shrinking, it has become impossible to print dense layouts within one single exposure. As a result, MPL such as double patterning lithography (DPL) and triple patterning lithography (TPL) has been widely adopted. There is a large volume of literature on DPL/TPL layout decomposition, and the current approach is to formulate the problem as a classical graph-coloring problem: Layout features (polygons) are represented by vertices in a graph G and there is an edge between two vertices if and only if the distance between the two corresponding features are less than a minimum distance threshold value d_min. The problem is to color the vertices of G using k colors (k = 2 for DPL, k = 3 for TPL) such that no two vertices connected by an edge are given the same color. This is a rule-based approach, which impose a geometric distance as a minimum constraint to simply decompose polygons within the distance into different masks. It is not desired in practice because this criteria cannot completely capture the behavior of the optics. For example, it lacks of sufficient information such as the optical source characteristics and the effects between the polygons outside the minimum distance. To remedy the deficiency, a model-based layout decomposition approach to make the decomposition criteria base on simulation results was first introduced at SPIE 2013.¹ However, the algorithm¹ is based on simplified assumption on the optical simulation model and therefore its usage on real layouts is limited. Recently AMSL² also proposed a model-based approach to layout decomposition by iteratively simulating the layout, which requires excessive computational resource and may lead to sub-optimal solutions. The approach² also potentially generates too many stiches. In this paper, we propose a model-based MPL layout decomposition method using a pre-simulated library of frequent layout patterns. Instead of using the graph G in the standard graph-coloring formulation, we build an expanded graph H where each vertex represents a group of adjacent features together with a coloring solution. By utilizing the library and running sophisticated graph algorithms on H, our approach can obtain optimal decomposition results efficiently. Our model-based solution can achieve a practical mask design which significantly improves the lithography quality on the wafer compared to the rule based decomposition.