As the semiconductor process further scales down, the industry encounters many lithography-related issues. In the 14nm logic node and beyond, triple patterning lithography (TPL) is one of the most promising techniques for Metal1 layer and possibly Via0 layer. As one of the most challenging problems in TPL, recently layout decomposition efforts have received more attention from both industry and academia. Ideally the decomposer should point out locations in the layout that are not triple patterning decomposable and therefore manual intervention by designers is required. A traditional decomposition flow would be an iterative process, where each iteration consists of an automatic layout decomposition step and manual layout modification task. However, due to the NP-hardness of triple patterning layout decomposition, automatic full chip level layout decomposition requires long computational time and therefore design closure issues continue to linger around in the traditional flow. Challenged by this issue, we present a novel incremental layout decomposition framework to facilitate accelerated iterative decomposition. In the first iteration, our decomposer not only points out all conflicts, but also provides the suggestions to fix them. After the layout modification, instead of solving the full chip problem from scratch, our decomposer can provide a quick solution for a selected portion of layout. We believe this framework is efficient, in terms of performance and designer friendly.

As the semiconductor critical dimension (CD) is shrunk to 20nm node and beyond, double and triple patterning technologies become necessary for current 193nm optical lithography. However, the new technologies induce a new variation factor of the two or three mask pattern mismatching in terms of the wafer CD or alignment performance on silicon. This mismatch can degrade matching circuit performance such as SRAM and analog circuit. In this paper, we address the impact on our 20nm CRAM (configuration RAM used in FPGA circuit) performance caused by diffusion layer pattern decomposition (coloring). Furthermore, we propose a methodology to optimize the coloring based on an alignment performance assessment and CD control of two mask patterns printed on silicon wafer. In the same experiment, we observed that the OPC (Optical Proximity Correction) is also critical to the coloring methodology. The silicon results show that after the optimization, the impact of coloring-induced mismatch on CRAM performance can be reduced significantly.

Full chip model based Optical Proximity Correction (OPC) at advanced nodes involves iteratively modifying the drawn polygon shapes while simulating them through complex optical and resist models. Due to the computational complexity of the models and the large size of VLSI designs, these mask simulations run for very long times. In this study we propose a pattern replacement step to generate a partial mask solution before applying model based OPC correction. Since the pattern replacement step is very fast and model based OPC has to be applied only to a portion of the design, total mask generation runtime is significantly reduced.

We treat the OPC engine with a classical dynamics perspective, and quantify its potential to converge in all dimensions. The inherent engine weakness is thus taken into account for retargeting planning. Specifically, we follow the one-dimensional helical spring model, and calculate the retarget amount as an analogy to the spring restoring force, and eventually improve the wafer target convergence. Unlike conventional measures, this methodology does not require patching or rebuilding the OPC engine, therefore minimizes the cycle time. Meanwhile, it entails little risk by causing no impact on the mask solution outside the retargeted region, thereby compartmentalizing the treatment.

Whether for VSB mask writing or for multibeam mask writing, the shapes we need to write on masks are increasingly complex, increasingly curvilinear, and smaller in minimum width and space. The overwhelming trend in mask data preparation (MDP) is the shift from deterministic, rule-based, geometric, context-independent, shape-modulated, rectangular processing to statistical, simulation-based, context-dependent, dose- and shape-modulated any-shape processing. The paper briefly surveys the history of MDP, and explains through a simulation-based study that 50nm line and space is the tipping point where rule-based processing gives away to simulation-based processing.

A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity and variability. The work described here is motivated by requirements for extreme accuracy and control of variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design of VSB shots and dose assignment.

Shrinking feature sizes and the need for tighter CD (Critical Dimension) control require the introduction of new technologies in mask making processes. One of those methods is the dose assignment of individual shots on VSB (Variable Shaped Beam) mask writers to compensate CD non-linearity effects and improve dose edge slope. Using increased dose levels only for most critical features, generally only for the smallest CDs on a mask, the change in mask write time is minimal while the increase in image quality can be significant. However, this technology requires accurate modeling of the mask effects, especially the CD/dose dependencies. This paper describes a mask model calibration flow for Mask Process Correction (MPC) applications with shot dose assignment. The first step in the calibration flow is the selection of appropriate test structures. For this work, a combination of linespace patterns as well as a series of contact patterns are used for calibration. Features sizes vary from 34 nm up to several micrometers in order to capture a wide range of CDs and pattern densities. After mask measurements are completed the results are carefully analyzed and measurements very close to the process window limitation and outliers are removed from the data set. One key finding in this study is that by including patterns exposed at various dose levels the simulated contours of the calibrated model very well match the SEM contours even if the calibration was based entirely on gauge based CD values. In the calibration example shown in this paper, only 1D line and space measurements as well as 1D contact measurements are used for calibration. However, those measurements include patterns exposed at dose levels between 75% and 150% of the nominal dose. The best model achieved in this study uses 2 e-beam kernels and 4 kernels for the simulation of development and etch effects. The model error RMS on a large range of CD down to 34 nm line CD is 0.71 nm. The calibrated model is then used to generate 2D contours for line ends, space ends and contacts and those contours are compared to SEM images. For all patterns, including those very close to the resolution limit, very good contour overlay is achieved. It appears that by including the various dose levels in the calibration a very good separation of the e-beam model components from the etch components is possible and that this also results in very accurate 2D model quality. In conclusion, very accurate mask model calibration is achieved for mask processes using shot dose assignment. Standard test patterns can be used for calibration if they include the dose variations intended for correction.

Continuously shrinking designs by further extension of 193nm technology lead to a much higher probability of hotspots especially for the manufacturing of advanced logic devices. The CD of these potential hotspots needs to be precisely controlled and measured on the mask. On top of that, the feature complexity increases due to high OPC load in the logic mask design which is an additional challenge for CD metrology. Therefore the hotspot measurements have been performed on WLCD from ZEISS, which provides the benefit of reduced complexity by measuring the CD in the aerial image and qualifying the printing relevant CD. This is especially of advantage for complex 2D feature measurements. Additionally, the data preparation for CD measurement becomes more critical due to the larger amount of CD measurements and the increasing feature diversity. For the data preparation this means to identify these hotspots and mark them automatically with the correct marker required to make the feature specific CD measurement successful. Currently available methods can address generic pattern but cannot deal with the pattern diversity of the hotspots. The paper will explore a method how to overcome those limitations and to enhance the time-to-result in the marking process dramatically. For the marking process the Synopsys WLCD Output Module was utilized, which is an interface between the CATS mask data prep software and the WLCD metrology tool. It translates the CATS marking directly into an executable WLCD measurement job including CD analysis. The paper will describe the utilized method and flow for the hotspot measurement. Additionally, the achieved results on hotspot measurements utilizing this method will be presented.

Highly regular gridded designs are generally seen as a key component for continued advances in lithographic resolution in a time of limited further progress in lithography hardware [1]. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical limit ∼ 0.25. A highly effective implementation of GDR is the lines+cuts approach discussed in [4, 5, 8] and else- where. Excellent results at very advanced nodes are achieved by this double-patterning process, where lines are created first, then cuts are patterned on top as required by circuit connectivity. The regular structure of gridded designs offers the opportunity to use an optimized approach to Optical Proximity Correction (OPC), one taking full advantage of the design style to achieve best possible ac- curacy and speed and at the same time small mask file size and good manufacturability. In this work we describe our GDR-tailored OPC tool called OPC- Lite [6]. The OPC-Lite approach is discussed and compared to conventional 2D OPC. Sub-20nm silicon data are shown, validating predictive quality of our simulation and OPC techniques.

We review the state-of-art and issues of dry etching of masks for nano-device photo lithography. After introducing the basics of photo-mask structures and their plasma etching, we discuss the specifics of mask etching as compared to the etching of silicon wafers, focusing on processes for the two most-challenging cases: phase-shift masks and NGL where it is achieved by etching the quartz exactly to the prescribed depth. State-of the art solutions for the etching of such masks must provide stringent etching uniformity and accurate end-point monitoring. This can be addressed by either reducing the lithography fields to half or even quarter of their present area, with two to four times worse productivity, or working with larger masks of 9 and later 12 inch. The pressure for such development is becoming stronger with the wider adoption of 450 mm wafers. The new masks may need to be thicker to prevent unwanted deformations. Etching uniformity will have to be sustained over much wider areas. Furthermore, RF bias control for thicker substrates is not straightforward due to the quartz impedance preventing effective RF coupling. Our etching experiments in Ar and Cl₂ showed that well established mask etching conditions can be reproduced for moderately thicker substrates, while further increase of substrate thickness may require essentially different approach, such as a series resonance of the inductive plasma bulk and the capacitive sheath.

There are significant advantages of using the ReticleSense^TM Airborne Particle Sensor (APSR) in reticle environments to locate and troubleshoot airborne particles in reticle environments as compared to traditional surface scan reticle, in-situ or hand-held methods. Time, resource and cost savings are identified.

We have developed a new focused ion beam (FIB) technology using a gas field ion source (GFIS) for mask repair. Meanwhile, since current high-end photomasks do not have high durability in exposure nor cleaning, some new photomask materials are proposed. In 2012, we reported that our GFIS system had repaired a representative new material “A6L2”. It is currently expected to extend the application range of GFIS technology for various new materials and various defect shapes. In this study, we repaired a single bridge, a triple bridge and a missing hole on a phase shift mask (PSM) of “A6L2”, and also repaired single bridges on a binary mask of molybdenum silicide (MoSi) material “W4G” and a PSM of high transmittance material “SDC1”. The etching selectivity between those new materials and quartz were over 4:1. There were no significant differences of pattern shapes on scanning electron microscopy (SEM) images between repair and non-repair regions. All the critical dimensions (CD) at repair regions were less than +/-3% of those at normal ones on an aerial image metrology system (AIMS). Those results demonstrated that GFIS technology is a reliable solution of repairing new material photomasks that are candidates for 1X nm generation.

As the number of masks per wafer product set is increasing and low k1 lithography requires tight mask specifications, the patterning process below sub 20nm tech. node for critical layers will be much more expensive compared with previous tech. generations. Besides, the improved resolution and the zero defect level are necessary to meet tighter specifications on a mask and these resulted in the increased the blank mask price as well as the mask fabrication cost. Unfortunately, in spite of expensive price of blank masks, the certain number of defects on the blank mask is transformed into the mask defects and its ratio is increased. But using high quality blank mask is not a good idea to avoid defects on the blank mask because the price of a blank mask is proportional to specifications related to defect level. Furthermore, particular defects generated from the specific process during manufacturing a blank mask are detected as a smaller defect than real size by blank inspection tools because of its physical properties. As a result, it is almost impossible to prevent defects caused by blank masks during the mask manufacturing. In this paper, blank defect types which is evolved into mask defects and its unique characteristics are observed. Also, the repair issues are reviewed such as the pattern damage according to the defect types and the repair solution is suggested to satisfy the AIMS (Arial Image Measurement System) specification using a nanomachining tool.

Reticle critical dimension uniformity (CDU) is one of the major sources of wafer CD variations which include both inter-field variations and intra-field variations. Generally, wafer critical dimension (CD) measurement sample size interfield is much less than intra-field. Intra-field CDU correction requires time-consumption of metrology. In order to improve wafer intra-field CDU, several methods can be applied such as intra-field dose correction to improve wafer intra-field CDU. Corrections can be based on CD(SEM) or aerial image metrology data from the reticle. Reticle CDU and wafer CDU maps are based on scanning electron microscope (SEM) metrology, while reticle inspection intensity mapping (NuFLare 6000) and wafer level critical dimension (WLCD) utilize aerial images or optical techniques. Reticle inspecton tools such as those from KLA and NuFlare, offer the ability to collect optical measurement data to produce an optical CDU map. WLCD of Zeiss has the advantage of using the same illumination condition as the scanner to measure the aerial images or optical CD. In this study, the intra-field wafer CDU map correlation between SEMs and aerial images are characterized. The layout of metrology structures is very important for the correlation between wafer intra-field CDU, measured by SEM, and the CDU determined by aerial images. The selection of metrology structures effects on the correlation to SEM CD to wafer is also demonstrated. Both reticle CDU, intensity CDU and WLCD are candidates for intra-field wafer CDU characterization and the advantages and limitations of each approach are discussed.

This paper reports on the experimental validation of adapting the multilayer periodicity of an EUV mask to mitigate pattern shifts at wafer level. This EUV specific pattern shift will eventually contribute to overlay budgets which continue to tighten with decreasing technology node. A good understanding of its manipulators, i.e., mask 3D effects, is paramount. By means of mask diffractometry and scanner exposures at numerical aperture of 0.33 the mask-induced pattern shift at wafer level is verified. These measurements are then correlated to rigorous simulations using a calibrated EUV mask stack model to accurately predict the imaging impact of multilayer tuning in EUV masks. A comprehensive interpretation of the mask 3D impact on pattern shift at wafer level will be presented based on simulated diffraction pupils supported by experimental verification at both mask and wafer level.

The authors are expanding the capabilities of the SHARP microscope by implementing complementary imaging modes. SHARP (the SEMATECH High-NA Actinic Reticle review Project) is an actinic, synchrotron-based microscope dedicated to extreme ultraviolet (EUV) photomask research. SHARP’s programmable Fourier Synthesis Illuminator and its use of Fresnel zoneplate lenses as imaging optics provide a versatile framework, facilitating the implementation of diverse modes beyond conventional imaging. In addition to SHARP’s set of standard zoneplates, we have created more than 100 zoneplates for complementary imaging modes, all designed to extract additional information from photomasks, improve navigation and enhance defect detection. More than 50 new zoneplates are installed in the tool; the remaining lenses are currently in production. In this paper we discuss the design and fabrication of zoneplates for complementary imaging modes and present image data, obtained using Zernike Phase Contrast and different implementations of Differential Interference Contrast.

In this paper, we present a complete study on mask blank and patterned mask inspection utilizing the Zernike phase contrast method. The Zernike phase contrast method provides in-focus inspection ability to study phase defects with enhanced defect sensitivity. However, the 90 degree phase shift in the pupil will significantly reduce the amplitude defect signal at focus. In order to detect both types of defects with a single scan, an optimized phase shift instead of 90 degree on the pupil plane is proposed to achieve an acceptable trade-off on their signal strengths. We can get a 70% of its maximum signal strength at focus for both amplitude and phase defects with a 47 degree phase shift. For SNR, the tradeoff between speckle noise and signal strength has to be considered. The SNR of phase and amplitude defects at focus can both reach 11 with 13 degree phase shift and 50% apodization. Moreover, the simulation results on patterned mask inspection of partially hidden phase defects with die-to-database inspection approach on the blank inspection tool show that the improvement of the Zernike phase method is more limited. A 40% enhancement of peak signal strength can be achieved with the Zernike phase contrast method when the defect is centered in the space, while the enhancement drops to less than 10% when it is beneath the line.

According to the road map shown in ITRS [1], the EUV mask requirement for defect inspection is to detect the defect size of sub- 20 nm in the near future. EB (Electron Beam) inspection with high resolution is one of the promising candidates to meet such severe defect inspection requirements. However, conventional EB inspection using the SEM method has the problem of low throughput. Therefore, we have developed an EB inspection tool, named Model EBEYE M※. The tool has the PEM (Projection Electron Microscope) technique and the image acquisition technique with TDI (Time Delay Integration) sensor while moving the stage continuously to achieve high throughput [2]. In our previous study, we showed the performance of the tool applied for the half pitch (hp) 2X nm node in a production phase for particle inspection on an EUV blank. In the study, the sensitivity of 20 nm with capture rate of 100 % and the throughput of 1 hour per 100 mm square were achieved, which was higher than the conventional optical inspection tool for EUV mask inspection [3]-[5]. Such particle inspection is called for not only on the EUV blank but also on the patterned EUV mask. It is required after defect repair and final cleaning for EUV mask fabrication. Moreover, it is useful as a particle monitoring tool between a certain numbers of exposures for wafer fabrication because EUV pellicle has not been ready yet. However, since the patterned EUV mask consists of 3D structure, it is more difficult than that on the EUV blank. In this paper, we evaluated that the particle inspection on the EUV blank using the tool which was applied for the patterned EUV mask. Moreover, the capability of the particle inspection on the patterned EUV mask for the hp 2X nm node, whose target is 25 nm of the sensitivity, was confirmed. As a result, the inspection and SEM review results of the patterned EUV masks revealed that the sensitivity of the hp 100 nm Line/Space (LS) was 25 nm and that of the hp 140- 160 nm Contact Hole (CH) was 21 nm. Therefore, we confirmed that particle inspection on the patterned EUV mask using Model EBEYE M could be available for the EUV mask of the hp 2X nm node. In the future, we will try to inspect the production mask of the hp 2X nm node, and try to confirm the performance for the EUV mask of the hp 1X nm node.

Overcoming the challenges associated with photomask defectivity is one of the key aspects associated with EUV mask infrastructure. In addition to establishing specific EUV mask repair approaches, the ability to identify printable mask defects that require repair as well as to verify if a repair was successful are absolutely necessary. Such verification can only be performed by studying the repaired region using actinic light at an exact emulation of the scanner illumination conditions of the mask as can be done by the AIMS^TM EUV. ZEISS, in collaboration with the SEMATECH EUVL Mask Infrastructure (EMI) consortium are currently developing the AIMS^TM EUV system and have recently achieved First Light on the prototype system, a major achievement. First light results will be presented in addition to the current development status of the system.

A negative tone imaging with application of new developer to conventional ArF immersion resist materials is proposed for narrow trench pattern formation, which is effective to the double trench process that is one of the candidates of double patterning process for semiconductor devices below 20nm node. Significantly better resolution on narrow trench pattern and small CH pattern was observed with this negative tone development compared to positive tone development. These results suggest that this negative tone development process is one of the promising candidates for double trench process.

The critical layer masks for 14 nm and 10 nm logic nodes are typically bright field, and the key features are opaque structures on the mask. In order to meet the tight critical dimension (CD) requirements on these opaque features the use of a high quality negative tone chemically amplified e-beam resist (NCAR) is required. Until very recently the only negative tone e-beam resists available for use by the mask industry were the traditional cross linking type in which ebeam exposure cross links the material and makes it insoluble in developer. In this paper we will describe the performance of a new polarity switching type of NCAR resist that works by changing the solubility of the exposed resist without cross linking. This has the advantage of significantly reduced swelling and scumming and resulted in major improvements in the resolution of heavily nested features and small clear features on the mask. Additional detailed characterization results will be described.

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the results of both AIMS optical simulation and to actual wafer prints.

Mask repair is an essential step in the mask manufacturing process as the extension of 193nm technology and the insertion of EUV are drivers for mask complexity and cost. The ability to repair all types of defects on all mask blank materials is crucial for the economic success of a mask shop operation. In the future mask repair is facing several challenges. The mask minimum features sizes are shrinking and require a higher resolution repair tool. At the same time mask blanks with different new mask materials are introduced to optimize optical performance and long term durability. For EUV masks new classes of defects like multilayer and phase defects are entering the stage. In order to achieve a high yield, mask repair has to cover etch and deposition capabilities and must not damage the mask. These challenges require sophisticated technologies to bring mask repair to the next level. For high end masks ion-beam based and e-based repair technologies are the obvious choice when it comes to the repair of small features. Both technologies have their pro and cons. The scope of this paper is to review and compare the performance of ion-beam based mask repair to e-beam based mask repair. We will analyze the limits of both technologies theoretically and experimentally and show mask repair related performance data. Based on this data, we will give an outlook to future mask repair tools.

Photomasks are key elements of photolithographic processes, implying that their degradation must be reliably monitored and strongly mitigated. Indeed, the photo-induced oxidation of Cr in Cr On Glass (COG) photomasks and the concomitant electrostatic-field migration present in high-volume production using 193-nm photolithographic scanners severely deteriorate the pattern transfer quality, therefore limiting the lifetime of these reticles. To moderate this effect, Opaque MoSi On Glass (OMOG) photomasks, significantly less prone to such degradation, are currently being massively used in leading-edge microfabrication flows. The type of mask fabrication process normally used involving ebeam writing is however not adapted for non-critical photolithographic layers that do not yet benefit from its inherent performances but still suffer from its high cost and its long processing time. It is therefore proposed in this work to combine the simplicity of laser writing and the resistance of MoSi to degradation by using laser-written binary OMOG photomasks for the non-critical layers (e.g. ion-implantation) of a 28-nm production flow. To evaluate one of this new reticle, its pattern transfer fidelity is compared to the one of a laser-written binary COG mask already qualified for production from a photolithographic quality perspective, both masks being treated using the same optical proximity correction (OPC) model. Dispersive and dissipative properties, critical dimension uniformity, pattern linearity and pattern proximity are directly measured on wafer level, subsequently revealing that both photomasks match in terms of OPC parameters. The utilized OPC model is moreover proven robust against the use of both types of masks, consequently making the conversion from COG to OMOG particularly simple. These experimental results therefore qualify the new mask fabrication type and pave the way for a major utilization in high-volume production.

This industry faces new challenges every day. It gets tougher as process nodes shrink and the data complexity and volume increase. We are a mask data preparation (MDP) software provider, and have been providing MDP systems to mask shops since 1990. As the industry has, MDP software providers also have been facing new challenges over time, and the challenges get tougher as process nodes shrink and the data complexity and volume increase. We discuss such MDP challenges and solutions in this paper from a MDP software provider’s perspective. The data volume continuously increases, and it is caused by shrinking the process node. In addition, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and inverse lithography technique (ILT) induce data complexity, and it contributes considerably to the increase in data volume. The growth of data volume and complexity brings challenges to MDP system, such as the computing speed, shot count, and mask process correction (MPC). New tools (especially mask writers) also bring new challenges. Variable-shaped E-beam (VSB) mask writers demand fracturing less slivers and lower figure counts for CD accuracy and write time requirements respectively. Now multibeam mask writers are under development and will definitely bring new challenges.

A new correction technique has been developed not only to reduce the corner rounding, but also to restrain the building up of shot counts that is able to increase the exposure time in electron beam (e-beam) lithography. It is able to prove the developed corner rounding correction technique is useful with high accuracies throughout the simulation of several different types of correction in the data preparation software, Inscale® from Aselta Nanographics, and its comparisons with exposure images. The developed one is helpful to suppress the accumulation of shot counts either. Furthermore, it shows the general limit of corner rounding correction in a conventional variable shaped beam exposure tool with current resist process. Firstly, we are demonstrating the new method for correcting the corner rounding that either can avoid the extension of exposure shot counts, called writing time. Secondly, this study reveals the current bounds of corner rounding correction, especially the lithography employing the shaped beam tool. Finally, we propose the criteria of data preparation for the corner rounding in e-beam lithography, specifically upcoming 18nm technology node and practical applications.

With more and more photonic data presence in e-beam lithography, the need for efficient and accurate data fracturing is required to meet acceptable manufacturing cycle time. Large photonic based layouts now create high shot count patterns for VSB based tools. Multiple angles, sweeping curves, and non-orthogonal data create a challenge for today’s e-beam tools that are more efficient on Manhattan style data. This paper describes techniques developed and used for creating fractured data for VSB based pattern generators. Proximity Effect Correction is also applied during the fracture process, taking into account variable shot sizes to apply for accuracy and design style. Choosing different fracture routines for pattern data on-the-fly allows for fast and efficient processing. Data interpretation is essential for processing curvilinear data as to its size, angle, and complexity. Fracturing complex angled data into "efficient" shot counts is no longer practical as shot creation now requires knowledge of the actual data content as seen in photonic based pattern data. Simulation and physical printing results prove the implementations for accuracy and write times compared to traditional VSB writing strategies on photonic data. Geometry tolerance is used as part of the fracturing algorithm for controlling edge placement accuracy and tuning to different e-beam processing parameters.

Mask writers’ architectures have evolved through the years in response to ever tightening requirements for better resolution, tighter feature placement, improved CD control, and tolerable write time. The unprecedented extension of optical lithography and the myriad of Resolution Enhancement Techniques have tasked current mask writers with ever increasing shot count and higher dose, and therefore, increasing write time. Once again, we see the need for a transition to a new type of mask writer based on massively parallel architecture. These platforms offer a step function improvement in both dose and the ability to process massive amounts of data. The higher dose and almost unlimited appetite for edge corrections open new windows of opportunity to further push the envelope. These architectures are also naturally capable of producing curvilinear shapes, making the need to approximate a curve with multiple Manhattan shapes unnecessary.

In the half pitch (hp) 16nm generation, the shot count on a mask is expected to become bipolar. The multi-patterning technology in lithography seems to maintain the shot count around 300G shots instead of increase in the number of masks needed for one layer. However, as a result of mask multiplication, the better positional accuracy would be required especially in Mask-to-Mask overlay. On the other hand, in complex OPC, the shot count on a mask is expected to exceed 1T shots. In addition, regardless of the shot count forecast, the resist sensitivity needs to be lower to reduce the shot noise effect so as to get better LER. In other words, slow resist would appear on main stream, in near future. Hence, such trend would result in longer write time than that of the previous generations. At the same time, most mask makers request masks to be written within 24 hours. Thus, a faster mask writer with better writing accuracy than those of previous generations is needed. With this background, a new electron beam mask writing system, EBM- 9000, has been developed to satisfy such requirements of the hp 16nm generation. The development of EBM-9000 has focused on improving throughput for larger shot counts and improving the writing accuracy.

Recently, Multi-Beam Mask Writer (MBMW) scheme is newly considered for next generation writing scheme. As the MBMW writing uses many multi-array bundle beams with small spot size, the fast writing and complex pattering is possible conceptually. The target dose level of MBMW is high around 100μC/cm² and the target of total writing time is within 10 hours for next generation layout with complex and small node pattern. The risks of high dose writing are rising of blank temperature, chemical reaction with photo-resist and charging effects in blank. In addition, the fast writing can cause the rising of temperature in blank. The heating effect can be divided into local and global terms, and each effect of critical dimension (CD) and registration was analyzed by heating effect. In case of MBMW, the global heating is more critical than local heating. Therefore, we need to study about the global heating effect which can affect global registration in MBMW. In this paper, we study about the global heat distribution on mask blank in certain MBMW writing condition, and the directional deformation of blank which can affect global registration was analyzed by using Finite Element Method (FEM). We approach with two kinds of modified heat model and the FEM model was verified with analytical calculation. The temperature variation and deformation distribution were achieved with transient method with the writing conditions, in case of 100μC/cm² of total dose, 50kV of acceleration voltage, 100% of chip density and 10 hour of total writing time. Therefore, we can consider the writing conditions according to mask specification in MBMW scheme.

We quantitatively evaluate Nuflare’s latest resist charging effect correction (CEC) model for advanced photomask production using e-beam lithography. Functionality of this CEC model includes the simulation of static and timedependent charging effects together with an improved calibration method. CEC model calibration is performed by polynomial fitting of image placement distortions induced by various beam scattering effects on a special test design with writing density variations. CEC model parameters can be fine tuned for different photomask blank materials facilitating resist charging compensation maps for different product layers. Application of this CEC model into production yields a significant reduction in photomask image placement (IP), as well as improving photomask overlay between critical neighbouring layers. The correlations between IP improvement facilitated by this CEC model and single mask parameters are presented and discussed. The layer design specifics, resist and blank materials, coupled with their required exposure parameters are observed to be the major influences on CEC model performance.

The black border is a frame created by removing all the multilayers on the EUV mask in the region around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a wafer. Papers have documented its effectiveness. As the technology transitions into manufacturing, the black border must be optimized from the initial mask making process through its life. In this work, the black border is evaluated in three stages: the black border during fabrication, the final sidewall profile, and extended lifetime studies. This work evaluates the black border through simulations and physical experiments. The simulations address concerns for defects and sidewall profiles. The physical experiments test the current black border process. Three masks are used: one mask to test how black border affects the image placement of features on mask and two masks to test how the multilayers change through extended cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images and simulated wafer effects. By evaluating the black border from both a mask making perspective and a lifetime perspective, we are able to characterize how the structure evolves. The mask data and simulations together predict the performance of the black border and its ability to maintain critical dimensions on wafer. In this paper we explore what mask changes occur and how they will affect mask use.

One of the main concerns about EUV lithography is whether or not it can be extended to very high numerical aperture. In this paper, we show by rigorous electromagnetic simulation that there is a very interesting and hitherto undiscovered electromagnetic phenomenon occurring in the 4-nm feature size regime. This new phenomenon can be exploited to enable the printing of 4-nm lines and spaces with excellent aerial-image contrast and peak intensity. Also, we show how it is possible to print a logic circuit containing a general 2D pattern with 4-nm feature size, using suitable absorber and multilayer tuning, reduction ratio, exposure technique and optical proximity correction.

Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA (Numerical Aperture) optics for less than hp10nm node is accelerated. Increasing magnification of projection optics or mask size using conventional mask structure has been studied, but these methods make lithography cost high because of low through put and preparing new large mask infrastructures. To avoid these issues, etched multilayer EUV mask has been proposed. As a result of improvement of binary etched multilayer mask process, hp40nm line and space pattern on mask (hp10nm on wafer using 4x optics) has been demonstrated. However, mask patterns are easily collapsed by wet cleaning process due to their low durability caused by high aspect ratio. We propose reducing the number of multilayer pairs from 40 to 20 in order to increase durability against multilayer pattern collapse. With 20pair multilayer blank, durable minimum feature size of isolated line is extended from 80nm to 56nm. CD uniformity and linearity of 20pair etched multilayer pattern are catching up EUV mask requirement of 2014.

Mask defectivity is a serious problem for all lithographic masks, but especially for EUV masks. Defects in the EUV blank are particularly challenging because their elimination is beyond control of the mask fab. If defects have been identified on a mask blank, patterns can be shifted to place as many blank defects as possible in regions where printing impact will be eliminated or become unimportant. For those defects that cannot be mitigated through pattern shift, repair strategies must be developed. Repairing defects that occur naturally in the EUV blank is challenging because the printability of these defects varies widely. This paper describes some types of native defects commonly found and begins to outline a triage strategy for defects that are identified on the blank. Sample defects best suited to nanomachining repair are treated in detail: repairs are attempted, characterized using mask metrology and then tested for printability. Based on the initial results, the viability of repairing EUV blank native defects is discussed.

We report on our investigation of dry cleaning of reticles with a microwave induced hydrogen plasma on dummy reticles. The dummy reticles were manufactured with 70 nm ALD grown TaN on a Ru surface and test structures were patterned with lines and spaces ranging between 250 and 400 nm. After processing the test structures were contaminated with e–beam grown carbon and exposed in our plasma facility to remove the carbon with the aid of a hydrogen plasma. Analysis of the samples was performed with SEM/EDX and with SIMS-SPM to verify the complete removal of carbon from the bottom of the trench. Analysis showed that there are small traces of carbon still present on the samples. This can be contributed to contamination which has occurred during transport and storage or that the grown carbon has some edges which are higher due to localized high intensity in the focus of the e-beam.

The extreme ultraviolet (EUV) exposure technology has drawn a high degree of attention as an exposure technique for a 16 nm half-pitch generation and beyond. EUV masks, unlike conventional transmissive masks, are categorized as a reflective type mask. The structure of an EUV mask is shown in Error! Reference source not found.. An EUV mask is classified into an absorption layer, a reflective layer, a multilayer, a low thermal expansion material (LTEM), and a chucking layer. Here, the cleaning process normally consists of organic contaminant cleaning through surface oxidation as well as physical cleaning. But there are two major problems when cleaning EUV masks. First, because ruthenium (Ru), typically used to produce the reflective layer, is easily oxidized, it is difficult to conduct organic contaminant cleaning. The other problem is that the reflectance could change as a result of diffusion of the multilayer, if the mask is processed at high temperature. These two problems are especially critical when a cleaning procedure needs to be repeated in the production stage of EUV masks. In this report, we will discuss a method to clean the surface of EUV masks without oxidizing Ru in the management stage of EUV masks.

The importance of partitioning scatterometry data from EUV multilayer mask blanks into amplitude and phase roughness on meeting LWR specifications is examined using thin mask simulations. Scatterometry measurements are unable to determine whether the scattering is due to phase or reflectivity variations. We show that if a fraction of the scattering is due to amplitude roughness there can be a significant impact on the total amount of scatter permitted to meet the LWR specification.

The inspection sensitivity of a patterned extreme ultraviolet (EUV) mask with B₄C capped multilayer (ML) was investigated using a simulated projection electron microscope (PEM) image. Extrusion and intrusion defects with 16 nm in size were detected with their intensity of > 10 times the standard deviation of the background level on a half-pitch (hp) 64 nm line and space pattern. The defect detection sensitivity in this case was higher than that of Ru capped ML sample, and has a potential to meet the requirement for beyond 16 nm node generation from the standpoint of patterned mask inspection using the PEM technique. These results indicate that B₄C capping layer besides its good durability has an advantage for high sensitivity of patterned mask inspection. The optimal condition of the incident beam energy was found to be 500 and 1000 eV for the samples of B₄C capped ML and B₄C buffered Ru capped ML, respectively. The sensitivity of defect detection was strongly affected by the difference of secondary electron emission coefficients (SEECs) between the absorber layer and capping layer. However, severely scattered electrons near the pattern edge become a source of noise and then they block the effect of large SEEC difference. Thus, the small incident beam energy was found to be preferable when the SEEC difference was relatively high.

The recent status of a newly developed PEM pattern inspection system for hp 16 nm node defect detection is presented. A die-to-die defect detection sensitivity of the developing system is also investigated. A programmed defect mask was used for demonstrating the performance of the system. Defect images were obtained as difference images by comparing the PEM images “withdefects” to the PEM images “without-defects”. This image-processing system was also developed for die-to-die inspection. Captured images of extrusion and intrusion defects in hp 64 nm L/S pattern were used for detection. 12 nm sized intrusion defect, that was smaller than our target size for hp 16 nm defect detection requirement, was identified without false defects. To improve the performance of hp 16 nm patterned mask inspection for hp 11 nm EUVL patterned mask inspection, defect detection signal characteristics, which depend on hp 64 nm pattern image intensity deviation on EUVL mask, was studied.

Non-imaging techniques like X-ray scattering are supposed to play an important role in the further development of CD metrology for the semiconductor industry. Grazing Incidence Small Angle X-ray Scattering (GISAXS) provides directly assessable information on structure roughness and long-range periodic perturbations. The disadvantage of the method is the large footprint of the X-ray beam on the sample due to the extremely shallow angle of incidence. This can be overcome by using wavelengths in the extreme ultraviolet (EUV) spectral range, EUV small angle scattering (EUVSAS), which allows for much steeper angles of incidence but preserves the range of momentum transfer that can be observed. Generally, the potentially higher momentum transfer at shorter wavelengths is counterbalanced by decreasing diffraction efficiency. This results in a practical limit of about 10 nm pitch for which it is possible to observe at least the ± 1^st diffraction orders with reasonable efficiency. At the Physikalisch-Technische Bundesanstalt (PTB), the available photon energy range extends from 50 eV up to 10 keV at two adjacent beamlines. PTB commissioned a new versatile Ellipso-Scatterometer which is capable of measuring 6" square substrates in a clean, hydrocarbon-free environment with full flexibility regarding the direction of the incident light polarization. The reconstruction of line profiles using a geometrical model with six free parameters, based on a finite element method (FEM) Maxwell solver and a particle swarm based least-squares optimization yielded consistent results for EUV-SAS and GISAXS. In this contribution we present scatterometry data for line gratings and consistent reconstruction results of the line geometry for EUV-SAS and GISAXS.

As the device design rule shrinks, photomask manufacturers need to have advanced defect controllability during the ARC (Anti-Reflection Coating) and ABS (Absorber) etch in an EUV (extreme ultraviolet) mask. Therefore we studied etching techniques of EUV absorber film to find out the evasion method of particle generation. Usually, Particles are generated by plasma ignition step in etching process. When we use the standard etching process, ARC and ABS films are etched step by step. To reduce the particle generation, the number of ignition steps need to decrease. In this paper, we present the experimental results of in-situ EUV dry etching process technique for ARC and ABS, which reduces the defect level significantly. Analysis tools used for this study are as follows; TEM (for cross-sectional inspection) , SEM (for in-line monitoring ) and OES (for checking optical emission spectrum)

The introduction of ever higher source powers in EUV systems causes increased risks for contamination and degradation of EUV masks and pellicles. Appropriate testing can help to inventory and mitigate these risks. To this end, we propose EBL2: a laboratory EUV exposure system capable of operating at high EUV powers and intensities, and capable of exposing and analyzing EUV masks. The proposed system architecture is similar to the EBL system which has been operated jointly by TNO and Carl Zeiss SMT since 2005. EBL2 contains an EUV Beam Line, in which samples can be exposed to EUV irradiation in a controlled environment. Attached to this Beam Line is an XPS system, which can be reached from the Beam Line via an in-vacuum transfer system. This enables surface analysis of exposed masks without breaking vacuum. Automated handling with dual pods is foreseen so that exposed EUV masks will still be usable in EUV lithography tools to assess the imaging impact of the exposure. Compared to the existing system, large improvements in EUV power, intensity, reliability, and flexibility are proposed. Also, in-situ measurements by e.g. ellipsometry is foreseen for real time monitoring of the sample condition. The system shall be equipped with additional ports for EUVR or other analysis tools. This unique facility will be open for external customers and other research groups.

Implementations of the Semiconductor Equipment Communications Standard (SECS) are uneven across mask shop tool sets, which often implement only tool control functionality and ignore data collection. Furthermore, data collection, if implemented at all, typically exposes only a fraction of the information available within log files created by the tool. This leaves a veritable wealth of information languishing unused in tool log files – data that could provide key insights toward improvements in tool performance, processes and utilization. This paper discusses a reusable, lightweight framework for mining data from mask shop tool log files. It details the categories of data that can be mined using this framework, as well as different actions that can be triggered based on the data. The paper also proposes a generic log file format that mask shop tool vendors can implement on any tool to facilitate tool troubleshooting and simplify automated data collection.

Influence of the size or volume of the phase defect embedded in the Extreme Ultraviolet (EUV) mask on wafer printability by scanning probe microscope (SPM) is well studied. However, only few experimental results on the measurement accuracy of the phase defect size have been reported. Therefore, in this study, measurement repeatability of the phase defect volume using SPM, and influence of the defect volume distribution on defect detection signal intensity using an at-wavelength dark-field defect inspection tool were examined. A programmed phase defect mask was prepared, and defect size measurement repeatability test was conducted using a SPM. After capturing the defect images, the defect volumes were then calculated. As a result, variation of measured volume due to the measurement repeatability was much smaller than that of the defect-to-defect variation. This result indicates that measuring of the volume of each phase defect is necessary in order to evaluate the defect detection yield using phase defect inspection tool and wafer printability. In addition, the phase defects were captured their images using an at-wavelength dark-field inspection tool and from which the defect detection signal intensities were calculated. Even though the defect signal intensity itself seemed to have variation, the defect volume can be roughly estimated from the defect signal intensity.

Requalifying semiconductor photomasks remains critically important and is increasingly challenging for 20nm and 14nm node logic reticles. Patterns are becoming more complex on the photomask, and defect sensitivity requirements are more stringent than ever before. Reticle inspection tools are equally important for effective process development and the successful ramp and sustained yield for high volume manufacturing. The inspection stages considered were: incoming inspection to match with Mask Shop Outgoing result and to detect defects generated during transport; requalification by routine cycle inspection to detect Haze and any other defects; and inspection by in-house or Mask shop at the post cleaning. There are many critical capability and capacity factors for the decision for best inspection tool and strategy for high volume manufacturing, especially objective Lens NA, wavelength, power, pixel size, throughput, full-automation inspection linked with Overhead Transport, algorithm application, engineering application function, and inspection of PSM and OMOG . These tools are expensive but deliver differentiated value in terms of performance and throughput as well as extendibility. Performing a thorough evaluation and making a technically sound choice which explores these many factors is critical for success of a fab. This paper examines the methodology for evaluating two different photomask inspection tools. The focus is on ensuring production worthiness on real and advanced product photomasks requiring accurate evaluation of sensitivity, throughput, data analysis function and engineering work function on those product photomasks. Photomasks used for data collection are production reticles, PDM(Program defect Mask), SiN spray defect Reticle which is described that evaluates how the tools would perform on a contaminated plate.

Mask preparation stages are crucial in mask manufacturing, since this mask is to later act as a template for considerable number of dies on wafer. Defects on the initial blank substrate, and subsequent cleaned and coated substrates, can have a profound impact on the usability of the finished mask. This emphasizes the need for early and accurate identification of blank substrate defects and the risk they pose to the patterned reticle. While Automatic Defect Classification (ADC) is a well-developed technology for inspection and analysis of defects on patterned wafers and masks in the semiconductors industry, ADC for mask blanks is still in the early stages of adoption and development. Calibre ADC is a powerful analysis tool for fast, accurate, consistent and automatic classification of defects on mask blanks. Accurate, automated classification of mask blanks leads to better usability of blanks by enabling defect avoidance technologies during mask writing. Detailed information on blank defects can help to select appropriate job-decks to be written on the mask by defect avoidance tools [1][4][5]. Smart algorithms separate critical defects from the potentially large number of non-critical defects or false defects detected at various stages during mask blank preparation. Mechanisms used by Calibre ADC to identify and characterize defects include defect location and size, signal polarity (dark, bright) in both transmitted and reflected review images, distinguishing defect signals from background noise in defect images. The Calibre ADC engine then uses a decision tree to translate this information into a defect classification code. Using this automated process improves classification accuracy, repeatability and speed, while avoiding the subjectivity of human judgment compared to the alternative of manual defect classification by trained personnel [2]. This paper focuses on the results from the evaluation of Automatic Defect Classification (ADC) product at MP Mask Technology Center (MPMask). The Calibre ADC tool was qualified on production mask blanks against the manual classification. The classification accuracy of ADC is greater than 95% for critical defects with an overall accuracy of 90%. The sensitivity to weak defect signals and locating the defect in the images is a challenge we are resolving. The performance of the tool has been demonstrated on multiple mask types and is ready for deployment in full volume mask manufacturing production flow. Implementation of Calibre ADC is estimated to reduce the misclassification of critical defects by 60-80%.

EUV lithography has been delayed due to well-known issues such as source power, debris, pellicle, etc. for high volume manufacturing. For this reason, conventional optical lithography has been developed to cover more generations with various kinds of Resolution Enhancement Techniques (RETs) and new process technology like Multiple Patterning Technology (MPT). Presently, industry lithographers have been adopting two similar techniques of the computational OPC scheme such as Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) [1]. Sub-20 nm node masks including these technologies are very difficult to fabricate due to many small features which are near the limits of mask patterning process. Therefore, these masks require the unseen level of difficulty for inspection. In other words, from the viewpoint of mask inspection, it is very challenging to maintain maximum sensitivities on main features and minimum detection rates on the Sub-Resolution Assist Features (SRAFs). This paper describes the proper technique as the alternative solution to overcome these critical issues with Aerial Imaging (AI) inspection and High Resolution (HR) imaging inspection.

Recently, the development of semiconductor process for 14nm node and beyond is in progress. The mask-making process demands higher resolution and CD accuracy to meet requirements. Current conventional ArF PSM has several problems such as higher 3D effect and higher loading effect due to the thicker film. These problems cause the CD performance degradation. This study is about the manufacturing of advance ArF PSM, which has thinner phase shift layer and higher etch rate Cr absorber film. The thickness of phase shift film is less than 60nm and the total etch-time for the Cr absorber film is reduced more than 30%. The mask CD performance of this new blank was evaluated in terms of CD uniformity, CD linearity, pattern resolution, and loading effect and so on. Adapting to this new blank, we can achieve better CD performance by reducing the loading effect. In addition, the chemical durability and ArF exposure durability were also improved. In conclusion, the mask-making process margin was extended by using this new blank, and it is expected that we can achieve the required specifications for 14nm node and beyond.

6-inch size (known as 6025QZ) binary Cr mask is widely used in the semiconductor lithography for over 20years. Recently for the 450mm wafer process, high grade 9-inch size mask is expected. For this application, we have studied and developed new grade 9-inch size mask blanks for recent 450mm wafer process requirement. There are three types of glass substrates material use and select as 9inch size mask blanks and for required applications by the users. Each glass material has advantage and disadvantage for lithography process as well as wafer process. By knowing the each glass substrate material characteristics and quality level the users enable to select the proper 9inch mask blanks for their targeting applications.

As EUV(Extreme Ultraviolet) Lithography has been delayed because of technical difficulties, ArF-immersion technology is continued to be utilized in the several future years. To progress constantly chip’s minimization and pattern shrink with ArF wavelength, the adoption of aggressive SRAF(Sub Resolution Assist Feature) is inevitable. This trend is giving the big challenge in Photomask industry such as pattern collapse, pattern wiggling and bending. Generally, the reduction of the resist thickness is being tried to solve these problems. But this approach has the limitation, because of depending on the margin of etch process. Additionally, finding appropriate resist must be evaluated by a variety of experiments for verifying the stability of the process. According to several papers, the main reason of pattern collapse is the unbalanced capillary force at drying step in develop process. The capillary stresses (σ) experienced by the resist can be described as shown in equation (1.1) and Figure 1[1].

Mask registration control is one of the key performance specifications during the mask qualification process. It is becoming an important factor for yield improvement with the continuously tightening registration specs driven by tight wafer overlay specs. Understanding the impact of miss classified masks on the final wafer yield is gaining more and more attention, especially with the appearance of Multiple Patterning Technologies, where mask to mask overlay effect on wafer is heavily influenced by mask registration. ZEISS has established a promising closed loop solution implemented in the mask house, where the PROVE® system – a highly accurate mask registration and overlay metrology measurement tool, is being used to feed the RegC® - a registration and mask to mask overlay correction tool that can also accurately predict the correction potential in advance. The well-established RegC® process typically reaches 40-70% improvement of the mask registration/overlay error standard deviation. The PROVE® - RegC® closed loop solution has several advantages over alternative registration control methods apart of the mask re-write saving. Among the advantages is the capability to correct for pellicle mounting registration effects without the need to remove the pellicle. This paper will demonstrate improved method for enhanced mask to mask overlay control based on a new scheme of data acquisition and performance validation by the PROVE®. The mask registration data as well as additional mask information will be used to feed the RegC® correction process. Significantly improved mask to mask overlay correction results will be discussed and presented in details.

EUV (Extreme Ultraviolet) Lithography has been delayed caused by several technical problems such as EUV mask, source power and etc. So ArF immersion lithography has been continued with adopting new technology. Especially, the wafer lithography tends to increase rapidly NTD(Negative Tone Develop) process for overcoming high resolution such as small hole type patterns. For wafer NTD process, the pattern shape in mask has changed from hole pattern to dot pattern. Also the local CD uniformity of aerial image is getting more important. In this paper, we studied local CD uniformity with analyzing aerial images of high transmittance HT-PSM (attenuated phase-shift mask) and conventional 6% HT-PSM from AIMS (Aerial Image Measurement System) tool. Additionally, several cell sizes were analyzed to find an optimum target cell size which has good wafer performance and AIMS aerial image. And we analyzed NILS(Normalized Image Log Slope) factor which represent wafer photolithographic performance. Furthermore, we analyzed not only AIMS NILS simulation, but also wafer lithographic performance.

With the introduction of complex lithography schemes like double and multi – patterning and new design principles like gridded designs with cut masks the requirements for mask to mask overlay have increased dramatically. Still, there are some good news too for the mask industry since more mask are needed and qualified. Although always confronted with throughput demands, latest writing tool developments are able to keep pace with ever increasing pattern placement specs not only for global signatures but for in-die features within the active area. Placement specs less than 3nm (max. 3 Sigma) are expected and needed in all cases in order to keep the mask contribution to the overall overlay budget at an accepted level. The qualification of these masks relies on high precision metrology tools which have to fulfill stringent metrology as well as resolution constrains at the same time. Furthermore, multi-patterning and gridded designs with pinhole type cut masks are drivers for a paradigm shift in registration metrology from classical registration crosses to in-die registration metrology on production features. These requirements result in several challenges for registration metrology tools. The resolution of the system must be sufficiently high to resolve small production features. At the same time tighter repeatability is required. Furthermore, tool induced shift (TIS) limit the accuracy of in-die measurements. This paper discusses and demonstrates the importance of low illumination wavelength together with low aberrations for best contrast imaging for in-die registration metrology. Typical effects like tool induced shift are analyzed and evaluated using the ZEISS PROVE® registration metrology tool. Additionally, we will address performance gains when going to higher resolution. The direct impact on repeatability for small features by registration measurements will be discussed as well.

Shrinking feature sizes and the need for tighter CD (Critical Dimension) control require the introduction of new technologies in mask making processes. One of those methods is the dose assignment of individual shots on VSB (Variable Shaped Beam) mask writers to compensate CD non-linearity effects and improve dose edge slope. Using increased dose levels only for most critical features, generally only for the smallest CDs on a mask, the change in mask write time is minimal while the increase in image quality can be significant. This paper describes a method combining rule-based shot dose assignment with model-based shot size correction. This combination proves to be very efficient in correcting mask linearity errors while also improving dose edge slope of small features. Shot dose assignment is based on tables assigning certain dose levels to a range of feature sizes. The dose to feature size assignment is derived from mask measurements in such a way that shape corrections are kept to a minimum. For example, if a 50nm drawn line on mask results in a 45nm chrome line using nominal dose, a dose level is chosen which is closest to getting the line back on target. Since CD non-linearity is different for lines, line-ends and contacts, different tables are generated for the different shape categories. The actual dose assignment is done via DRC rules in a pre-processing step before executing the shape correction in the MPC engine. Dose assignment to line ends can be restricted to critical line/space dimensions since it might not be required for all line ends. In addition, adding dose assignment to a wide range of line ends might increase shot count which is undesirable. The dose assignment algorithm is very flexible and can be adjusted based on the type of layer and the best balance between accuracy and shot count. These methods can be optimized for the number of dose levels available for specific mask writers. The MPC engine now needs to be able to handle different dose levels and requires a model which accurately predicts mask shapes at all dose levels used. The calibration of such a model is described in a separate paper [1]. In summary this paper presents an efficient method for combining rule-based VSB shot dose assignment with modelbased shape corrections in MPC. This method expands the printability of small features sizes without the need for increasing the base dose of the e-beam writer which reduces backscattering and increases the lifetime of the electron gun of the writer.

A calibrated Optical Proximity Correction Model (OPC) allows the accurate prediction of wafer printing results based on the geometrically defined layout of features. Therefore the OPC Model takes physical parameter of the mask, optical parameter of the printing system and chemical parameter of the resist into account. In order to find a good correlation between OPC simulated data and real wafer prints, the mentioned parameter needs to be calibrated. In the past, this calibration was done based only on the wafer CD SEM measurements. To speed up the calibration process, this paper investigates the possibility to use the aerial image measured by a wafer level critical dimension measurement tool (WLCD) to shorten the feedback loop and to reduce the amount of wafer prints needed for calibration.

The semiconductor manufacturing industry has been continuously shrinking the critical dimension of integrated circuits. An important step in manufacturing integrated circuits is transforming the photomasks into constituent shots, a process referred to as fracturing. A major problem with fracturing is the explosion of shots which leads to long mask write times and costly masks. In this paper, we develop fracturing algorithms that are tailored towards curvilinear layouts, such as those optimized by pixel based OPC. Our proposed fracturing algorithms generate the location, size, and dosage of shots given the mask layout and mask manufacturing parameters. We propose two classes of algorithms that both allow for shot overlap. The first manhattanizes a curvilinear mask and applies our previously developed rectilinear fracturing algorithm upon the resulting rectilinear mask. The second one directly generates the shots by matching the boundary of the input polygon with a dictionary of possible shot corners that are associated with a shot dosage. This is followed by the same rectilinear fracturing algorithm to refine the shot edges. An important feature of all our algorithms is that they can readily trade off between mask error and shot count by adjusting input parameters. Compared to a commercially available non- overlapping shot software package, our algorithm results in up to a 50% reduction in shot count with comparable mask error.

Dummy fill insertion is a necessary step in modern semiconductor technologies to achieve homogeneous pattern density per layer. This benefits several fabrication process steps including but not limited to Chemical Mechanical Polishing (CMP), Etching, and Packaging. As the technology keeps shrinking, fill shapes become more challenging to pattern and require aggressive model based optical proximity correction (MBOPC) to achieve better design fidelity. MBOPC on Fill is a challenge to mask data prep runtime and final mask shot count which would affect the total turnaround time (TAT) and mask cost. In our work, we introduce a novel flow that achieves a robust and computationally efficient fill handling methodology during mask data prep, which will keep both the runtime and shot count within their acceptable levels. In this flow, fill shapes undergo a smart MBOPC step which improves the final wafer printing quality and topography uniformity without degrading the final shot count or the OPC cycle runtime. This flow is tested on both front end of line (FEOL) layers and backend of line (BEOL) layers, and results in an improved final printing of the fill patterns while consuming less than 2% of the full MBOPC flow runtime.

Significant interest from the integrated circuit (IC) industry has been placed on directed selfassembly (DSA) for sub 10nm nodes. DSA is being considered as a cost reduction complementary process to multiple patterning (MP) and an enabler of new technology nodes. However, to realize the potential of this technology, it is essential to look holistically at the necessary infrastructure from the point of view of materials, hardware, software, process integration and design methodologies which enable its deployment in large volume manufacturing. One key aspect in enabling DSA processes is the ability to mirror functionality of full chip mask synthesis and verification methods of existing tools used in production. One of those critical components is the ability to accurately model the placement of the target phases in the DSA process with a given mask shape, as well as determining the conditions at which unwanted phase transitions start to occur. Self-consistent field theory and Monte Carlo1 simulators have the capability to probe and explore the mechanisms driving the different phases of a diblock copolymer system. While such methods are appropriate to study the nature of the self-assembly process, they are computationally expensive and they cannot be used to perform mask synthesis operations nor full chip verification. The nature of a compact model is to make a series of approximations allowing a simpler description of the problem in a way that the phenomena of interest can be sufficiently captured even if it is at the expense of its generality. In this case we focus our effort in establishing the minimum set of conditions that a compact model for the manufacture of contact holes using a grapho epitaxy process for a PS-PMMA diblock copolymer system needs. The processes uses etched short trenches as guiding patterns in which the vertical DSA cylinders are formed. By focusing in the phase of interest (i.e., cylinder forming conditions), it is possible to reformulate the problem in a phenomenological formulation which accounts for the interaction among cylinders, the volume fraction of the respective co-polymers and the interaction with the confinement walls. As such, a 2D approximation to the 3D environment can be applied too simplify thhe representation of the DSA process. This enables thee use of a 2D contour for compact model training and verification. Further simplification is not recommended due to the nature of the grapho-epitaxy guiding patterns, where a simple CD measurement is not sufficient to capture the 2D environment of post routed contact patterns for sub 10nm nodes. In this paper, we will study the application of the DSA compact model to a via layer of imec’s 7nm technology node standard cells. ArF immersion lithography will be used to pattern the guides, and the layout will be DSA compliant to determine the mask complexity as well as the sensitivity of the solution to mask biases for the contact layer.

Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask flow prior to release OPC data to mask house.

Patterning scaling trends are expected to continue until at least the 5 nm node. With the introduction of EUV now delayed until at least the 7 nm node, 193i patterning will continue mainstream use for the foreseeable future. This scaling increases reliance on optimized OPC and illumination and imposes strict requirements on RET solutions, which we define here as source, optics, and mask synthesis (including SRAF). Along with the patterning requirements, any solution must be calculated efficiently. To meet these requirements, a new RET Selection flow has been built using the Calibre platform. This flow includes SMO, Mask synthesis to further tune the output mask, Verification, and Analysis. The entire flow is session based, allowing runs to be cloned, queued, and compared. The flow is built on a robust GUI framework featuring persistent database integration. The central component of the flow is a new SMO algorithm that offers improved scalability using parallel implementation, and improved accuracy using thick mask modeling and resist models. Lithography-aware mask manufacturability limit enforcement is possible using an integrated inverse lithography tool. This also allows large area patterns to be included for RET benchmarking purposes. Finally, the analysis and visualization stages of the flow allow a particular solution to be compared against other candidates using any image metric desired. Comparison metrics can be customized for layer and customer requirements. In this paper, we will summarize the key points of our flow, and demonstrate it using several experiments.

The development of multiple e-beam lithography equipment is seen as an alternative for next generation lithography. However, similarly to EUV lithography, this technology faces important challenges in controlling the contamination of the optics due to deposition of carbon layer induced by the outgassed chemical species from resist under electron bombardment. An experimental setup was designed and built at LETI to study the outgassed species and observe the carbon layer. In this setup, resist coated wafers 100 mm size are exposed under a 5 kV e-beam gun. During exposure, byproducts from outgassed species are monitored with a Residual Gas Analyzer (RGA). The identification of outgassed chemical species is done with an ex-situ TD-GC-MS analysis (ThermoDesorption-Gaz Chromatography-Mass Spectrometry). In a second part of this investigation, we observed the contamination carbon layer growth induced by the outgassing. Thereby, we fabricated a device which consists of a silicon membrane with micro-machined apertures. During e-beam exposure, this device simulates the multiple parallel beams of the optic system of a maskless lithography tool. The deposited contamination layer on device is then observed and thickness measured under SEM. In this paper, we present the results of outgassing and contamination on 3 chemically amplified resists showing that contamination is not directly dependent of the overall outgassing rate but on first order of the outgassing from Photo Acid Generator (PAG). It also reports on the performance in reducing outgassing and contamination of applying a top-coat layer on top of the resist and shows that reduction is more important for contamination than for outgassing.

The increasing complexity of RET solutions has increased the shot count for advanced photomasks. In particular, the introduction of the inverse lithography technique (ILT) brings a significant increase in mask complexity and conventional fracturing algorithms generate many more shots because they are not optimized for curvilinear shapes. Several methods have been proposed to reduce shot count for ILT photomasks. One of the stronger approaches is model-based fracturing, which utilizes precise dose control, shot overlaps and many other techniques. However, it requires much more computation resources and upgrades to the EB mask writer to support user-level dose modulation and shot overlaps. We proposed an efficient algorithm to fracture curvy shapes into VSB shots⁵ which was based on geometry processing. The algorithm achieved better EPE and reasonable process time compared with a conventional fracturing algorithm but its fracturing quality can be degraded for the pattern which has relatively rough contour though it is curvy ILT pattern. In this paper, we present a couple of general techniques to refine a set of VSB shots to reduce edge placement error (EPE) to an original curvy contour with their experimental results.

The on-product overlay specification and Advanced Process Control (APC) are getting extremely challenging particularly after the introduction of multi-patterning applications like Litho-Etch-Litho-Etch (LELE). While the Reticle Writing Error (RWE) contribution could be marginalized for quite some time in the layer-to-layer overlay budget, it will become one of the dominating overlay contributors when the intra-layer overlay budget is considered. While most of the overlay contributors like wafer processing, scanner status, reticle transmission, dose, illumination conditions drop out of the intra-layer overlay budget, this is certainly not the case for reticle to reticle writing differences. In this work, we have studied the impact of the RWE on the on-product overlay performance. We show that the RWE can be characterized by an off-line mask registration tool and the modelled results can be sent as feed-forward corrections to the ASML TWINSCAN^TM. By doing so, the overlay control complexity (e.g. send-ahead wafers, APC settling time) can be reduced significantly. Off-line characterization enables that all reticles virtually become equal after correction (at least to the level of correction capability of the scanner). This means that all higher order RWE contributions (currently up to a third order polynomial) can be removed from the fingerprint. We show that out of 50 production reticles (FEOL, 28-nm technology), 30% can be improved on residual level when non-linear feed-forward corrections are considered as well. The additional benefit of feeding forward linear corrections to the scanner is even higher: it is anticipated that a large portion of the APC variation might find its origin in the RWE contribution. In order to send feed-forward corrections to the scanner, we obviously rely on the quality of the off-line RWE measurements. These measurements are usually provided by a registration tool at the mask shop. To secure the quality, an independent experimental verification test was developed to check if off-line RWE measurements can be used as feed-forward corrections to the scanner. The test has been executed on an ASML NXT: 1950i scanner and was designed such to isolate the reticle writing error contribution. The match between the off-line measurements and the experiment is striking.

For the volume mask production of 28nm node and beyond, the defect disposition is an important factor for mask process, due to the scaling feature sizes and advanced resolution enhancement technologies. In this paper, the series of specifications for different mask patterns have been established from the defect printability study through the behaviors of programmed defects with varies types and sizes on mask, AIMS and wafer. The defect disposition to qualify the mask defects and verify the defect repair proceeds on the basis of the defect printability study. It is found that the defect specification is an effective and industrialized approach for mask production.

The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD’s, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

The march toward tighter design rules, and thus smaller defects, implies stronger surface adhesion between defects and the photomask surface compared to past generations, thereby resulting in increased difficulty in photomask cleaning. Current state-of-the-art wet clean technologies utilize functional water and various energies in an attempt to produce similar yield to the acid cleans of previous generations, but without some of the negative side effects. Still, wet cleans have continued to be plagued with issues such as persistent particles and contaminations, SRAF and feature damages, leaving contaminants behind that accelerate photo-induced defect growth, and others. This paper details work done through a design of experiments (DOE) utilized to qualify an improved cryogenic cleaning technology for production in the Advanced Mask Technology Center (AMTC) advanced production lines for 20 and 14 nm processing. All work was conducted at the AMTC facility in Dresden, Germany utilizing technology developed by Eco-Snow Systems and RAVE LLC for their cryogenic local cleaning VC1200F platform. This system uses a newly designed nozzle, improved gaseous CO2 delivery, extensive filtration to remove hydrocarbons and minimize particle adders, and other process improvements to overcome the limitations of the previous generation local cleaning tool. AMTC has successfully qualified this cryogenic cleaning technology and is currently using it regularly to enhance production yields even at the most challenging technology nodes.