Delivering complexity at the frontier of electronics
Author(s):
Michael C. Mayberry
Show Abstract
The current era of semiconductor research is heavily dependent on the incorporation of new materials into structures measured in nanometers. We require complexity at not only the functional level but complexity in how these functions work together to make better products. The mask set is the critical element in managing that complexity in a cost effective manner but mask making today is challenged to key up with demands. For the next decade, these trends are expected to continue and will suffice to improve the traditional metrics of performance-power and costs. There are many choices to be made but a rich future lies ahead of us.
Line width roughness and its control on photomask
Author(s):
Banqiu Wu;
Ajay Kumar
Show Abstract
Line edge roughness (LER) or line width roughness (LWR) is a fundamental challenge in the semiconductor industry.
LWR on transistor gate length is a dominant parameter for determining the variability of threshold voltage, on-current
and off-current, and LER on interconnect impacts breakdown voltages. Integrated circuit (IC) scaling enabled by
lithography is the technology to increase device density and improve performance. However, scaling below 32nn
technology node induces short-channel effect (SCE) because of the short distance between the transistor source and the
drain. Final LER on the working layer results from several processes, and, thus, LER controls rely on lithography, resist
properties, post-resist-development processing, pattern transfer methods, and photomask LER. Now, pattern generation
is main source of LER, where short exposure wavelength and consecutive low photon numbers result in discrete photon
flux and shot noise, causing high LER. Extreme ultraviolet lithography (EUVL) uses shorter wavelengths and a lower
dose than the current 193 nm lithography, making LWR one of the three most critical challenges. Characterization of
LER is also a challenge. The current rms method is broadly used; however, this approach is not enough and a better
method has yet to be established.
Ultra-low roughness magneto-rheological finishing for EUV mask substrates
Author(s):
Paul Dumas;
Richard Jenkins;
Chuck McFee;
Arun J. Kadaksham;
Dave K. Balachandran;
Ranganath Teki
Show Abstract
EUV mask substrates, made of titania-doped fused silica, ideally require sub-Angstrom surface roughness, sub-30 nm
flatness, and no bumps/pits larger than 1 nm in height/depth. To achieve the above specifications, substrates must
undergo iterative global and local polishing processes. Magnetorheological finishing (MRF) is a local polishing
technique which can accurately and deterministically correct substrate figure, but typically results in a higher surface
roughness than the current requirements for EUV substrates. We describe a new super-fine MRF® polishing fluid
whichis able to meet both flatness and roughness specifications for EUV mask blanks. This eases the burden on the
subsequent global polishing process by decreasing the polishing time, and hence the defectivity and extent of figure
distortion.
Entering mask process correction era for EUV mask manufacturing
Author(s):
Christian Bürgel;
Keith Standiford;
Gek Soon Chua
Show Abstract
The 50keV ebeam exposure of EUV blanks leads to additional electron backscattering from the tantalum layer and the
mirror portion of the blank substrate that cannot be adequately corrected by in-tool algorithms. Coupling this additional
backscatter with process effects, such as develop and etch micro/macro loading, results in significant systematic Critical
Dimension (CD) errors for through pitch and linearity patterns on EUV masks. In wafer production EUV masks are
targeted as single layer exposure, which requires extremely stringent CD control. The systematic CD errors can easily
exceed the CD requirements of a typical EUV mask, facilitating the need for a correction scheme or mask process
correction (MPC).
AMTC and GLOBALFOUNDRIES have started a program to evaluate MPC solutions and drive improvements.
Working closely with companies that provide solutions for ebeam and process modelling along with the corresponding
correction, we have completed several iterations of MPC evaluations. Specifically, we have tested different equipment,
processes and process partitioning for model calibration including a verification of the results.
We report on the results of these evaluations, which include simulation of available models, as well as verification data
from mask prints. We conclude by summarizing the current capabilities of available MPC solutions and present the
remaining gaps for model and correction accuracy as well as the remaining questions for fully implementing MPC into
the process landscape.
Automated Defect Classification (ADC) and Progression Monitoring (DPM) in wafer fab reticle requalification
Author(s):
T. H. Yen;
Rick Lai;
Laurent C. Tuo;
Vikram Tolani;
Dongxue Chen;
Peter Hu;
Jiao Yu;
George Hwa;
Yan Zheng;
Suresh Lakkapragada;
Kechang Wang;
Danping Peng;
Bill Wang;
Kaiming Chiang
Show Abstract
As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continue to diminish, and so
do mask defect requirements due to increasing MEEF. Post-inspection, mask defects have traditionally been classified by
operators manually based on visual review. This approach may have worked down to 65/55nm node layers. However,
starting 45nm and smaller nodes, visually reviewing 50 to sometimes 100s of defects on masks with complex modelbased
OPC, SRAF, and ILT geometries, is error-prone and takes up valuable inspection tool capacity. Both these
shortcomings in manual defect review are overcome by adoption of the computational solution called Automated Defect
Classification (ADC) wherein mask defects are accurately classified within seconds and consistent to guidelines used by
production technicians and engineers.
Performance of an automatic algorithm for quantifying critical dimensions in actinic aerial images
Author(s):
Doug Uzzel;
Mark Ma;
Shad E. Hedges;
Saghir Munir
Show Abstract
This article presents results from an algorithm that can automatically quantify critical dimensions in images
from Mask inspection tools with a very high level of accuracy. Using such an algorithm the inspection
systems can be run with much tighter settings, resulting in more false defect detections that can then be
filtered using the algorithm described here. Such a technique could potentially make the inspection system
suitable for inspecting photo-masks beyond its practical limitation.
Improve mask inspection capacity with Automatic Defect Classification (ADC)
Author(s):
Crystal Wang;
Steven Ho;
Eric Guo;
Kechang Wang;
Suresh Lakkapragada;
Jiao Yu;
Peter Hu;
Vikram Tolani;
Linyong Pang
Show Abstract
As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to
diminish. The adoption of RET techniques like aggressive OPC, sub-resolution assist features combined with
the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable
challenges for mask inspection operators and engineers. Therefore a comprehensive approach is required in
handling defects post-inspections by correctly identifying and classifying the real killer defects impacting the
printability on wafer, and ignoring nuisance defect and false defects caused by inspection systems. This paper
focuses on the results from the evaluation of Automatic Defect Classification (ADC) product at the SMIC mask
shop for the 40nm technology node.
Traditionally, each defect is manually examined and classified by the inspection operator based on a set of predefined
rules and human judgment. At SMIC mask shop due to the significant total number of detected defects,
manual classification is not cost-effective due to increased inspection cycle time, resulting in constrained mask
inspection capacity, since the review has to be performed while the mask stays on the inspection system.
Luminescent Technologies Automated Defect Classification (ADC) product offers a complete and systematic
approach for defect disposition and classification offline, resulting in improved utilization of the current mask
inspection capability. Based on results from implementation of ADC in SMIC mask production flow, there
was around 20% improvement in the inspection capacity compared to the traditional flow. This approach of
computationally reviewing defects post mask-inspection ensures no yield loss by qualifying reticles without the
errors associated with operator mis-classification or human error.
The ADC engine retrieves the high resolution inspection images and uses a decision-tree flow to classify a given
defect. Some identification mechanisms adopted by ADC to characterize defects include defect color in
transmitted and reflected images, as well as background pattern criticality based on pattern topology. The final
classification uses a matrix decision approach for achieving the final defect disposition. As a first step for
qualifying ADC for high volume production, the defect classification results obtained with ADC are compared
to the operator classification. Matching rates of greater than 90% were achieved when compared to operator
defect classifications. Moreover, no critical defect has been missed. ADC performance was proven to be
qualified for deployment in full volume mask manufacturing production flow.
Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation
Author(s):
Sung Jae Ryu;
Sung Taek Lim;
Anthony Vacca;
Peter Fiekowsky;
Dan Fiekowsky
Show Abstract
IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification
inspections are costly for many reasons including the capital equipment, system maintenance, and
labor costs. In addition, masks typically remain in the “requal” phase for extended, non-productive
periods of time. The overall “requal” cycle time in which reticles remain non-productive is
challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master
critical layer reticle is returned to production. Unfortunately, substituting backup critical layer
reticles can significantly reduce an otherwise tightly controlled process window adversely affecting
wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing
hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of
potentially yield-limiting detections, each additional classification increases the risk of manual
review techniques accidentally passing real yield limiting defects. Even assuming all defects of
interest are flagged by operators, how can any person's judgment be confident regarding lithographic
impact of such defects? The time reticles spend away from scanners combined with potential yield
loss due to lithographic uncertainty presents significant cycle time loss and increased production
costs.
Fortunately, a software program has been developed which automates defect classification with
simulated printability measurement greatly reducing requal cycle time and improving overall
disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in
both engineering and high-volume production environments with very successful results. In this
paper, data is presented supporting significant reduction for costly wafer print checks, improved
inspection area productivity, and minimized risk of misclassified yield limiting defects.
Your worst nightmare: inspection of aggressive OPC on 14nm masks with emphasis on defect sensitivity and wafer defect print predictability
Author(s):
Karen D. Badger;
Michael Hibbs;
Jed Rankin;
Kazunori Seki;
Ian Stobert;
Daniel J. Dechene;
Ben Bleiman;
Mini Ghosal;
William Broadbent Jr.;
Vincent Redding
Show Abstract
To prevent catastrophic failures during wafer manufacturing, mask manufacturers employ sophisticated
reticle inspection systems to examine every image on every reticle to identify defects. These advanced
systems inspect at resolutions typically 3x higher at the reticle-plane than advanced wafer scanners; thus
enabling them to detect the small defects necessary to ensure reticle quality.
The most thorough inspection is done using a reticle-to-database comparison that ensures the reticle pattern
matches the design pattern. For high defect sensitivity, the database must be carefully modeled to exactly
match the reticle pattern. Further, sub-resolution OPC shapes are often at the limit of the mask
manufacturing process, which adds subtle variations on such shapes across the reticle. These modeling
errors and process variations can cause high numbers of unwanted detections, thereby limiting inspection
system defect detection sensitivity.[1]
OPC designs are expected to become more aggressive for future generations and may stress the
performance of current reticle inspection systems. To systematically assess the capability of various
inspection approaches and identify needed areas for improvement, a new “Nightmare” test reticle has been
designed by IBM. The test reticle contains various sizes and shapes of sub-resolution features that might
appear on reticle generations from today’s 22nm to future 7nm. It also contains programmed defects to
assess defect detection capability of current and future generation inspection systems.
This paper will discuss the design of the “Nightmare” test reticle, and the inspection results of the current
generation reticle inspection methods with emphasis on both inspectability and defect sensitivity. The subresolution
features will be ranked according to importance for advanced OPC design. The reticle will also
be evaluated using wafer print simulation so lithographic impact of features and defects can be measured
and compared against inspection approaches and results.
The impact of 14nm photomask variability and uncertainty on computational lithography solutions
Author(s):
John Sturtevant;
Edita Tejnil;
Peter D. Buck;
Steffen Schulze;
Franklin Kalk;
Kent Nakagawa;
Guoxiang Ning;
Paul Ackmann;
Fritz Gans;
Christian Buergel
Show Abstract
Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables
for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can
become significant. In this work, we examine via simulation, the impact of errors in the representation of
photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. The simulations are done by ignoring the wafer photoresist model, and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the 1D/2D representation of the mask and for 3D, that the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.
An accurate ILT-enabling full-chip mask 3D model for all-angle patterns
Author(s):
Hongbo Zhang;
Qiliang Yan;
Ebo Croffie;
Lin Zhang;
Yongfa Fan
Show Abstract
As the technology node keeps shrinking down to sub-28 nm, mask topography (Mask3D) effect is one of the most influential factors to draw intensive research lately. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. Different approaches have been tried to resolve the difficulties in the full-chip modeling, but so far none of the existing Mask3D modeling methods have succeeded in meeting all the three criterion at the same time. It is often seen that an existing Mask3D model to succeed in one or two criteria, but fails in the rest. In this paper, we propose our innovative full chip Mask3D modeling method to successfully handle the above criterion at the same time. To our best of knowledge, it is the first ever Mask3D modeling in literature that is be able to achieve this goal. In our modeling flow, we first analyze the Mask3D effect by using rigorous simulation as the reference and generate edge-based kernels to mimic the Mask3D effect near the feature boundaries. The flexibility of handling the kernel helps us enable the support for all-angle patterns and be extendable for edge coupling effect and off-axis illumination. Our experimental results show that with only less than 30% runtime overhead compared to the conventional Mask2D model, we are able to achieve less than 0.8 nm CD RMS on the flexible feature patterns. An ILT-based OPC and simulation result is provided to validate the capability of all-angle support of our proposed model.
Simulation study of CD variation caused by field edge effects and out-of-band radiation in EUVL
Author(s):
Weimin Gao;
Ardavan Niroomand;
Gian F. Lorusso;
Robert Boone;
Kevin Lucas;
Wolfgang Demmerle
Show Abstract
Although extreme ultraviolet lithography (EUVL) remains a promising candidate for semiconductor
device manufacturing of the 1x nm half pitch node and beyond, many technological burdens have to
be overcome. The “field edge effect” in EUVL is one of them. The image border region of an EUV
mask,also known as the “black border” (BB), reflects a few percent of the incident EUV light,
resulting in a leakage of light into neighboring exposure fields, especially at the corner of the field
where three adjacent exposures take place. This effect significantly impacts on CD uniformity
(CDU) across the exposure field. To avoid this phenomenon, a light-shielding border is introduced
by etching away the entire absorber and multi-layer (ML)at the image border region of the EUV
mask. In this paper, we present a method of modeling the field edge effect (also called the BB effect)
by using rigorous lithography simulation with a calibrated resist model. An additional “flare level”
at the field edge is introduced on top of the exposure tool flare map to account for the BB effect. The
parameters in this model include the reflectivity and the width of the BB, which are mainly
determining the leakage of EUV light and its influence range, respectively. Another parameter is the
transition width which represents the half shadow effect of the reticle masking blades. By setting the
corresponding parameters, the simulation results match well the experimental results obtained at the
imec’s NXE:3100 EUV exposure tool. Moreover, these results indicate that the out-of-band (OoB)
radiation also contributes to the CDU. Using simulation we can also determine the OoB effect
rigorouslyusing the methodology of an “effective mask blank”. The study in this paper demonstrates
that the impact of BB and OoB effects on CDU can be well predicted by simulations.
Color balancing for triple patterning lithography with complex designs
Author(s):
Haitong Tian;
Hongbo Zhang;
Martin D. F. Wong
Show Abstract
With the minimum feature size keeps shrinking, there are increasing difficulties to print these small features using one exposure (LE) or double exposures (LELE). To resolve the inherent physical limitations for current lithography techniques, triple patterning lithography (LELELE) has been widely recognized as one the most promising options for 14/10nm technology node. For triple patterning lithography (TPL), the designers are more interested in finding a decomposition with none of the three masks overwhelms the other. This color balancing issue is of crucial importance to ensure that consistent and reliable printing qualities can be achieved. In our previous work,18 a simple color balancing scheme is proposed to handle designed without stitches, which is not capable of handling complex designs with stitches. In this paper, we further extend the previous approach to be able to simultaneously optimizing the number of stitches and balancing the color usage in the three masks. This new approach is very efficient and robust, and guarantees to find a color balancing decomposition while achieving the optimal number of stitches. For the largest benchmark with over 10 million features, experimental results show that the new approach achieves almost perfect color balancing with reasonable runtime.
450mm wafer patterning with jet and flash imprint lithography
Author(s):
Ecron Thompson;
Paul Hellebrekers;
Paul Hofemann;
Dwayne L. LaBrake;
Douglas J. Resnick;
S. V. Sreenivasan
Show Abstract
The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must
account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability,
individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set,
with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the
infrastructure necessary to the transition, with a focus on the development of both process and metrology tools.
Central to any process module development, which includes deposition, etch and chemical mechanical polishing is
the lithography tool. In order to address the need for early learning and advance process module development,
Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450,
capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being
used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to
facilitate the semiconductor industry’s transition to lower cost 450mm wafer production.
The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV
curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively
being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and
displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and
defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology
to a 450mm lithography platform.
2013 mask industry survey
Author(s):
Matt Malloy
Show Abstract
A comprehensive survey was sent to merchant and captive mask shops to gather information about the mask industry as
an objective assessment of its overall condition. 2013 marks the 12th consecutive year for this process. Historical topics
including general mask profile, mask processing, data and write time, yield and yield loss, delivery times, maintenance,
and returns were included and new topics were added. Within each category are multiple questions that result in a
detailed profile of both the business and technical status of the mask industry.
While each year’s survey includes minor updates based on feedback from past years and the need to collect additional
data on key topics, the bulk of the survey and reporting structure have remained relatively constant. A series of
improvements is being phased in beginning in 2013 to add value to a wider audience, while at the same time retaining
the historical content required for trend analyses of the traditional metrics. Additions in 2013 include topics such as top
challenges, future concerns, and additional details in key aspects of mask masking, such as the number of masks per
mask set per ground rule, minimum mask resolution shipped, and yield by ground rule. These expansions beyond the
historical topics are aimed at identifying common issues, gaps, and needs. They will also provide a better understanding
of real-life mask requirements and capabilities for comparison to the International Technology Roadmap for
Semiconductors (ITRS).
Computational mask defect review for contamination and haze inspections
Author(s):
Paul Morgan;
Daniel Rost;
Daniel Price;
Noel Corcoran;
Masaki Satake;
Peter Hu;
Danping Peng;
Dean Yonenaga;
Vikram Tolani;
Yulian Wolf;
Pinkesh Shah
Show Abstract
As optical lithography continues to extend into sub-0.35 k1 regime, mask defect inspection and subsequent review has
become tremendously challenging, and indeed the largest component to mask manufacturing cost. The routine use of
various resolution enhancement techniques (RET) have resulted in complex mask patterns, which together with the need
to detect even smaller defects due to higher MEEFs, now requires an inspection engineer to use combination of
inspection modes. This is achieved in 193nm AeraTM mask inspection systems wherein masks are not only inspected at
their scanner equivalent aerial exposure conditions, but also at higher Numerical Aperture resolution, and special
reflected-light, and single-die contamination modes, providing better coverage over all available patterns, and defect
types. Once the required defects are detected by the inspection system, comprehensively reviewing and dispositioning
each defect then becomes the Achilles heel of the overall mask inspection process.
Traditionally, defects have been reviewed manually by an operator, which makes the process error-prone especially
given the low-contrast in the convoluted aerial images. Such manual review also limits the quality and quantity of
classifications in terms of the different types of characterization and number of defects that can practically be reviewed
by a person. In some ways, such manual classification limits the capability of the inspection tool itself from being setup
to detect smaller defects since it often results in many more defects that need to be then manually reviewed.
Paper 8681-109 at SPIE Advanced Lithography 2013 discussed an innovative approach to actinic mask defect review
using computational technology, and focused on Die-to-Die transmitted aerial and high-resolution inspections. In this
approach, every defect is characterized in two different ways, viz., quantitatively in terms of its print impact on wafer,
and qualitatively in terms of its nature and origin in the mask manufacturing process. The latter characterization qualifies
real defect signatures, such as pin-dots or pin-holes, extrusions or intrusions, assist-feature or dummy-fill defects, writeerrors
or un-repairable defects, chrome-on-shifter or missing chrome-from-shifter defects, particles, etc., and also false
defect signatures, such as those due to inspection tool registration or image alignment, interlace artifacts, CCD camera
artifacts, optical shimmer, focus errors, etc. Such qualitative characterization of defects has enabled better inspection tool
SPC and process defect control in the mask shop.
In this paper, the same computational approach to defect review has been extended to contamination style defect
inspections, including Die-to-Die reflected, and non Die-to-Die or single-die inspections. In addition to the
computational methods used for transmitted aerial images, defects detected in die-to-die reflected light mode are
analyzed based on special defect and background coloring in reflected-light, and other characteristics to determine the
exact type and severity. For those detected in the non Die-to-Die mode, only defect images are available from the
inspection tool. Without a reference, i.e., defect-free image, it is often difficult to determine the true nature or impact of
the defect in question. Using a combination of inspection-tool modeling and image inversion techniques, Luminescent’s
LAIPHTM system generates an accurate reference image, and then proceeds with automated defect characterization as if
the images were simply from a die-to-die inspection. The disposition of contamination style defects this way, filters out
>90% of false and nuisance defects that otherwise would have been manually reviewed or measured on AIMSTM.
Such computational defect review, unifying defect disposition across all available inspection modes, has been imperative
to ensuring no yield losses due to errors in operator defect classification on one hand, and on the other, has enhanced
defect characterization and detection capability of the inspection platform itself notwithstanding the number of defects
detected in the process.
Evaluation of dry technology for removal of pellicle adhesive residue on advanced optical reticles
Author(s):
Shazad Paracha;
Samy Bekka;
Benjamin Eynon;
Jaehyuck Choi;
Mehdi Balooch;
Ivin Varghese;
Tyler Hopkins
Show Abstract
The fast pace of MOSFET scaling is accelerating the introduction of smaller technology nodes to
extend CMOS beyond 20nm as required by Moore’s law. To meet these stringent requirements, the
industry is seeing an increase in the number of critical layers per reticle set as it move to lower
technology nodes especially in a high volume manufacturing operation. These requirements are
resulting in reticles with higher feature densities, smaller feature sizes and highly complex Optical
Proximity Correction (OPC), built with using new absorber and pellicle materials. These rapid
changes are leaving a gap in maintaining these reticles in a fab environment, for not only haze control
but also the functionality of the reticle. The industry standard of using wet techniques (which uses
aggressive chemicals, like SPM, and SC1) to repel reticles can result in damage to the sub‐resolution
assist features (SRAF’s), create changes to CD uniformity and have potential for creating defects that
require other means of removal or repair. Also, these wet cleaning methods in the fab environment
can create source for haze growth. Haze can be controlled by: 1) Chemical free (dry) reticle cleaning,
2) In‐line reticle inspection in fab, and 3) Manage the environment where reticles are stored. In this
paper we will discuss a dry technique (chemical free) to remove pellicle adhesive residue from
advanced optical reticles. Samsung Austin Semiconductors (SAS), jointly worked with Eco‐Snow
System (a division of RAVE N.P., Inc.) to evaluate the use of Dry Reactive Gas (DRG) technique to
remove pellicle adhesive residue on reticles. This technique can significantly reduce the impact to the
critical geometry in active array of the reticle, resulting in preserving the reticle performance level
seen at wafer level. The paper will discuss results on the viability of this technique used on advanced
reticles.
Inline detection of Chrome degradation on binary 193nm photomasks
Author(s):
Félix Dufaye;
Astrid Sippel;
Mark Wylie;
Edgardo García-Berríos;
Charles Crawford;
Carl Hess;
Luca Sartelli;
Carlo Pogliani;
Hiroyuki Miyashita;
Stuart Gough;
Frank Sundermann;
Christophe Brochard
Show Abstract
193nm binary photomasks are still used in the semiconductor industry for the lithography of some critical layers for the
nodes 90nm and 65nm, with high volumes and over long periods. However, these 193nm binary photomasks can be
impacted by a phenomenon of chrome oxidation leading to critical dimensions uniformity (CDU) degradation
with a pronounced radial signature. If not detected early enough, this CDU degradation may cause defectivity issues and
lower yield on wafers. Fortunately, a standard cleaning and repellicle service at the mask shop has been demonstrated as efficient to remove the grown materials and get the photomask CD back on target.Some detection methods have
been already described in literature, such as wafer CD intrafield monitoring (ACLV), giving reliable results but also
consuming additional SEM time with less precision than direct photomask measurement.
In this paper, we propose another approach, by monitoring the CDU directly on the photomask, concurrently with defect
inspection for regular requalification to production for wafer fabs. For this study, we focused on a Metal layer in a 90nm
technology node. Wafers have been exposed with production conditions and then measured by SEM-CD. Afterwards,
this photomask has been measured with a SEM-CD in mask shop and also inspected on a KLA-Tencor X5.2 inspection
system, with pixels 125 and 90nm, to evaluate the Intensity based Critical Dimension Uniformity (iCDU) option.
iCDU was firstly developed to provide feed-forward CDU maps for scanner intrafield corrections, from arrayed dense
structures on memory photomasks. Due to layout complexity and differing feature types, CDU monitoring on logic
photomasks used to pose unique challenges.The selection of suitable feature types for CDU monitoring on logic
photomasks is no longer an issue, since the transmitted intensity map gives all the needed information, as shown in this
paper.
In this study, the photomask was heavily degraded after more than 18,000 300mm wafers exposed and the cleaning
brought it back almost to its original state after manufacture. Wafer CD, photomask CD and iCDU results can be
compared, before and after a standard mask shop cleaning. Measurement points have be chosen in logic areas and
SRAM areas, so that their respective behaviours can be studied separately. Transmitted maps before and after cleaning
were analysed in terms of CD shift and CDU degradation. The delta map shows a nice correlation with photomask CD
shift. iCDU demonstrated the capability to detect a reliable CD range degradation of 5nm on photomask by a comparison
between a reference inspection and the current inspection. Die to die inspection mode provides also valuable data,
highlighting the degraded chrome sidewalls, more in the photomask centre than on the edges.
Ultimately, these results would enable to trigger the preventive cleanings rather than on predefined thresholds. The
expected gains for wafer fabs are cost savings (adapted cleanings frequency), increased photomask availability for
production, longer photomask lifetime, no additional SEM time neither for photomask nor on wafer.
Comparison of CD measurements of an EUV photomask by EUV scatterometry and CD-AFM
Author(s):
Frank Scholze;
Victor Soltwisch;
Gaoliang Dai;
Mark-Alexander Henn;
Hermann Gross
Show Abstract
EUV scatterometry is a potential high-throughput measurement method for the characterization of EUV photomask
structures. We present a comparison of angle resolved extreme ultraviolet (EUV) scatterometry and critical dimension
atomic force microscope (CD-AFM) as a reference metrology for measurements of geometrical parameters like line
width (CD), height and sidewall angle of EUV photomask structures. The structures investigated are dense and semidense
bright and dark lines with different nominal CDs between 140 nm and 540 nm. The results show excellent linearity
of the critical dimension measured with both methods within a range of only 1.8 nm and an offset of the absolute values
below 3 nm. A maximum likelihood estimation (MLE) method is used to reconstruct the shape parameters and to
estimate their uncertainties from the measured scattering efficiencies. The newly developed CD-AFM at PTB allows
versatile measurements of parameters such as height, CD, sidewall angle, line edge/width roughness, corner rounding,
and pitch. It applies flared tips to probe steep and even undercut sidewalls and employs a new vector approaching
probing (VAP) strategy which enables very low tip wear and high measurement flexibility. Its traceability is ensured by
a set of calibrated step-height and reference CD standards.
Two-dimensional mask effects at the 14 nm logic node
Author(s):
A. E. Zweber;
A. McGuire;
M. Hibbs;
S. Nash;
K. Ballman;
T. Faure;
J. Rankin;
T. Isogawa;
T. Senna;
Y. Negishi;
M. Miller;
S. Barai;
D. J. Dechene
Show Abstract
At the 14 nm logic node, significant lithographic changes relative to previous technologies are needed to resolve smaller
features with increased fragmentation in mask design and increased use of sub-resolution assist features. Extending the
application of 193 immersion lithography for further generations requires not only continued reduction of traditional
sources of variation but investigation into and quantification of the impact of completely new ones, such as mask twodimensional
(2D) variability. To improve the overall lithography model accuracy, two-dimensional (2D) data from the
mask is required to complete a mask model with an optimal wafer response. This paper characterizes and assesses the
importance of 2D mask effects on thin opaque MoSi on glass (OMOG) masks. Methodologies for characterizing corner
rounding in terms of corner rounding radius and contact area are presented. Optical mask 2D measurements and wafer
print results are summarized.
Measurement of EUV absorber and resist CD using spectroscopic ellipsometer
Author(s):
Kyung M. Lee;
Malahat Tavassoli;
Pei-yang Yan;
Guojing Zhang
Show Abstract
Evaluation of lithography process or stepper involves very large quantity of CD measurements and measurement
time. In this paper, we report on an application of Scatterometry based metrology for evaluation of EUV photomask
lithography. Measurements were made on mask level with Ellipsometric scatterometer for develop-check CD (DCCD)
and final check CD (FCCD). Calculation of scatterometer profile information was performed with in-situ library-based
rigorous coupled wave analysis (RCWA) method. We characterized the CD uniformity (CDU) and metal film thickness
uniformity. OCD results show that high precision CD measurement EUV absorber and resist is possible with this
method.
A series of simulations were also performed to investigate the feasibility of Ellipsometric scatterometry for various
pitches/line CD sizes, down to 11nm half-pitch at 1x magnification. The data showed that Scatterometry provides a
nondestructive and faster mean of characterizing mask CD performance for various EUV process generations.
Reflecting on inspectability and wafer printability of multiple EUV mask absorbers
Author(s):
Kazunori Seki;
Karen Badger;
Emily Gallagher;
Gregory McIntyre;
Toshio Konishi;
Yutaka Kodera;
Satoshi Takahashi;
Vincent Redding
Show Abstract
Four EUV film stacks are prepared and evaluated from multiple points of view: mask fabrication, blank inspection, nonactinic
inspection, actinic inspection and wafer print. Mask linearity measurements show very good results for all of four
blanks. Blank inspection results reveal similar inspectability. Blank roughness and reflectivity at 193nm wavelength
were also measured. Some types of defects were evaluated with both non-actinic inspection tools and simulations. It was
found that the thinner low reflectivity (LR) stack shows higher defect sensitivity than the thicker ones for pattern defects
at 193nm inspection wavelengths. Phase defect evaluations indicate that thinner total film stacks (LR plus absorber) have
an advantage for phase defect detection. Defect printability was evaluated through focus by imaging on an EUV
microscope and defect printability was shown to be equivalent among the four stacks. Then the appropriate film stacks
are discussed from the wafer point of view. Finally the appropriate stack was chosen based on evaluations from all the
various points of view.
The SEMATECH high-NA actinic reticle review project (SHARP) EUV mask-imaging microscope
Author(s):
Kenneth A. Goldberg;
Iacopo Mochi;
Markus P. Benk;
Chihcheng Lin;
Arnaud P. Allezy;
Michael Dickinson;
Carl W. Cork;
James B. Macdougall;
Erik H. Anderson;
Weilun Chao;
Farhad Salmassi;
Eric M. Gullikson;
Daniel Zehm;
Vamsi Vytla;
William Cork;
Jason DePonte;
Gino Picchi;
Ahmet Pekedis;
Takeshi Katayanagi;
Michael S Jones;
Elizabeth Martin;
Patrick P Naulleau;
Senajith B Rekawa
Show Abstract
The SEMATECH High Numerical Aperture Actinic Reticle Review Project (SHARP) is a newly commissioned,
synchrotron-based extreme ultraviolet (EUV) microscope dedicated to photomask research. SHARP offers several major
advances including objective lenses with 4xNA values from 0.25 to 0.625, flexible, lossless coherence control through a
Fourier-synthesis illuminator, a rotating azimuthal plane of incidence up to ±25°, illumination central ray angles from 6 to 10°, and a continuously tunable, EUV illumination wavelength. SHARP is now being used to study programmed and
native mask defects, defect repairs, mask architecture, optical proximity correction, and the influence of mask substrate
roughness on imaging. SHARP has the ability to emulate a variety of current and future lithography tool numerical
apertures, and illumination properties. Here, we present various performance studies and examples where SHARP’s
unique capabilities are used in EUV mask research.
EUV patterned mask inspection system using a projection electron microscope technique
Author(s):
Hidehiro Watanabe;
Ryoichi Hirano;
Susumu Iida;
Tsuyoshi Amano;
Tsuneo Terasawa;
Masahiro Hatakeyama;
Takeshi Murakami;
Shoji Yoshikawa;
Kenji Terao
Show Abstract
The concept and the current status of a newly developed PEM pattern inspection system are presented. An
image-processing technique with learning functions to enhance the system’s detection capability is investigated. Highly
accelerated electrons employed here in electron-optics function as an enabler to improve the image resolution and
transmittance in the system, and to acquire an image contrast of 0.5 in a half pitch (hp) 64 nm lines and space pattern.
This process also results in the formation of an electron image with more than 3000 electrons per pixel on a sensor. The
image-processing system was also developed for die-to-die inspection. The alignment error is minimized to a negligibly
small size by a continuous 2D pattern matching. An ensemble of signal characteristics enables the identification of any
defect signal in a noisy electron image. The developed detection system met the requirements for hp16 nm generation.
Defects on high-resolution negative-tone resist: "The revenge of the blobs"
Author(s):
M. I. Sanchez;
L. K. Sundberg;
L. D. Bozano;
R. Sooriyakumaran;
D. P. Sanders;
T. Senna;
M. Tanabe;
T. Komizo;
I. Yoshida;
A. E. Zweber
Show Abstract
Resist materials rely on solubility differences between the exposed and unexposed areas to create the
desired image. Most negative-tone resists achieve the solubility difference by crosslinking the exposed area
causing it to be insoluble in developer. The negative tone resist studied here is a high sensitivity negativetone
resist that relies on polarity switching, similar to a positive-tone mechanism, but where the exposed
area is insoluble in aqueous developer resulting in a negative-tone image. During mask evaluation for 14nm
optical technology applications of the studied non-cross linking (polarity switching) resist, 1 - 5 μm size
blob-like defects were found in large numbers under certain exposure conditions. This paper will describe
the process and methodologies used to investigate these blob defects.
Controlling the sidewall angle of advanced attenuated phase-shift photomasks for 14nm and 10nm lithography
Author(s):
Richard Wistrom;
Yoshifumi Sakamoto;
Jeffery Panton;
Thomas Faure;
Takeshi Isogawa;
Anne McGuire
Show Abstract
As optical lithography is extended to the 14nm and 10nm technology nodes, sidewall angle (SWA) control of photomask
features becomes increasingly important. The experiments to be reported here study SWA for advanced attenuated
phase-shift photomasks. SWA is evaluated from three perspectives. First, the effects of mask etch process parameters
will be studied. Second, the effects of local mask environment, such as etch loading and line width, will be tested.
Finally, a variety of SWA measurement methods will be compared.
Model-based etch profile simulation of PSM films
Author(s):
Michael Grimbergen;
Madhavi Chandrachood;
Jeffrey Tran;
Becky Leung;
Keven Yu;
Amitabh Sabharwal;
Ajay Kumar
Show Abstract
For advanced binary and PSM mask etch, final profile control is critically important for achieving desired mask
specifications. As an aid to attain profile control, an etch profile simulation method has been developed. The method
starts with an initial photoresist profile and incorporates etch rate and directionality information to predict the final etch
profile. In this paper, simulated results are compared to measured etch profiles for PSM substrates. The results highlight
the importance and implications of incoming resist profile and etch selectivity on final profile.
Implementable and systematic mitigation of native defects in EUV masks
Author(s):
Wen-Chang Hsueh;
Li-Chih Yeh;
Ming-Jiun Yao;
Yun-Yue Lin;
Jia-Jen Chen;
Shin-Chang Lee;
Anthony Yen
Show Abstract
Native defects in mask blanks is one of the key issues in extreme ultraviolet lithography. If defect-free mask blanks
is the only solution, the resulting cost will be very high due to the low yield of such blanks. In this paper, we present a
method for fabricating defect-free-like EUV masks by implementing several novel techniques such as global pattern shift,
fine metrology-orientation and precise e-beam second-alignment from blank preparation to e-beam exposure. The mitigation
success rate versus mask pattern density is simulated and verified by lithographic results using mitigated masks.
Our methodology provides a way to achieve defect-free-like EUV mask blanks.
Studying the effects of modified surface chemistry on chrome migration in binary photomasks
Author(s):
Christopher Kossow;
Peter Kirlin;
Michael Green
Show Abstract
Migration of the Cr/CrxOy film in binary photomasks during use in 193nm photolithography has been observed for some
time in the semiconductor industry. This phenomenon leads to a shift in the reticle critical dimensions (CDs) that worsen
with increased exposure eventually resulting in wafer yield loss. This paper studies the impact of varying annealing
conditions on the CrxOy species on the surface of the mask. Further, we examined the effect of a surface condition with
maximized Cr2O3 content on the 193nm-induced chrome migration phenomenon. Scanning Electron Microscopy (SEM),
Transmission Electron Microscopy (TEM), and X-Ray Photoelectron Spectroscopy (XPS) were used to characterize the
composition of the Cr/CrxOy film. A 193nm accelerated exposure test bench was used to induce film migration in samples of varying surface chemistry.
Investigation of EUVL reticle capping layer peeling under wet cleaning
Author(s):
Sherjang Singh;
Davide Dattilo;
Uwe Dietze;
Arun John Kadaksham;
Il-Yong Jang;
Frank Goodwin
Show Abstract
In the absence of a pellicle, an EUVL reticle is expected to withstand up to 100 cleaning cycles. EUVL reticles
constitute a complex multi-layer structure with extremely sensitive materials which are prone to damage during
cleaning. The 2.5 nm thin Ru capping layer has been reported to be most sensitive to repeated cleaning, especially
when exposed to aggressive dry etch or strip chemicals [1]. Such a Ru film exhibits multiple modes of failure under
wet cleaning processes. In this study we investigated the Ru peeling effect. IR-induced thermo-stress in the multilayer
and photochemical-induced radical attack on the surface are investigated as the two most dominant
contributors to Ru damage in cleaning. Results of this investigation are presented and corrective actions are
proposed.
1D design style implications for mask making and CEBL
Author(s):
Michael C. Smayling
Show Abstract
At advanced nodes, CMOS logic is being designed in a highly regular design style because of the resolution limitations of optical lithography equipment. Logic and memory layouts using 1D Gridded Design Rules (GDR) have been demonstrated to nodes beyond 12nm.[1-4] Smaller nodes will require the same regular layout style but with multiple patterning for critical layers.
One of the significant advantages of 1D GDR is the ease of splitting layouts into lines and cuts. A lines and cuts approach has been used to achieve good pattern fidelity and process margin to below 12nm.[4] Line scaling with excellent line-edge roughness (LER) has been demonstrated with self-aligned spacer processing.[5]
This change in design style has important implications for mask making:
• The complexity of the masks will be greatly reduced from what would be required for 2D designs with very complex OPC or inverse lithography corrections.
• The number of masks will initially increase, as for conventional multiple patterning.
But in the case of 1D design, there are future options for mask count reduction.
• The line masks will remain simple, with little or no OPC, at pitches (1x) above 80nm.
This provides an excellent opportunity for continual improvement of line CD and LER. The line pattern will be processed through a self-aligned pitch division sequence to divide pitch by 2 or by 4.
• The cut masks can be done with “simple OPC” as demonstrated to beyond 12nm.[6] Multiple simple cut masks may be required at advanced nodes. “Coloring” has been demonstrated to below 12nm for two colors and to 8nm for three colors.
• Cut/hole masks will eventually be replaced by e-beam direct write using complementary e-beam lithography (CEBL).[7-11] This transition is gated by the availability of multiple column e-beam systems with throughput adequate for high- volume manufacturing.
A brief description of 1D and 2D design styles will be presented, followed by examples of 1D layouts. Mask complexity for 1D layouts patterned directly will be compared to mask complexity for lines and cuts at nodes larger than 20nm. No such comparison is possible below 20nm since single-patterning does not work below ~80nm pitch using optical exposure tools.
Also discussed will be recently published wafer results for line patterns with pitch division by-2 and by-4 at sub-12nm nodes, plus examples of post-etch results for 1D patterns done with cut masks and compared to cuts exposed by a single-column e-beam direct write system.
Charting CEBL's role in mainstream semiconductor lithography
Author(s):
David K. Lam
Show Abstract
historically kept it out of mainstream fabs. Thanks to continuing EBDW advances combined with the industry’s move to
unidirectional (1D) gridded layout style, EBDW promises to cost-efficiently complement 193nm ArF immersion (193i)
optical lithography in high volume manufacturing (HVM).
Patterning conventional 2D design layouts with 193i is a major roadblock in device scaling: the resolution limitations of
optical lithography equipment have led to higher mask cost and increased lithography complexity. To overcome the
challenge, IC designers have used 1D layouts with “lines and cuts” in critical layers.1
Leading logic and memory chipmakers have been producing advanced designs with lines-and-cuts in HVM for several
technology nodes in recent years. However, cut masks in multiple optical patterning are getting extremely costly.
Borodovsky proposes Complementary Lithography in which another lithography technology is used to pattern line-cuts
in critical layers to complement optical lithography.2 Complementary E-Beam Lithography (CEBL) is a candidate to
pattern the Cuts of optically printed Lines.
The concept of CEBL is gaining acceptance. However, challenges in throughput, scaling, and data preparation rate are
threatening to deny CEBL’s role in solving industry’s lithography problem. This paper will examine the following
issues:
The challenges of massively parallel pixel writing
The solutions of multiple mini-column design/architecture in:
Boosting CEBL throughput
Resolving issues of CD control, CDU, LER, data rate, higher resolution, and 450mm wafers
The role of CEBL in next-generation solution of semiconductor lithography
Impact of proximity model inaccuracy on patterning in electron beam lithography
Author(s):
Cheng-Hung Chen;
Tsung-Chih Chien;
P. Y. Liu;
W. C. Wang;
J. J. Shin;
S. J. Lin;
Burn J. Lin
Show Abstract
Electron beam lithography is a promising technology for next generation lithography. Compared to optical
lithography, it has better pattern fidelity and larger process window. However, the proximity effect caused by the
electron forward scattering and backscattering in the resist and the underlying substrate materials has a severe influence
on the pattern fidelity when the required critical dimensions (CD) are comparable to the electron beam blur size.
Therefore, an accurate electron scattering model and a proper proximity correction play a vital role in electron beam
lithography. In this paper, we describe the model accuracy of electron scattering in terms of multiple Gaussian kernels
with an in-house proximity error correction to reduce proximity error with much better accuracy and more
self-consistency than the double Gaussian kernel on the 100-keV electron energies. The impact of various Gaussian
kernels used in the proximity correction on the lineation of typical patterns is also addressed.
Mask automation: need a revolution in mask makers and equipment industry
Author(s):
Seong-yong Moon;
Sang-yong Yu;
Young-hwa Noh;
Ki-jung Son;
Hyun-Joo Lee;
Han-Ku Cho
Show Abstract
As improving device integration for the next generation, high performance and cost down are also required
accordingly in semiconductor business. Recently, significant efforts have been given on putting EUV
technology into fabrication in order to improve device integration. At the same time, 450mm wafer
manufacturing environment has been considered seriously in many ways in order to boost up the productivity.
Accordingly, 9-inch mask has been discussed in mask fabrication business recently to support 450mm wafer
manufacturing environment successfully. Although introducing 9-inch mask can be crucial for mask industry,
multi-beam technology is also expected as another influential turning point to overcome currently the most
critical issue in mask industry, electron beam writing time. No matter whether 9-inch mask or multi-beam
technology will be employed or not, mask quality and productivity will be the key factors to survive from the
device competition. In this paper, the level of facility automation in mask industry is diagnosed and analyzed
and the automation guideline is suggested for the next generation.
DSA template mask determination and cut redistribution for advanced 1D gridded design
Author(s):
Zigang Xiao;
Yuelin Du;
Martin D.F. Wong;
Hongbo Zhang
Show Abstract
Directed self-assembly (DSA) technology has already demonstrated its capability for isolated and grouped contact/via pattern for 1D gridded design. If we reverse the resist tune, this technique can also be used to implement the cut printing. However, for this purpose, we need to redistribe the cuts by extending the real wires to form the desired cut distribution for template mask making. Based on this assumption, we propose an algorithm to redistribute the original cuts such that they form groups of non-conflict DSA templates. Experimental results demonstrate that our method can effectively redistribute the cuts and improve the layout manufacturability.
Finishing of EUV photomask substrates by CNC precessed bonnet polisher
Author(s):
Anthony T. H. Beaucamp;
Yoshiharu Namba;
Phillip Charlton;
Richard R. Freeman
Show Abstract
The progressive transition from Excimer to EUV lithography is driving a need for flatter and smoother photomasks. It is
proving difficult to meet this next generation specification with the conventional chemical mechanical polishing
technology commonly used for finishing photomasks. This paper reports on the application of sub-aperture CNC
precessed bonnet polishing technology to the corrective finishing of photomask substrates for EUV lithography. Fullfactorial
analysis was used to identify process parameters capable of delivering 0.5 nm rms surface roughness whilst
achieving removal rates above 0.1 mm3/min. Experimental results show that masks pre-polished to 300~600 nm P-V flatness by CMP can then be improved down to 50~100 nm P-V flatness using the automated technology described in
this paper. A series of edge polishing experiments also hints at the possibility of increasing the quality area beyond the 5
mm defined in the official EUV photomask specification.
Simulation and correction of resist charging due to fogging in electron-beam lithography
Author(s):
Sergey Babin;
Sergey Borisov;
Vladimir Militsin;
Elena Patyukova
Show Abstract
Improvements in the variation of critical dimensions (CD) and placement accuracy in electron beam
lithography (EBL) are of high importance in the modern maskmaking industry where acceptable variations
are on the one nanometer range over the mask area. In EBL, electrons backscatter from the resist and
substrate, reach the bottom of objective lens and come back to the resist, causing undesirable exposure and
charging far away from the point of exposure. This fogging affects both CD variation and placement
accuracy. The Monte Carlo software CHARIOT was upgraded to be capable of simulating this fogging effect.
The results of simulations are presented for variety of conditions. The results were used for the correction of
charging placement error. Fogging is one of the contributing factors to the charging placement error; the
DISPLACE software tool predicts the displacement map for any layout, system setup and exposure strategy,
which allows for the correction of placement error in maskmaking.
A novel design-based global CDU metrology for 1X nm node logic devices
Author(s):
Young-Keun Yoon;
Dong Hoon Chung;
Min-Ho Kim;
Jung-Uk Seo;
Byung-Gook Kim;
Chan-Uk Jeon;
JiUk Hur;
Wonil Cho;
Tetsuya Yamamoto
Show Abstract
As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks
becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical
techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate
the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view
(FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics.
For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a
long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of
masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement
sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns
are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the
mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a
statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in
order to maximize the coverage area on a mask.
In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data
base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the
patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle
multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its
fundamental performance such as accuracy, repeatability, and correlation with other CD metrology tools with a set of
logic masks.
EUV scatterometry-based measurement method for the determination of phase roughness
Author(s):
Rikon Chao;
Eric Gullikson;
Michael Goldstein;
Frank Goodwin;
Ranganath Teki;
Andy Neureuther;
Patrick Naulleau
Show Abstract
AFM-based roughness measurement reveals the topography of EUV masks, but is only sensitive to the top surface [1].
Scatterometry provides a more accurate approach to characterize the effective phase roughness of the multilayer, and it
becomes important to determine the valid metrology for roughness characterization. In this work, the power spectral
density calculated from scatterometry is compared to that from AFM for measurements before and after coating of
substrates with a range of roughness levels. Results show noticeable discrepancies between AFM- and scatterometrymeasured
roughness, and indicates that when the physical surface roughness increases with deposition the EUV
penetration into the multilayer tends to mitigate this effect. In this paper, we describe an EUV scatterometry-based
measurement method for the determination of phase roughness with the goal of minimizing the amount of physical
scattering data to be collected and rendering the method compatible with potential future standalone EUV reflectometer
tools.
SEM image quality enhancement technology for bright field mask
Author(s):
Naoki Fukuda;
Yuta Chihara;
Soichi Shida;
Keisuke Ito
Show Abstract
Bright-field photomasks are used to print small contact holes via ArF immersion multiple patterning lithography. There
are some technical difficulties when small floating dots are to be measured by SEM tools because of a false imaging
shadow. However, a new scan technology of Multi Vision Metrology SEMTM E3630 presents a solution for this issue. The combination of new scan technology and the other MVM-SEM® functions can provide further extended applications with more accurate measurement results.
Direct phase-shift measurement of an EUV mask with gradient absorber thickness
Author(s):
Hiroyoshi Tanabe;
Tetsunori Murachi;
Seh-Jin Park;
Eric M. Gullikson;
Tsukasa Abe;
Naoya Hayashi
Show Abstract
We directly extracted the phase-shift values of an EUV mask by measuring the reflectance of the mask. The mask had
gradient absorber thickness along vertical direction. We measured the reflectance of the open multilayer areas and the
absorber areas by using an EUV reflectometer at various absorber thicknesses. We also measured the diffracted 0th order
light intensities of grating patterns having several sizes of lines or holes. The phase-shift values were derived from these
data assuming a flat mask interference model of the diffracted lights. This model was corrected by including the
scattering amplitude from the pattern edges. We recalculated the phase-shift values which was free from the mask
topological effect. The extracted phase-shift value was close to 180 degrees at 67 nm and 71 nm absorber thicknesses.
The phase measurement error around 180 degree phase shift was 5 degrees (3σ).
Performance of the proof-of-concept multi-beam mask writer (MBMW POC)
Author(s):
Christof Klein;
Hans Loeschner;
Elmar Platzgummer
Show Abstract
Two proof-of-concept electron multi-beam mask writer tools (MBMW POC) have been realized,which are
utilizing262,144 programmable beams of 20nm beam size and 50keV beam energy to pattern 6" mask blanks. Tool
characterization details and test results are outlined. Especially,LMSIPRO4 measurements (after development
inspection) of short term and long term stability of the 82μm x 82μm beam array field are discussed.Scale stability of
the beam array field of 0.1nm per day is demonstrated.
Shot count reduction for non-Manhattan geometries: concurrent
optimization of data fracture and mask writer design
Author(s):
Russell Cinque;
Tadashi Komagata;
Taiichi Kiuchi;
Clyde Browning;
Patrick Schiavone;
Paolo Petroni;
Luc Martin;
Thomas Quaglio
Show Abstract
VSB mask writers, which create patterns using a combination of rectangles and 45 degree triangles, are ill-suited to non-
Manhattan geometries. This issue is particularly acute for layouts which contain a large fraction of curvilinear “offangle”
patterns such as photonic or DRAM designs. Unable to faithfully reproduce the “off-angle” structures, traditional
VSB mask writers approximate the desired design using abutted rectangular shots or small shapes to smooth out line
edge roughness. Fidelity to the original pattern comes at a cost of increased shot count and reduced throughput.
Aselta has developed a novel fracture algorithm to dramatically reduce the shot count of such designs. Using a traditional
VSB pattern generator, the new algorithm provides significant shot count reduction. When combined with a modified
JBX-3200MV VSB, the shot count is reduced while maintaining the same level of fidelity. The data preparation software
tool has also the capability of trading off a more accurate level of fidelity with an even more reduced shot count.
The paper will first describe the basic principles of the fracturing algorithm and e-beam writer hardware configuration
then demonstrate the advantage of the method on a variety of patterns.
Turret-type electron gun for EBM-8000
Author(s):
Nobuo Miyamoto;
Rodney Kendall;
Kenichi Saito
Show Abstract
To reduce down time associated with routine cathode replacement we developed a turret-type electron gun
for our electron beam mask writer, EBM-8000. This enables us to exchange cathodes without venting the gun
to atmosphere, thereby reducing the downtime for cathode replacement by 80% compared to conventional
single-cathode guns.
Two key elements were considered in developing the turret-type electron gun: reducing fluctuation in beam
current, and eliminating discharge sources.
Reducing fluctuation in beam current is one of the most important elements because it has an impact to
critical CD accuracy. In EBM-8000, the current fluctuation must be 0.1% (3s) or less to attain the CD
accuracy specification. We will explain how the beam stability is realized.
Special treatment to eliminate discharge sources is necessary to realize long-term stability of the electron
gun. We devised a conditioning sequence which repeatedly increases and decreases the voltage applied to the
barrel in N2 atmosphere. This conditioning sequence allowed us to dramatically decrease the probability of
discharges, allowing us to achieve long-term stability operation.
EUV multilayer defect compensation (MDC): latest progress on model and compensation methods
Author(s):
Linyong Pang;
Masaki Satake;
Ying Li;
Peter Hu;
Danping Peng;
Dongxue Chen;
Vikram Tolani
Show Abstract
Making a multilayer defect-free extreme ultraviolet (EUV) blank is not possible today, and is unlikely to happen in the
next few years. The method proposed by Luminescent is to compensate effects of multilayer defects on images by
modifying the absorber patterns. Progress in MDC is the subject of this paper. The multilayer growth model was
calibrated using real data - the top layer profile captured by AFM and cross section captured by TEM for programmed
defects. Multilayer defect profiles on repair sites were recovered by applying inverse methods with the calibrated model
to AFM surface scans. The recovered defect profiles were fed into the MDC engine to calculate modified absorber
patterns that would compensate for the defects. Further, new methods to compensate for phase errors by depositing
materials or peeling multilayers in addition to absorber modifications have been developed. Different options of
multilayer peeling for compensating phase error are also evaluated through simulation. A case study was performed to
find out what is the maximum pit and bump defects that can be compensated by all options available. It shows absorber
pattern modification plus material deposition is the most effective option for pit defect, while absorber pattern
modification plus layer-by-layer multilayer peeling is the most effective option for bump defect. Either of these methods
can fix defects up to four times larger than those that can be fixed by only modifying absorber patterns near them.
Using segmented models for initial mask perturbation and OPC speedup
Author(s):
Ayman Hamouda;
Mohab Anis;
Karim S. Karim
Show Abstract
Sub-wavelength photolithography heavily depends on OPC (optical proximity correction), where the pattern fidelity
and CD Uniformity can never be achieved without a good OPC. The OPC runtime-resource factor has been
exponentially increasing every node. It is currently approaching a dangerous level in terms of runtime and cost as
the 20nm node is approaching production. A reasonable portion of the OPC computation is spent in small iterative
mask perturbations trying to reach a state that prints closer to the OPC target, followed by the final few iterations
aiming to accurately achieve printability on target with an almost zero EPE (edge placement error). In our work, we
propose replacing the first few iterations of OPC with a single fast multi-model iteration that can perturb the OPC
mask into a shape that is very close to its final state. This approach is proven to reduce the OPC runtime by an
average of 28% without degrading the final mask quality.
Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies
Author(s):
J-C. Michel;
J-C. Le Denmat;
E. Sungauer;
F. Robert;
E. Yesilada;
A-M. Armeanu;
J. Entradas;
J. L. Sturtevant;
T. Do;
Y. Granik
Show Abstract
Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted
overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology
nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer
topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the
use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a
consequence, computational lithography solutions are currently under development in order to correct wafer
topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography
effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer
stack.
In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology
is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational
verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC
flow for chip scale mask correction is presented with quality and run time penalty analysis.
High-fidelity dummy fill printing with repair OPC
Author(s):
Louis Lin;
Wei-Long Wang;
Sarah McGowan
Show Abstract
Dummy fill plays a crucial role on both controlling topography uniformity and ensuring device performance by
manipulating homogenous pattern density. There are several types of fill to achieve this purpose on advanced
technologies. The conventional way is to place them out of optical ambit range from main features as reference for
Optical Proximity Correction (OPC) procedure, but it degrades the FILL performance due to leaving considerable empty
space between FILL and main features. The aggressive way is to place FILL as close as main features to perfectly
achieve uniform pattern density. However, in this way, it’s challenge to produce defect-free FILL in ORC (Optical
Review Check) without applying model-based OPC on FILL which boost the OPC cycle time significantly. In this paper,
we propose a novel approach by in-stage Repair OPC technique to not only accurately print aggressive placement FILL
on the wafer accurately but also reduce the impact of run time cost on full chip OPC processing.
Phase preservation study on ArF mask for haze-free mask resist strip and cleaning
Author(s):
Irene Shi;
Eric Guo;
Eric Tian;
Tracy Gu;
Forrest Jiang;
Sandy Qian;
Daisuke Matsushima;
Jinyuan Pang
Show Abstract
Ozonated water, as an alternative to a Sulfuric – Peroxide Mixture (SPM), was introduced to the resist strip and cleaning
processes to prevent surface haze formation through the elimination of sulfuric acid from these processes. [1] [2] [3] [4] [5]
However, it also was found to cause significant change of optical characteristics and CD-linewidth shift on ArF6%
attenuation phaseshift masks (AttPSM). Although the use of 172nm Excimer UV light irradiation treatment before the
cleancouldimprove the above-mentioned shifts, after several clean cycle, this phase/CD preservation effect would be
dramatically degraded.[6] [7] [8]
In this paper, a novel approach of phase preservationto usedry treatments based on reactive plasma Asher as part of acid-free
resist strip or cleaning process is introduced. [9][10] We have investigated on the surface material integrity and CD stability
of MoSi based shifters and compared with above-mentioned approach of 172nm UV light irradiation treatment, and tried to
illustrate and explain the principle. Not only Asher process but also UV irradiation, is supposed to be kind of oxygen
activation process to accelerate oxidization on MoSi based shifter of ArF AttPSM masks, and created passivation layer
would stand out for wet cleaning; furthermore, plasma Asher process is in prior to UV irradiation. As shown in Cross-section
profiles on the masks without and with Asher process, although the deference is very limited, it may be proved that a thin
passivation layer was created on the surface and side of MoSi based shifter after Asher process.
A study on the ESD damage of a silicon oxy-nitride hard mask on the chromium surface of PSM blank
Author(s):
Songbae Moon;
Heebom Kim;
Inkyun Shin;
Chanuk Jeon
Show Abstract
A thin silicon oxy-nitride hard mask on the PSM blank is needed for the feature patterning with the size smaller
than 70 nm. It is a good material for hard mask. However, the electrical property of silicon oxy-nitride with the thickness
smaller than 10 nm causes the chromium surface damage during the mask processes. From the measurement of the
surface damage, we figure out that the chromium surface damage is originated from the charging and the dielectric
breakdown phenomena. In our present work, two types of silicon oxy-nitride film with the thicknesses of 5 nm and 12
nm are tested for verifying optimal mask fabrication processes. We find that the occurrence of ESD damage is related to
the thickness of silicon oxy-nitride hard mask and mask fabrication process conditions. The optimal fabrication process
condition for silicon oxy-nitride thin film hard mask, in which break-down never occurs, is discussed.
In-die mask registration measurement on 28nm-node and beyond
Author(s):
Shen Hung Chen;
Yung Feng Cheng;
Ming Jui Chen
Show Abstract
As semiconductor go to smaller node, the critical dimension (CD) of process become more and more small. For
lithography, RET (Resolution Enhancement Technology) applications can be used for wafer printing of smaller CD/pitch
on 28nm node and beyond. SMO (Source Mask Optimization), DPT (Double Patterning Technology) and SADP
(Self-Align Double Patterning) can provide lower k1 value for lithography. In another way, image placement error and
overlay control also become more and more important for smaller chip size (advanced node). Mask registration (image
placement error) and mask overlay are important factors to affect wafer overlay control/performance especially for DPT or
SADP.
In traditional method, the designed registration marks (cross type, square type) with larger CD were put into scribe-line
of mask frame for registration and overlay measurement. However, these patterns are far way from real patterns. It does not
show the registration of real pattern directly and is not a convincing method. In this study, the in-die (in-chip) registration
measurement is introduced. We extract the dummy patterns that are close to main pattern from post-OPC (Optical
Proximity Correction) gds by our desired rule and choose the patterns that distribute over whole mask uniformly. The
convergence test shows 100 points measurement has a reliable result.
Alternative material to mitigate chrome degradation on high volume ArF layers
Author(s):
Guoxiang Ning;
Selvi Gopalakrishnan;
Thomas Thamm;
Nikolay Oleynik;
Paul Ackmann;
Remi Riviere;
Stephanie Maelzer;
Yee Mei Foong
Show Abstract
One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation including
3D mask effects or mask models for different mask blanks. Assuming that the data of different reticle blanks is the same,
the wafer data should be a close match for the same OPC model. In order to enhance the robustness of the OPC model,
the 3D mask effects need to be reduced. A test of this would be to ensure a close match of the so called fingerprints of
different reticle blanks at the wafer level. Features for fingerprint test patterns include “critical dimension through pitch”
(CDTP), “inverse CDTP”, and “linearity patterns” and critical dimension (CD) difference of disposition structures. In
this manuscript the proximity matching of implant layers on chrome on glass (COG) and advance binary reticle blanks
will be demonstrated. We will also investigate the influence of reticle blank material including reticle process on isolated
and dense features upon the proximity matching for 28 nm high volumes ArF layers such as implant and 2X metal
layers. The OPC model verification has been done successfully for both bare wafer and full field wafer for implant
layers. There is comparable OPC model for advanced binary and COG reticle. Moreover, the wafer critical dimension
uniformity (CDU) results show that advance binary has much better wafer CDU then COG. In spite of higher reticle cost
when switching over to advanced binary, there is a considerable cost reduction for the wafer fab which includes a 39%
savings in total reticle cost as well as cost reduction due to minimal line holds (LH), wafer reworks and scraps due to
Chrome degradation.
OPC modeling using AFM CD measurement
Author(s):
Kyoil Koo;
Gyengseop Kim;
Sanghun Kim;
Seunghune Yang;
Sooryong Lee;
Youngchang Kim;
Jungdal Choi;
Hokyu Kang
Show Abstract
Most important factors in OPC model building will be sampling data for model calibration.
We will demonstrate that how CD-AFM data can be used in OPC modeling and will show possibility to get a more predictive model by using CD-AFM data.
Increased depth of field through wave-front coding: using an off-axis zone plate lens with cubic phase modulation
in an EUV microscope
Author(s):
Markus P. Benk;
Kenneth A. Goldberg;
Iacopo Mochi;
Weilun Chao;
Erik H. Anderson
Show Abstract
The authors are extending the capabilities of the SHARP microscope (SEMATECH High-NA Actinic Reticle review
Project) by implementing wave front coding as a complementary imaging mode. SHARP, using a single off-axis lens has
a tilted focal plane, reducing the instrument’s field of view to a few micrometers. Wave-front coding increases the depth
of field of an incoherent imaging system without affecting its resolution and light gathering power, rendering clear,
large-field images for navigation and analysis. The resolution of the resulting image is close to the diffraction limit of the
unmodified system. The authors have designed and nanofabricated zone plate lenses with a modified pattern that
combines focusing power and wave front coding in a single optical element. The study clears the path to further
applications of wave front coded zone plates in lab- and synchrotron-based microscopes and metrology tools. The
authors have demonstrated wave-front coding in visible-light optical systems using Fresnel zone plate lenses in an offaxis
configuration similar to SHARP. Simulations complementing the visible light experiments assess the performance of
wave-front coded zone plates in the SHARP microscope.
A study of the defect detection technology using the optic simulation for the semiconductor device
Author(s):
Yusin Yang;
Yongdeok Jeong;
Mitsunori Numata;
Mira Park;
Mingoo Seo;
SangKil Lee;
ChungSam Jun;
Kyupil Lee;
Insoo Cho
Show Abstract
In the era of sub-30nm devices, the size of the defects on semiconductor wafer has already exceeded the resolution limit
of optic microscope, but we still can't help using optical inspection tools. Therefore, the contrast enhancement technique
is more useful rather than the resolution itself. The best contrast can be taken by the optimized light conditions such as
wavelength, polarization, incidence angle and so on. However these kinds of parameters are not easily estimated
intuitively because they are strongly dependent on the pattern structures and materials. In this paper, we propose a
simulation methodology to find those optic conditions to detect sub 20nm defect. The simulation is based on FDTD
(Finite Difference Time Domain) calculation and Fourier optics.
Mask contamination study in electron and ion beam repair system
Author(s):
Hyo-Jin Ahn;
Jong-Min Kim;
Dong-Seok Lee;
Gyu-Yong Lee;
Dong-Heok Lee;
Sang-Soo Choi
Show Abstract
At 32nm technology node and beyond, the number of defect to be repaired is increased because pattern size is shrunk
and the detecting ability of inspection system higher than before. In repair system, mask surface is exposed to the
various contaminations such as contamination from vacuum chamber wall, reaction gas for repair etc. Although
contaminations deposited on mask surface are removed by followed cleaning process, it makes reflectance change on
scan area detected by high resolution inspection system. This reflectance change on scan area in repair system detected
during inspection is big burden for mask making because the number of scan area requires more time to confirm and
need AIMS simulation if there is any issue on the area. Most of all, it is hard to find where the exact repaired pattern is
and verify whether there are no problems because inspection system does not detect exact repaired pattern but detect all
scan area. Especially, this phenomenon is more observed to MoSi absorber of OMOG mask.
In this paper, we demonstrate the findings of contamination source and the root cause of contamination using surface
analyzing methods, ToF-SIMS(Time of Flight-SIMS) and AFM(Atomic Force Microscope). In addition, preventive
strategy to minimize and remove reflectance change issue in repair system will be discussed.
Sensitivity analysis for OMOG and EUV photomasks characterized by UV-NIR spectroscopic ellipsometry
Author(s):
A. Heinrich;
I. Dirnstorfer;
J. Bischoff;
K. Meiner;
U. Richter;
T. Mikolajick
Show Abstract
We investigated the potentials, applicability and advantages of spectroscopic ellipsometry (SE) for the
characterization of high-end photomasks. The SE measurements were done in the ultraviolet-near infrared (UVNIR)
wavelength range from 300 nm to 980 nm, at angle of incidences (AOI) between 10 and 70° and with a
microspot size of 45 x 10 μm2 (AOI=70°). The measured Ψ and 𝛥 spectra were modeled using the rigorous coupled wave analysis (RCWA) to determine the structural parameters of a periodic array, i.e. the pitch and
critical dimension (CD). Two different types of industrial photomasks consisting of line/space structures were
evaluated, the reflecting extreme ultraviolet (EUV) and the transmitting opaque MoSi on glass (OMOG) mask.
The Ψ and 𝛥 spectra of both masks show characteristic differences, which were related to the Rayleigh
singularities and the missing transmission diffraction in the EUV mask. In the second part of the paper, a
simulation based sensitivity analysis of the Fourier coefficients α and β is presented, which is used to define the required measurement precision to detect a CD deviation of 1%. This study was done for both mask types to
investigate the influence of the stack transmission. It was found that sensitivities to CD variations are
comparable for OMOG and EUV masks. For both masks, the highest sensitivities appear close to the Rayleigh
singularities and significantly increase at very low AOI. To detect a 1% CD deviation for pitches below 150 nm
a measurement precision in the order of 0.01 is required. This measurement precision can be realized with
advanced optical hardware. It is concluded that UV-NIR ellipsometry is qualified to characterize photomasks
down to the 13 nm technology node in 2020.
Fleet matching performance for multiple registration measurement tools
Author(s):
D. Beyer;
C. Bläsing;
K. Boehm;
S. Heisig;
D. Seidel
Show Abstract
Currently semiconductor industry drives the 193nm lithography to its limits, using techniques like double exposure,
double patterning, mask-source optimisation and inverse lithography. These requirements trend to full in-die
measurement capability of photomask metrology for registration. Especially, overlay becomes more and more critical
and must be ensured on every die. For this, Carl Zeiss SMS has developed the next generation photomask registration
and overlay metrology tool PROVE which is already well established in the market. To ensure in-die measurement
capability, sophisticated image analysis methods based on 2D correlations have been developed.
A key component for registration tool users is the cross site manufacturing flexibility given by the matching capability of
all its metrology tools. Therefore all PROVE tools offer a tool matching procedure based on 2D Golden Grid
references. In this paper we first review the optimal length standard and golden grid matching procedures of modern
registration metrology tools. Systematic errors in fleet matching based on illumination differences, thermal expansionbased
issues or line width roughness are addressed. The tool matching performance of PROVE tools is demonstrated by
comparing up to 7 different tools. All tools are well within accuracy and long-term repeatability specification which
considerably reduces the statistical error contribution of the tool matching performance. For grid matched tools the final
cross tool registration error is shown to be below 1nm.
The recovering method of etch chamber condition by using the optical emission spectroscopy monitoring system
Author(s):
Choong Han Ryu;
Jae Young Jun;
Ho Yong Jung;
Sang Pyo Kim;
Dong Gyu Yim
Show Abstract
The etch chambers has been cleaned by wet process and replaced with new parts to maintain etch chamber perfectly
clean. However, the wet cleaning process results in following issues. One of issues is that the critical dimension mean to
target (CD MTT) and phase-shift would be changed due to the variation of etch rate, which is generally caused by the
new parts and wet chamber cleaning process. Another issue is that the wet cleaning process takes long time to recover
the chamber condition. Moreover, the production will be stopped until recovering the chamber condition. Therefore,
the recovering time should be minimized to keep the high productivity of etch tool.
The change of chamber condition during the plasma seasoning can be monitored with the optical emission
spectroscopy (OES) system. The optical emission intensity represents the concentration of materials in the plasma and
the surface condition of chamber. The OES peak intensities were collected during the plasma seasoning, which was
applied to remove the moisture and residues. The correlation of the OES peak intensities and chamber condition was
verified by the CD and phase-shift difference between pre and post chamber cleaning. This methodology was applied to optimize the seasoning time, which occupies 80% of whole the chamber cleaning process time.
Analysis of EUV mask durability under various absorber etch conditions
Author(s):
Dong Wook Lee;
Sang Jin Jo;
Sung Hyun Oh;
Tae Joong Ha;
Sang Pyo Kim;
Dong Gyu Yim
Show Abstract
During EUV exposure, more frequent mask cleaning is essential for removing not only particles from lack
of pellicle but also the carbon contamination due to accumulative EUV exposure. Because of this reason,
process improvement for minimize corrosion and etching of the Ru capping layer is urgently needed. In this
work, the influence of TaBN absorber etch condition on Ru integrity followed by repetitive cleaning was
evaluated and the effects on long-term durability of Ru are compared under various cleaning conditions.
Consequently, it was shown that Ru durability was strongly influenced by the gas contents and over etch time
of absorber dry etch, not only as a function of cleaning conditions.
Metrology variability and its impact in process modeling
Author(s):
Thiago Figueiro;
Mohamed Saib;
Kang-Hoon Choi;
Christoph Hohle;
Martin J. Thornton;
Cyril Vannufel;
Jean-Hervé Tortai;
Patrick Schiavone
Show Abstract
In electron proximity effects correction (PEC), the quality of a correction is highly dependent on the quality of the model
used to compute the effects. Therefore it is of primary importance to have a reliable methodology to extract the
parameters and assess the quality of a model. Usually, model calibration procedures consist of one or more cycles of
exposure and measurements on the calibration stage. The process and metrology variability may play a key role in the
quality of the final model and, hence, of the PEC result. Therefore, it is important to determine at which level these
variations may impact a calibration procedure and how a calibration design may be implemented in order to enable more
robustness to the resulting model.
In this work, metrology variability was evaluated by measuring the same wafer using two different CD-SEM tools. The
information coming from these analyses was used as reference to a variation induced calibration test using synthetic
data. By inserting variability in synthetic data it was possible to evaluate its impact on the resulting parameter values and
in the final model error evaluation.
Pupil shaping and coherence control in an EUV mask-imaging microscope
Author(s):
Iacopo Mochi;
Kenneth A. Goldberg;
Markus P. Benk;
Patrick P. Naulleau
Show Abstract
We are investigating the effect of pupil-fill patterns and partial coherence settings on EUV reticle images on the new
SEMATECH High-NA Actinic Reticle review Project (SHARP), to deepen our understanding of its performance, and
improve the emulation of image formation in arbitrary printing tools. SHARP is an EUV mask microscope developed as
the successor of the SEMATECH Berkeley Actinic Inspection Tool (AIT). It is equipped with a unique, MEMS-based
Fourier synthesis illuminator that generates arbitrary, customized pupil fill patterns to control the illumination partial
coherence. The high-magnification objective lenses are an array of interchangeable Fresnel zoneplates with 4×NA values
ranging from 0.25 to 0.625.
We have used SHARP to inspect isolated and dense features with half pitch as low as 55 nm using lenses with a range of
NA values, and common illumination patterns, such as annular, dipole and QUASAR™. We will show the effect of
illumination on important, measured pattern parameters, including contrast, normalized image log-slope, and depth of
focus.
We have also studied the effect of partial coherence on the imaging of on multilayer roughness observed in bright mask
regions, a topic important for expanding our understanding of the causes of LER.
Efficient full-chip mask 3D model for off-axis illumination
Author(s):
Hongbo Zhang;
Qiliang Yan;
Lin Zhang;
Ebo Croffie;
Peter Brooker;
Qian Ren;
Yongfa Fan
Show Abstract
Mask topography (Mask3D) effect is one of the most influential factors in sub-28 nm technology node. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. In the meanwhile, Mask3D modeling must be able to handle the off-axis illumination (OAI) condition accurately. In this paper, we propose our full chip Mask3D modeling method which is an extension to the edge-based Mask3D model. In our modeling flow, we first review the edge-based Mask3D model and then analyze the impact from the off-axis source. We propose a parameter-based extension to characterize the off-axis impact efficiently. We further introduce two methods to calibrate the OAI-aware parameters by using rigorous or wafer data as the reference. Our experimental results show the great calibration accuracy throughout the defocus range with OAI sources, and validate the accuracy of our two parameter calibration approach.
In-die mask registration for multi-patterning
Author(s):
F. Laske;
S. Kunitani;
T. Kamibayashi;
M. Yamana;
A. Fuse;
M. Wagner;
K.-D. Roeth;
M. Ferber;
M. Daneshpanah;
S. Czerkas;
H. Sakaguchi
Show Abstract
193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes.
Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts
extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The
International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each
mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic
nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error
impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to
support full in-die registration metrology on reticles.
Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process
Author(s):
Avi Cohen;
Thomas Trautzsch;
Ute Buttgereit;
Erez Graitzer;
Ori Hanuka
Show Abstract
Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable
functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule
shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task
in IC manufacturing.
In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to
improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It
combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while
applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short
femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material.
The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field
CDU improves.
The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and
pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity
and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for
the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been
effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.
A fast convolution method using basis expansion for highly efficient intensity calculation in mask optimization
Author(s):
Yaping Sun;
Yehua Zuo;
Jinyu Zhang;
Yan Wang;
Zhiping Yu
Show Abstract
Finer grid representation is inevitable to describing mask patterns more accurately in inverse lithography technology
(ILT), thus resulting in large-size mask representation and heavy computational cost. In this work we proposed a fast
convolution method called convolution using basis expansion (CBE) method to resolve computational issues caused by
intensive convolutions. The CBE method process can be elaborated as: 1) Project mask and kernel matrices from fine
grid representation to coarse grid representation under certain basis functions, which is similar to DCT or wavelet
transformations. This matrix formed by the expansion coefficient can be considered as the projection of the original large
matrix on coarse grid; 2) Perform mask and kernel convolutions on coarse grids; 3) the convolution result on fine grids is
restored by interpolation method. The selection of the basis set can be arbitrary. In this paper, we compare the
convolution accuracy and computational cost using 1) linear basis function; 2)discrete cosine basis function; 3) basis
function based on K-L transform for different fine and coarse matrix size ratios n in both 1-D and 2-D conditions. Also,
the quantitative interpolation error of cubic spline interpolation function is discussed. In numerical verification of aerial
image calculation, this new method provides almost the same effectiveness and 10X~20X running speed improvement
comparing to traditional convolution method. The CBE method will show its large effectiveness and efficiency in mask
optimization.
Impact of an etched EUV mask black border on imaging: part II
Author(s):
Natalia Davydova;
Robert de Kruif;
Hiroaki Morimoto;
Yo Sakata;
Jun Kotani;
Norihito Fukugami;
Shinpei Kondo;
Tomohiro Imoto;
Brid Connolly;
Dries van Gestel;
Dorothe Oorschot;
David Rio;
John Zimmerman;
Noreen Harned
Show Abstract
The image border is a pattern free dark area around the die on the photomask serving as transition area between
the parts of the mask that is shielded from the exposure light by the Reticle Masking (ReMa) blades and the die.
When printing a die at dense spacing on an EUV scanner, the reflection from its image border overlaps with the
edges of neighboring dies affecting CD and contrast in this area. This is related to the fact that EUV absorber
stack has 1-3% reflectance for actinic light. For a 55nm thick absorber the induced CD drop at the edges is
found to be 4-5 nm for 27 nm dense lines. In this work we will show an overview of the absorber reflection
impact on CD at the edge of the field across EUV scanner generations, for several imaging nodes and multiple
absorber heights.
Increasing spacing between dies on the wafer would prevent the unwanted exposure but results in an
unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable
manufacturing solution. In order to mitigate the reflection from the image border one needs to create a so called
black border. The most promising approach is removal of the absorber and the underlying multilayer down to
the low reflective LTEM substrate by multilayer etching. It was shown in the previous study that the impact
on CD was reduced essentially for 27 nm dense lines exposed on ASML NXE:3100.
In this work we will continue the study of a multilayer etched black border impact on imaging. In particular, 22
nm lines/spaces imaging on ASML NXE:3300 EUV scanner will be investigated in the areas close to the black
border as well as die to die effects. We will look closer into the CD uniformity impact by DUV Out-of-Band
light reflected from black border and its mitigation. A possible OPC approach will also be evaluated.
Development of inspection system for EUV mask with novel projection electron microscopy (PEM)
Author(s):
Masahiro Hatakeyama;
Takeshi Murakami;
Kenji Terao;
Kenji Watanabe;
Shoji Yoshikawa;
Tsuyoshi Amano;
Ryoichi Hirano;
Susumu Iida;
Tsuneo Terasawa;
Hidehiro Watanabe
Show Abstract
In order to realize EUV mask pattern defect inspection in 16nm node, we have developed new optics on a novel
projection electron microscopy (PEM) and a new inspection system with the new optics and a new mask handling and
imaging units, e.g., a high precision stage, an imaging detector, an imaging processing system, and so. on. This
inspection system enables us to make the inspection in high resolution and high speed as compared with conventional
DUV and EB inspection systems. The new optics on the novel PEM comprises an exposure and an imaging electron
beam optics (EOs). The optics is based on the new design concept to meet the required progress for 1Xnm EUV mask
inspection as compared to the current inspection system for 2Xnm node; The concept employs new techniques to
achieve the features: high energetic electron imaging optics to have low aberration, high transmittance efficiency, e.g.,
on the ratio of exposure current/emitted current, in the exposure and the imaging optics, respectively. The new handling
and imaging system are also based on the design concept of imaging in high resolution by combination operation among
the new optics on the novel PEM, the stage, and the detector. In this paper, we describe the basic performance evaluation
as concerning these features and the operation: 1) MTF inclination in hp44~100nm L/S pattern of the developed
imaging optics. 2) Secondary electron imaging by the integrated optics, i.e., both of the exposure and the imaging EOs,
on the novel PEM, 3) Secondary electron image acquisition operation in still mode on the new inspection system
assembled with the new optics on the novel PEM, the high precision stage, the detector, and so. on.. The results show the
new optics on the novel PEM is capable to meet the required progress for 1Xnm EUV mask inspection and the new
inspection system with the novel PEM operates in much feasibility in the electron image acquisition.
A novel method for utilizing AIMS to evaluate mask repair and quantify over-repair or under-repair condition
Author(s):
Doug Uzzel;
Anthony Garetto;
Krister Magnusson;
Gilles Tabbone
Show Abstract
The ZEISS AIMS™ platform is well established as the industry standard for qualifying the printability of mask features
based on the aerial image. Typically the critical dimension (CD) and intensity at a certain through-focus range are the
parameters which are monitored in order to verify printability or to ensure a successful repair. This information is
essential in determining if a feature will pass printability, but in the case that the feature does fail, other metrology is
often required in order to isolate the reason why the failure occurred, e.g., quartz level deviates from nominal.
Photronics-nanoFab, in collaboration with Carl Zeiss, demonstrate the ability to use AIMSTM to provide quantitative
feedback on a given repair process; beyond simple pass/fail of the repair. This technique is used in lieu of Atomic Force
Microscopy (AFM) to determine if failing post-repair regions are "under-repaired” (too little material removed) or
“over-repaired” (too much material removed).
Using the ZEISS MeRiT E-beam repair tool as the test platform, the AIMSTM technique is used to characterize a series
of opaque repairs with differing repair times for each. The AIMSTM technique provides a means to determine the etch depth based on through-focus response of the Bossung plot and further to predict the amount of MeRiT® recipe change required in order to bring out of spec repairs to a passing state.
Analysis of edge effects in attenuating phase-shift masks using quantitative phase imaging
Author(s):
Aamod Shanker;
Martin Sczyrba;
Brid Connolly;
Andy Neureuther;
Laura Waller
Show Abstract
Thick mask electromagnetic edge effects in attenuating phase-shift masks (ATT-PSM) are analyzed by extracting optical phase at the wafer plane from a series of through focus aerial images with 193nm light. The thick edges of an ATT-PSM can lead to phase distortions, creating asymmetric intensity contrast on either side of focus. Here we use through focus intensity images from an AIMS tool to quantitatively recover phase via the Transport of Intensity Equation (TIE). The TIE can recover the effective phase across the mask due to edge effects by analyzing the through focus image stack. We verify a previously proposed model for edge effects by adding quadrature phase boundary layers at the edges during simulation and compare the simulated through focus images with experimental data. After tuning the real and imaginary part of the boundary layer and the angle of the substrate, the simulated through focus behavior agrees with experiment, giving a measure of the edge effects. This leads to comparable quantitative phase profiles recovered at the wafer plane for simulation and experiment with the ATT-PSM. We expect that the method is applicable for the approximation of topographical effects in other types of thick masks as well.
Recovering effective amplitude and phase roughness of EUV masks
Author(s):
Rene A. Claus;
Iacopo Mochi;
Markus P. Benk;
Kenneth A. Goldberg;
Andrew R. Neureuther;
Patrick P. Naulleau
Show Abstract
Roughness in EUV masks can be induced at the substrate or during the deposition process in the multilayer, and this
roughness causes speckle when the mask is used for imaging. The 13.5-nm wavelength light penetrates into the
multilayer and interacts mostly with the roughness that is replicated through the multilayer. AFM measurements of the
substrate or surface cannot fully capture the effect of the roughness on imaging.
We present a method to extract the phase and amplitude roughness from measurements taken using an actinic
microscope. The method is non-iterative and is able to properly consider partial coherence, aberrations, and image noise.
It works by applying the small phase approximation to linearize the step of taking the intensity from electric field. We
also analyze the sensitivity of the method to various miscalibrations that might occur when applying it to measured data.
AF printability check with a full-chip 3D resist profile model
Author(s):
Cheng-En Rich Wu;
Jason Chang;
Hua Song;
James Shiely
Show Abstract
A single compact resist model capable of predicting 3D resist profile is strongly demanded for the advanced technology
nodes to avoid the potential hotspots due to imperfect resist pattern shape and its lack of resistance in the subsequent
etch process. In this work, we propose a resist 3D (R3D) compact model that takes acidz-diffusion effect into account.
The chemical reaction between acid and base along z-direction is treated as second order effect that is absorbed into the
anisotropic diffusion length as a fitting parameter. Meanwhile, the resist model in the x-y wafer plane is still kept in
general by applying the compact solution of 2D reaction-diffusion equation. In order to have the 2D contour
predictability at arbitrary resist height, calibration from entire 3D data (CDs at several heights) areconducted
simultaneously witha single cost function so that the R3D compact model is described by a common set of resist free
parameters and threshold for all resist heights. With the low energy approximation, the acid z-diffusion effect is
equivalent to a z-diffused TCC that takes the form of linear combination of pure optical TCCs sampled at discrete
image-depth which can be pre-calculated. With this benefit, the R3D compact model offers a more physical approach but
adds no runtime concern on the OPC and verification applications. The predicted resist cross-section profiles from our
test patterns are compared those computed with rigorous lithography simulator SLITHO and show very good matching
results between them. The demonstration of the AF printability check from the predicted cross-section profile at AF
indicates the success of our R3D compact model.
HSQ process development for a superior resolution and a reasonable sensitivity for an EB master-mold for nanoimprint lithography
Author(s):
Hideo Kobayashi;
Hiromasa Iyama;
Takeshi Kagatsume;
Takashi Sato;
Shuji Kishimoto;
Tsuyoshi Watanabe
Show Abstract
Half-pitch (hp) 11 to 7.5nm will be resolution requirement for 3 to 5 years later in lithography technology. In specific,
hp16nm in 2015 and hp11nm in 2019 for flash memory, bit pitch (bp) 18nm in 2015, bp15nm in 2018 for HDD patterned
media, such extremely fine patterning capability is expected.
We have been studying a positive resist ZEP520A particularly on its developers and process for the last 5 years. And, its
resolution limit is hp16nm in lines and spaces pattern and bp22nm bit patterns for patterned media, in a large and
practical patterning area (Figure 1). ZE520A is an option to pursue the resolution limit for the future. However, since it is
a positive-tone resist, dark erosion is significant between holes particularly on bp25nm and below, even when the highest
resolution developer of an alcohol and a fluoro-carbon mixture is used. ZEP holes in the nearest were not isolated but
connected due to excess dark erosion, which seemed to be caused by EB back-scattering and fogging. If a negative-tone
resist is employed, it would cause residue instead between pillars. However, the residue can be eliminated by etching
back to the bottom, and the pillars can be remained without defects (Figure 2).
Advancement of fast EUV lithography modeling/simulations and applications on evaluating different repair options for EUV mask multilayer defect
Author(s):
Ying Li;
Masaki Satake;
Danping Peng;
Peter Hu;
Linyong Pang
Show Abstract
EUV mask consists of an absorber layer and about 40-50 bi-layers of alternating molybdenum and silicon. Due to the
high profile of the absorber layer relative to wavelength, and the non-telecentric nature of EUV optics, masks 3D- and
shadowing-effects are important and must be taken into consideration. The presence of ML defect adds further
challenges to EUV simulation. The goal of our simulator is to build an empirical model specially tailored to capture such
effects by resurrect thin mask spectrum to match the results with rigorous simulation within the pupil of interests. We
will first present the mechanisms we used followed by accuracy comparison of our EUV mask model. We will evaluate
the effectiveness of different repair options for ML defect through simulation and their impact to process window.
E-beam GIDC resolution enhancement technology in practical applications
Author(s):
S. Martens;
J. Butschke;
R. Galler;
M. Krüger;
H. Sailer;
M. Sülzle
Show Abstract
For nearly all relevant applications of e-beam lithography the resolution and pattern quality requirements are
approaching or exceeding the limits of the available process. On one hand, for shrinking feature dimensions, the e-beam
proximity effect and process effects such as photo acid diffusion limit the pattern contrast and process window. On the
other hand, e-beam process related parasitic effects such as shot noise, fogging, developer loading, heating, charging, and
inhomogeneous bake introduce some significant errors. Even though e-beam tool and process tool suppliers continue to
implement new or improve current strategies to avoid or correct these effects, the amount of residual errors requires
some reasonable e-beam process window, in particular for high end applications.
For some patterns the undersize-overdose approach (SIZE) improves the pattern fidelity and process window. However,
for patterns with high fill factors this approach increases the overall deposited electron dose, which due to the increased
backscattering diminishes or even eliminates the advantages. The geometrically induced dose correction (GIDC) method
overcomes this issue by combining the SIZE concept with a short range framing technique, which reduces the deposited
dose in large filled pattern areas.
This paper provides a comparison of the standard, SIZE, and GIDC correction approaches for 1D test patterns as well as
production patterns. For a broad comparison, patterns were printed onto negative and positive chemically amplified
resists and on wafer and mask substrates using a Vistec SB352HR variable shape e-beam writer. Both wafers were also
etched.
The outcome of the study is that the SIZE and GIDC approaches often outperform the standard proximity effect
correction. For dense patterns, GIDC still provides a better pattern quality and process window, while the SIZE approach
suffers from the increased overall deposited electron dose and clearly falls behind GIDC in terms of process window.
Further it was shown that the lowering of the dose in inner areas due to GIDC does not impact the etch resistance.
Extreme ultraviolet mask defect observation using an extreme ultraviolet microscope
Author(s):
Tsuyoshi Amano;
Tsuneo Terasawa;
Hidehiro Watanabe;
Mitsunori Toyoda;
Tetsuo Harada;
Takeo Watanabe;
Hiroo Kinoshita
Show Abstract
To predict the effect of a phase defect position relative to the absorber pattern on a wafer printed image, a programmed
phase defect mask was fabricated, and was observed using an extreme ultraviolet (EUV) microscope employing EUV
light from a beam line BL3 of the New SUBARU at the University of Hyogo. The mask prepared for this work contains
programmed phase defects along with half-pitch (hp) 64 nm lines-and-spaces (L/S) absorber patterns. The phase defects
were located at different locations in reference to the absorber lines. A lithography simulator predicted that when the
distance between the line center and defect center range from 26 to 102 nm, the prepared 1.8 nm-high and 57.4 nm-wide
phase defects would cause errors of more than 10 % in wafer printed critical dimension (CD). The EUV microscope
could identify these phase defects with the EUV light intensity losses of more than 17 % in comparison to the space
pattern image intensity in the absence of the phase defect. The EUV microscope can predict the existence of the phase
defect, and its impact on a wafer printed CD even where the EUV microscope does not completely emulate the image of
the EUV scanner.
Novel fracturing algorithm to reduce shot count for curvy shape
Author(s):
Takuya Tao;
Nobuyasu Takahashi;
Masakazu Hamaji
Show Abstract
The increasing complexity of RET solutions has increased the shot count for advanced photomasks. In particular, the
introduction of the inverse lithography technique (ILT) brings a significant increase in mask complexity and
conventional fracturing algorithms generate much more shots because they are not optimized for curvilinear shapes.
Several methods have been proposed to reduce shot count for ILT photomasks. One of the stronger approaches is the
model-based fracturing, which utilizes precise dose control, shot overlaps and many other techniques. However, it
requires much more computation resource and upgrades to the EB mask writer to support user-level dose modulation
and shot overlaps.
The algorithm proposed here is not model-based but based on geometry processing, the combination of shape extraction
and direct manhattanization. Because it is not based on physical simulation, its processing speed is as fast as a
conventional fracturing algorithm. It can generate both non-overlapping shots and overlapping shots and does not require user-level dose modulation. As the result, it can be utilized for the current standard VSB mask writers.
Under-layer effects for block levels: are they under control?
Author(s):
Dongbing Shao;
Bidan Zhang;
Shayak Banerjee;
Hong Kry;
Anuja De Silva;
Ranee Kwong;
Kisup Chung;
Yea-Sen Lin;
Alan Leslie
Show Abstract
Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and under-layer aware modeling are the most promising. However, in this paper we will discuss and explain the limitation inefficiency of both methods. In addition, as more block levels are employing etching step, the under-layer dependent etch behavior that we see in some of the block levels is also discussed. All these place great challenges for block level process development. We discuss here possible solutions/improvements including: developable BARC (dBARC) thickness optimization for specific under layers; Simplified model based corrections for lith and etch. This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533
Patterning of EUVL binary etched multilayer mask
Author(s):
Kosuke Takai;
Takeharu Motokawa;
Koji Murano;
Takashi Kamo;
Naoya Hayashi
Show Abstract
Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA
(Numerical Aperture) optics for less than hp10nm node is accelerated. While studying more than 0.45 NA,
incident angle distribution of EUV light irradiation to mask becomes larger. It induces degradation of exposure
margin to form horizontal line pattern (perpendicular to EUV light direction) because of large mask 3D effect. In
order to resolve this issue, we evaluate binary etched multilayer mask structure, unlike conventional stacked
absorber structure.
As a result of improvement of binary etched multilayer mask process, hp40nm line and space pattern on mask
(hp10nm on wafer using 4X optics) is demonstrated.
This result suggests the capability of high-NA EUVL with 6inch and 4X optics with new mask structure.
Potential of mask production process for finer pattern fabrication
Author(s):
Keisuke Yagawa;
Kunihiro Ugajin;
Machiko Suenaga;
Yoshihito Kobayashi;
Takeharu Motokawa;
Kazuki Hagihara;
Masato Saito;
Masamitsu Itoh
Show Abstract
Photomask used for optical lithography has been developed for purpose of fabrication a pattern along with finer
designed rules and increase the productivity. With regard to pattern fabrication on mask, EB (Electron beam) mask
writer has been used because it has high resolution beam. But in producing photomask, minimum pattern size on mask is
hits a peak around 40nm by the resolution limit of ArF immersion systems. This value is easy to achieve by current EB
writer. So, photomask process with EB writer has gotten attached to increase turnaround time.
In next generation lithography such as EUV (Extreme ultraviolet) lithography and Nano-imprint lithography, it is
enable to fabricate finer pattern beyond the resolution limit of ArF immersion systems. Thereby the pattern on a mask
becomes finer rapidly. According to ITRS 2012, fabrication of finer patterns less than 20nm will be required on EUV
mask and on NIL template. Especially in NIL template, less than 15nm pattern will be required half a decade later. But
today’s development of EB writer is aiming to increase photomask’s productivity, so we will face a difficulty to fabricate
finer pattern in near future.
In this paper, we examined a potential of mask production process with EB writer from the view of finer pattern
fabrication performances. We succeeded to fabricate hp (half-pitch) 17nm pattern on mask plate by using VSB (Variable
Shaped Beam) type EB mask writer with CAR (Chemically Amplified Resist). This result suggests that the photomask
fabrication process has the potential for sub-20nm generation mask production.