Mask is a tool required to replicate a set of complicated IC geometries numerous times producing chips in large volume. It is absolutely crucial to achieve high quality mask in accuracy and perfection. This paper focuses on technology needs which challenge mask-making capabilities including data preparation and Optical Proximity Correction (OPC), Critical Dimension (CD) / Line Edge Roughness (LER) control, alignment and defect elimination. The impact of lithography and mask making on the design and manufacturing of new products is discussed from an end user perspective. The paper emphasizes performance, precision and perfection and the necessity of the three p’s for the continuation of Moore’s law.

A survey supported by SEMATECH and administered by David Powell Consulting was sent to semiconductor industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. 2012 marks the 11^th consecutive year for the mask industry survey. This year’s survey and reporting structure are similar to those of the previous years with minor modifications based on feedback from past years and the need to collect additional data on key topics. Categories include general mask information, mask processing, data and write time, yield and yield loss, delivery times, and maintenance and returns. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the mask industry. Results, initial observations, and key comparisons between the 2011 and 2012 survey responses are shown here, including multiple indications of a shift towards the manufacturing of higher end photomasks.

Model-Based Mask Data Preparation (MB-MDP) has been discussed in the literature for its benefits in reducing mask write times [1][2]. By being model based (i.e., simulation based), overlapping shots, per-shot dose modulation, and circular and other character projection shots are enabled. This reduces variable shaped beam (VSB) shot count for complex mask shapes, and particularly ideal ILT shapes [3]. In this paper, the authors discuss another even more important aspect of MB-MDP. MB-MDP enhances CD Uniformity (CDU) on the mask, and therefore on the wafer. Mask CDU is improved for sub-80nm features on mask through the natural increase in dose that overlapping provides, and through per-shot dose modulation. The improvement in CDU is at the cost of some write times for the less complex EUV masks with only rectangular features. But these masks do not have the basis of large write times that come from complex SRAFs. For ArF masks for the critical layers at the 20nm logic node and below, complex SRAFs are unavoidable. For these shapes, MB-MDP enhances CDU while simultaneously reducing write times. Simulated and measured comparison of conventional methodology and MB-MDP methodology are presented.

There are multiple mask parameters that can be tuned to optimize the lithographic performance of the EUV photo mask[1]. One of them is the absorber height. A reduction of the absorber height allows, for example, a higher resolution patterning on mask and reduces the OPC needed for shadowing correction[1][2][5]. Downside of a thinner absorber is the increased reflectivity which manifests itself not only in the image field (contrast loss) but also in the so called light shield area or image border. The image border is a pattern free (absorber covered) area around the die on the photo mask forming the transition area between the part on the mask that is completely shielded from the exposure light by the Reticle Masking (REMA) blades and the die. The image border accommodates the finite REMA placement accuracy and the half shadow of the REMA blades allowing close spaced die printing on the wafer. When printing a die at dense spacing, which is common practice in a production environment, the image border will overlap part of the neighboring die. This causes actinic EUV and DUV out of band light reflection from the image border exposing the overlapped die area and affecting CD and contrast at the edges of the dies. For a 44 nm thick absorber we found a CD impact of 8 nm for 32 nm dense lines[3] whereas for a 55 nm thick absorber the effect was 4 nm for 27 nm dense lines[7]. Increasing the die spacing would prevent this unwanted exposure but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable manufacturing solution. Optical Proximity Correction (OPC) using ASML Brion’s Tachyon NXE model at the edges of the die was proposed as possible solution to this problem[3]. An alternative is to create a so called Black Border: the reflectivity in the image border is reduced to a sufficiently low level by for example increasing the absorber thickness, add a special coating or replace the absorber with a low reflective material[4][5]. The most radical solution is removal of the absorber and the underlying multilayer down to the low reflective substrate, so-called multilayer etching[4][6]. In this paper we will present the effects of such a Black Border created by a multilayer etch on features and their placement on the reticle and the impact on CD of 27 nm dense lines on the wafer. By comparing the wafer CDU printed with and without Black Border we will determine how well the image border effect is mitigated by the multilayer etching.

Mask Error Enhancement Factor (MEEF) has been a standard measure of mask quality [1]. One of the key assumptions in the construction of MEEF is that mask CD uniformity is not dependent on the shape of mask feature and can be considered to be a constant for given mask process. This assumption is no longer valid for small (<100nm), curvilinear or diagonal features. In this paper we extend definition of MEEF to be valid for all mask shapes call new metric extended MEEF or eMEEF. We also demonstrate on the example of ILT features that eMEEF increases predictability of mask and wafer CD uniformity sometimes changing overall conclusion about mask/wafer manufacturability.

Cold-development is well-known for resolution enhancement on ZEP520A. Dipping a wafer in a developer solvent chilled by a freezer, such a typical method had been employed. But, it is obvious that the dip-development method has several inferiorities such as developer temperature instability, temperature inconsistency between developer and a wafer, water-condensation on drying. We then built a single wafer spin-develop tool, and established a process sequence, to solve those difficulties. And, we tried to see their effect down to -10degC over various developers. In specific, we tried to make hole patterns in hexagonal closest packing in 40nm, 35nm, 30nm, 25nm pitch, and examined holes pattern quality and resolution limit by varying setting temperature from room temperature to -10degC in the cold-development, as well as varying developer chemistry from the standard developer ZED N-50 (n-amyl acetate, 100%) to MiBK and IPA mixture which was a rinsing solvent mixture originally. We also examined the other developer (poor solvent mixture) we designed, N-50 and fluorocarbon (FC) mixture, MiBK and FC mixture, and IPA+FC mixture. This paper describes cold-development tool and technique, and its results down to minus (-) 10degC, for ZEP520A resolution enhancement to obtain 1Xnm bits (holes) in 25nm pitch to fabricate an EB master mold for Nano-Imprinting Lithography for 1Tbit/in2 bit patterned media (BPM) in HDD development and production.

An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1 dimensional GDR layout of 20nm node and below. The simulation under ArF single exposure shows 16nm node of metal layer and 12nm node of gate layer can be resolved with rectangle mask patterns. For both layers bright field exposure is used and experimentally positive and negative tone developments are applied for metal layer (island patterns) and gate layer (cut patterns) respectively. The integrated process through SADP, etching, and so on is shown. It is found that the simple pattern has lower MEEF than the complicated ones. Applying simple mask pattern MEEF can be suppressed to be 3~4 even at 16nm node. The SEM images of the masks with simple and complicated shapes show that it is difficult to reproduce the complicated pattern accurately. We prepared mask data with various complexities of patterns and evaluated the writing time of an up-to-date EB writer. The time depends on the shot counts and a typical OPC pattern takes 4 times longer time than rectangle pattern. Since the cost of writing time is around 20% of the entire cost, the saved cost from OPC pattern to rectangle pattern becomes 15%. Regarding advanced node of mask with more complicated pattern it takes further longer time and there is an impact on other technologies of inspection or process. So the saved cost becomes huge.

The pursuit of ever smaller transistors has pushed technological innovations in the field of lithography. In order to continue following the path of Moore’s law, several solutions have been proposed: EUV, e-beam and double patterning lithography. As EUV and e-beam lithography are still not ready for mass production for 20 nm and 14 nm nodes, double patterning lithography play an important role for these nodes. In this work, we focus on a Self-Aligned Double-Patterning process (SADP) which consists of depositing a spacer material on each side of a mandrel exposed during a first lithography step, dividing the pitch into two, after being transferred into the substrate, and then cutting the unwanted patterns through a second lithography exposure. In the specific case where spacers are deposited directly on the flanks of the resist, it is crucial to control its profile as it could induce final CD errors or even spacer collapse. One possibility to prevent these defects from occurring is to predict the profile of the resist at the OPc verification stage. For that, we need an empirical resist model that is able to predict such behaviour. This work is a study of a profile-aware resist model that is calibrated using both atomic force microscopy (AFM) and scanning electron microscopy (SEM) data, both taken using a focus and exposure matrix (FEM).

Achieving the required critical dimensions (CD) with the best possible uniformity (CDU) on photo-masks has always played a pivotal role in enabling chip technology. Current control strategies are based on scanning electron microscopy (SEM) based measurements implying a sparse spatial resolution on the order of ~ 10^-2 m to 10^-1 m. A higher spatial resolution could be reached with an adequate measurement sampling, however the increase in the number of measurements makes this approach in the context of a productive environment unfeasible. With the advent of more powerful defect inspection tools a significantly higher spatial resolution of 10^-4 m can be achieved by measuring also CD during the regular defect inspection. This method is not limited to the measurement of specific measurement features thus paving the way to a CD assessment of all electrically relevant mask patterns. Enabling such a CD measurement gives way to new realms of CD control. Deterministic short range CD effects which were previously interpreted as noise can be resolved and addressed by CD compensation methods. This in can lead to substantial improvements of the CD uniformity. Thus the defect inspection mediated CD control closes a substantial gap in the mask manufacturing process by allowing the control of short range CD effects which were up till now beyond the reach of regular CD SEM based control strategies. This increase in spatial resolution also counters the decrease in measurement precision due to the usage of an optical system. In this paper we present detailed results on a) the CD data generated during the inspection process, b) the analytical tools needed for relating this data to CD SEM measurement and c) how the CD inspection process enables new dimension of CD compensation within the mask manufacturing process. We find that the inspection based CD measurement generates typically around 500000 measurements with a homogeneous covering of the active mask area. In comparing the CD inspection results with CD SEM measurement on a single measurement point base we find that optical limitations of the inspection tool play a substantial role within the photon based inspection process. Once these shift are characterized and removed a correlation coefficient of 0.9 between these two CD measurement techniques is found. This finding agrees well with a signature based matching approach. Based on these findings we set up a dedicated pooling algorithm which performs on outlier removal for all CD inspections together with a data clustering according to feature specific tool induced shifts. This way tool induced shift effects can be removed and CD signature computation is enabled. A statistical model of the CD signatures which relates the mask design parameters on the relevant length scales to CD effects thus enabling the computation CD compensation maps. The compensation maps address the CD effects on various distinct length scales and we show that long and short range contributions to the CD variation are decreased. We find that the CD uniformity is improved by 25% using this novel CD compensation strategy.

This paper studies the repeatability and the reliability of CDUs from a mask inspector and their correlation with CD SEM measurements on various pattern attributes such as feature sizes, tones, and orientations. Full-mask image analysis with a mask inspector is one of potential solutions for overcoming the sampling rate limitation of a mask CD SEM. By comparing the design database with the inspected dimension, the complete CDU behavior of specific patterns can be obtained without extra work and tool time. These measurements can be mapped and averaged over various spatial lengths to determine changes in relative CDU across the mask. Eventually, success of this methodology relies on the optical system of the inspector being highly stable.

The ITRS roadmap specifies wafer overlay control as one of the major tasks for the sub 40 nm nodes in addition to CD control and defect control. Wafer overlay is strongly dependent on mask image placement error (registration errors or Reg errors)¹. The specifications for registration or mask placement accuracy are significantly tighter in some of the double patterning techniques (DPT). This puts a heavy challenge on mask manufacturers (mask shops) to comply with advanced node registration specifications. The conventional methods of feeding back the systematic registration error to the E-beam writer and re-writing the mask are becoming difficult, expensive and not sufficient for the advanced nodes especially for double pattering technologies.

Six production masks were measured on a standard registration metrology tool and the registration errors were calculated and plotted. Specially developed algorithm along with the RegC Wizard (dedicated software) was used to compute a correction lateral strain field that would minimize the registration errors. This strain field was then implemented in the photomask bulk material using an ultra short pulse laser based system. Finally the post process registration error maps were measured and the resulting residual registration error field with and without scale and orthogonal errors removal was calculated.

In this paper we present a robust process flow in the mask shop which leads up to 32% registration 3sigma improvement, bringing some out-of-spec masks into spec, utilizing the RegC^® process in the photomask periphery while leaving the exposure field optically unaffected.

The control of critical dimension uniformity (CDU), especially intra-field CDU, is an important aspect for advanced lithography, and this property must be controlled very tightly since it affects all of the exposure fields. It is well known that the influence of the mask CDU on the wafer intra-field CDU is becoming dominant because the mask error enhancement factor (MEEF) is quite high for low-k1 lithography. Additionally, the abovementioned factors impact the CDU through global (field-level) and local (grating-level) variations. In this paper, we analyze in detail CDU budgets by clarifying the impact of local CD variation. The 50-nm staggered hole features using Att-PSM showed a mask global CDU of 1.64 nm (3sigma at the mask level) and a wafer intra-field CDU of 2.30 nm, indicating that the mask global CDU was a major part of the intra-field CDU. By compensating for the contribution of the mask CD, the wafer intra-field CDU can be reduced to 0.986 nm. We analyzed the budgets of wafer intra-field CDU, which is caused by local CD variation (mask and process) and measurement noise. We determined that a primary cause of the wafer intra-field CDU after applying a mask CD correction was these local CD variations, which might disturb the proper use of dose correction for the mask CD. We demonstrated that the impact of mask local CD variation on the correction flow can be greatly reduced by averaging multiple point measurements within a small area, and therefore discuss the optimum conditions allowing for an accurate intra-field CDU determination. We also consider optimization of the CD sampling scheme in order to apply a dose correction on an exposure system to compensate for the mask CDU.

Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like “middle side lobe measurement”, evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology process layers (poly-, active-, contact-, 1X-metal-, 2X-via layers). Referring to the correlation between wafer and reticle MTT, the contribution of the reticle CD-difference to the wafer CD-difference can be used as an evaluation method for the transfer-process of different mask sites.

Critical dimension uniformity (CDU) is an important parameter for photomask and wafer manufacturing. In order to reduce long-range CD variation, compensation techniques for mask writers and scanners have been developed. Both techniques require mask CD measurements with high spatial sampling. Scanning electron microscopes (SEMs), which provide CD measurements at very high precision, cannot in practice provide the required spatial sampling due to their low speed. In contrast mask inspection systems, some of which have the ability to perform optical CD measurements with very high sampling frequencies, are an interesting alternative. In this paper we evaluate the CDU measurement results with those of a CD-SEM.

An impact of EUVL mask surface roughness on actinic inspection was studied. The background level (BGL) of an actinic inspection image is caused by the light scattered from the mask blank surface roughness. The BGL is found to be proportional to the square of the mask surface roughness measured by AFM. By using this proportionality coefficient, a global distribution of the surface roughness can be obtained at the same time while inspection a mask. On the other hand, any local variation of BGL indicates variation of the mask surface roughness at each pixel. Assuming that the roughness at a center pixel is 0.15 nm rms (SEMI standard specification) and those at the surrounding pixels are 0.1 nm rms, the signal intensity at the center pixel is found to be approximately the same as that of a 1.2 nm-high and 40 nm-wide programmed defect. In that case, CD error on a wafer image due to the reflectivity loss by the roughness is found to be not critical. This means that the local roughness should be less than 0.15 nm rms, and that the inspection system can detect such a local variation of the roughness with 100 % probability.

For the next few years, the EUV Lithography (EUVL) community must learn to find mask defects using non-actinic inspection wavelengths. The non-actinic light cannot always determine the exact nature of the defect; whether it is a particle, pattern, or defect in the multilayer. It also cannot predict which defects will induce phase errors and which will induce amplitude errors on wafer. Correlating the signature of the defect as seen by a non-actinic inspection tool and on wafer resist image will inject essential knowledge into the non-actinic defect classification. This paper will explore the correlation between EUVL mask defect signatures detected (and not detected) at both 193 nm and e-beam inspection wavelengths and waferprintable defects. The defects of interest will be characterized at mask level using atomic force microscopy (AFM) and critical dimension scanning microscopy (CDSEM). Simulations will be deployed to explain the signatures illuminated by both EUVL and 193nm exposures. This work addresses the gap between inspection sensitivity at non-actinic wavelengths and EUVL mask defect printability, and provide generalized understanding of how the two views differ.

According to the ITRS, mask defects are among the top technical challenges facing the introduction of extreme ultraviolet (EUV) lithography into production. Making a defect-free multilayer EUV mask blank is not possible today, and is unlikely to happen in the next few years. This means that EUV must work with masks having multilayer defects. The method presented here compensates effects of multilayer defects by modifying absorber patterns whose images they distort. It represents the patterns to be modified with level-set methods, providing more generality than binary pixels on a fixed grid. The level-set representation and fast model used to calculate fields at the mask have been published previously. The method has been applied with constraints to ensure that the pattern modifications are within the capability of available repair equipment, and has been shown to enlarge process windows. Although prior work focused on modifying absorber patterns, additional degrees of freedom to improve performance are available if modifications include deposition of different materials. Simulated images show potential benefits with deposited carbon. To apply the method, it is necessary to solve two sequential inverse problems. First, the defect buried in the multilayer must be modeled from available information about the top surface of the mask blank. Then the absorber modifications must be calculated from the desired image and properties of the modeled defect. Accuracy and speed of the computation meet requirements for using it to manufacture EUV masks.

According to the ITRS Roadmap [1], within a few years the EUV mask requirement for defect will be detection of defect size of less than 25 nm. Electron Beam (EB) inspection is one of the candidates to meet such a severe defect requirement. EB inspection system, Model EBEYE M※1, has been developed for EUV mask inspection. Model EBEYE M employs Projection Electron Microscope (PEM) technique and image acquisition technique to acquire image with Time Delay Integration (TDI) sensor while the stage moves continuously [2]. Therefore, Model EBEYE M has high performance in terms of sensitivity, throughput and cost. In a previous study, we showed the performance of Model EBEYE M for 2X nm in a development phase whose sensitivity in pattern inspection was around 20 nm and in particle inspection was 20 nm with throughput of 2 hours in 100 mm square [3], [4]. With regard to pattern inspection, Model EBEYE M for High Volume Manufacturing (HVM) is currently under development in the production phase. With regard to particle inspection, Model EBEYE M for 2X nm is currently progressing from the development phase to the production phase. In this paper, the particle inspection performance of Model EBEYE M for 2X nm in the production phase was evaluated. Capture rate and repeatability were used for evaluating productivity. The target set was 100% capture rate of 20 nm. 100% repeatability of 20 nm with 3 inspection runs was also set as a target. Moreover, throughput of 1 hour in 100 mm square, which was higher than for Model EBEYE M for 2X nm in the development phase, was set as a target. To meet these targets, electron optical conditions were optimized by evaluating the Signal-to-Noise Ratio (SNR). As a result, SNR of 30 nm PSL was improved 2.5 times. And the capture rate of 20 nm was improved from 21% with throughput of 2 hours to 100% with throughput of 1 hour. Moreover, the repeatability of 20 nm with 3 inspection runs was 100% with throughput of 1 hour. From these results, we confirmed that Model EBEYE M particle inspection mode could be available for EUV mask production.

EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in 2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly, small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line. In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV masks.

Reflected light inspection has been used to inspect EUVL mask which consists of multi layers and metal absorber. However, sub-wavelength half pitch patterns and reflected inspection make unprecedented phenomenon like tone inversion. These lead EUV inspection more difficult in detectability and inspectability for separating out defects and false. In this study, we report the evaluation result of inspection dependency of illumination conditions like OAI(Off-Axis Illumination), sigma and polarization for sub-20nm EUVL PDM(programmed defect mask). With inspection of sub- 20nm device mask, we finally address the inspection feasibility for sub-20nm device and the future direction of inspection technology.

With each new generation of e-beam mask writers comes the ability to write leading edge photomasks with improved patterning performance and increased throughput. However, these cutting-edge e-beam tools are often used with older generation resists, preventing the end-user from taking full advantage of the tool’s potential. The generation gap between tool and resist will become even more apparent with the commercialization of multi-beam mask writers, which are expected to be available for pilot line use around 2015. The mask industry needs resists capable of meeting the resolution, roughness, and sensitivity requirements of these advanced tools and applications.

The E-beam Resist Test Facility (ERTF) has been established to fill the need for consortium-based testing of e-beam resists for mask writing applications on advanced mask writers out to the 11nm half-pitch node and beyond. SEMATECH and the College of Nanoscale Science and Engineering (CNSE) began establishing the ERTF in early 2012 to test e-beam resist samples from commercial suppliers and university labs against the required performance metrics for each application at the target node. Operations officially began on June 12, 2012, at which time the first e-beam resist samples were tested. The ERTF uses the process and metrology infrastructure available at CNSE, including a Vistec VB300 Vectorscan e-beam tool adjusted to operate at 50kv. Initial testing results show that multiple resists already meet, or are close to meeting, the resolution requirements for mask writing at the 11nm node, but other metrics such as line width roughness still need improvement.

An overview of the ERTF and its capabilities is provided here. Tools, baseline processes, and operation strategy details are discussed, and resist testing and benchmarking results are shown. The long-term outlook for the ERTF and plans to expand capability and testing capacity, including resist testing for e-beam direct write lithography, are also discussed.

Electron beam resists develop a surface potential during exposure that can lead to image placement errors of up to several nanometers [1] and cause poor CD uniformity and image quality. To address this problem, we have formulated a conductive polymer that can be coated onto the resist. Our conductive discharge layer (CDL) is water soluble and it is easily removed during subsequent processing steps. We have established that our material has low enough resistance for full charge dissipation during e-beam exposure and have carried out extensive tests to evaluate the impact of the layer on lithographic performance. We will report these findings, which include measurements of the effect of the CDL application on resist resolution, contrast, speed, and roughness on both wafer and on mask.

As the ITRS Critical Dimension Uniformity (CDU) specification shrinks, semiconductor companies need to maintain a high yield of good wafers per day and a high performance (and hence market value) of finished products. This cannot be achieved without continuous analysis and improvement of on-product CDU as one of the main drivers for process control and optimization with better understanding of main contributors from the litho cluster: mask, process, metrology and scanner. In this paper we will demonstrate a study of mask CDU characterization and its impact on CDU Budget Breakdown (CDU BB) performed for an advanced EUV lithography with 1D and 2D feature cases. We will show that this CDU contributor is one of the main differentiators between well-known ArFi and new EUV CDU budgeting principles. We found that reticle contribution to intrafield CDU should be characterized in a specific way: mask absorber thickness fingerprints play a role comparable with reticle CDU in the total reticle part of the CDU budget. Wafer CD fingerprints, introduced by this contributor, may or may not compensate variations of mask CD’s and hence influence on total mask impact on intrafield CDU at the wafer level. This will be shown on 1D and 2D feature examples in this paper. Also mask stack reflectivity variations should be taken into account: these fingerprints have visible impact on intrafield CDs at the wafer level and should be considered as another contributor to the reticle part of EUV CDU budget. We observed also MEEF-through-field fingerprints in the studied EUV cases. Variations of MEEF may also play a role for the total intrafield CDU and may be taken into account for EUV Lithography. We characterized MEEF-through-field for the reviewed features, the results to be discussed in our paper, but further analysis of this phenomenon is required. This comprehensive approach to characterization of the mask part of EUV CDU characterization delivers an accurate and integral CDU Budget Breakdown per product/process and Litho tool. The better understanding of the entire CDU budget for advanced EUVL nodes achieved by Samsung and ASML helps to extend the limits of Moore's Law and to deliver successful implementation of smaller, faster and smarter chips in semiconductor industry.

Plasma etch challenges such as resolution enhancement, etch error reduction, and process reliability improvement are investigated in next generation phase shift photomask processes for ≤14nm technology node. Etch resolution predominantly depends on etch bias and linearity while overall process resolution is also determined by resist thickness. Several resolution enhancement techniques including thin hardmasks and new absorber materials are tested in terms of etch profile, linearity, and minimum feature printability. New approaches provide improvement on etch bias as well as good pattern fidelity for sub-resolution patterns. Reduction of etch profile errors is also critical to maintain high pattern resolution. It is found that some of etch profile distortion can be minimized by changing plasma conditions. To meet tighter process reliability requirement, we investigated a couple of advanced process control techniques in alternating phase shift mask manufacturing. Integration of real-time monitor is essential to obtain good process reliability with no degradation on defects or throughput.

As technical advances continue, the pattern size of semiconductor circuit has been shrunk. So the field of the photomask needs the processing more strictly. It is critical to the photomask which contained considerably shrank circuit and ultra high density pattern for sub-20 nm tech device, although a small defect is negligible in the conventional process. Even if some defect can be repaired, it is not satisfied with a strict pattern specification. Stricter fabrication process and pattern specification increase the manufacture cost. Furthermore, EUV photomask manufacture cost is several times expensive than the conventional photomask. Therefore the effort to decrease defects is important for the photomask fabrication process. In addition, when defects are generated, it is obviously important that the repaired patterns have better pattern reliability. In this paper, we studied about advanced processes that control and remove hard defects minutely .on ArF attenuated phase-shift mask. This study was accomplished for 4 areas. First of all, we developed advanced Mosi etch process. Defects are generated under this etch process are not fatal. The thickness of hard defects were controlled thinner under this etch process compared with conventional etch process. Secondly, we studied cleaning process that has good performance on Cr : MoSi surface and a poor hydrophilic contrast to control side effect by etch process. Thirdly, we made inspection technique for detecting thin thickness hard defects. Lastly, we researched a repair technology that is effective in hard defects of thin thickness. The performance of the repaired pattern was verified by AIMS. In this study, it is researched that control shape, properties of defects to prepare a reliable repair and improved repaired photomask pattern reliability by 30% over.

In order to meet the challenging patterning requirements of the 14 nm node, the semiconductor industry has implemented use of negative tone develop (NTD) and other tone inversion techniques on wafer to enable use of bright field masks which provide an improved lithography process window.^1,2,3 Due to e-beam write time and mask pattern fidelity requirements, the increased use of bright field masks means that mask makers must focus on improving the performance of their negative tone chemically amplified resist (NCAR) processes. In addition, the move to heavy use of bright field masks is introducing new challenges for mask makers. Bright field masks for 14 nm critical layers are required to have opaque sub-resolution assist features (SRAFs) as small as 50 nm while at the same time having across mask critical dimension uniformity (CDU) of less than 2 nm (3 sigma) to meet the 2014 ITRS targets.⁴ Achieving these specifications is particularly difficult for bright field contact and via level masks. This paper will survey the performance requirements for NCAR resists for building 14 nm critical level masks. As part of this survey, the results of current commercially available and development NCAR resists will be compared. The study will focus on key elements of the resist process pertaining to line edge roughness, pattern fidelity, minimum feature size, and critical dimension control through density with differences in resist type, sensitivity, and thickness. In addition, use of a novel flow cell test apparatus for detailed study of the develop loading performance of the NCAR resists will be described. Data showing the current capability of these NCAR materials as well as remaining 14 nm node performance gaps and issues will be presented.

Because extreme ultra violet (EUV) lithography is not ready due to technical challenges and low throughput, we are facing severe limitation for sub-20nm node patterning even though the extreme resolution enhancement technology (RET) such as the off-axis illumination and computational lithography have been used to achieve enough process window and critical dimension uniformity (CDU). As an alternative solution, double patterning technology (DPT) becomes the essential patterning scheme for the sub-20nm technology node. DPT requires the complex design rules because DPT rules need to consider layout decomposability into two masks. In order to improve CDU and to achieve both design rule simplicity and better designability, we propose two kinds of layout decomposition methodologies in this paper; 1) new mandrel decomposition of the Fin generation for better uniformity, 2) chip-level decomposition and colorless design rule of the contact to improve the scalability. Co-optimized design rules, decomposition method and process requirement enable us to obtain about 6% scaling benefits by comparison with normal DPT flow. These DPT approaches provide benefits for both process and design.

Mask Design, or the process of assembling, arranging and configuring the pattern data required to make a photomask, has many characteristics that make it appropriate for automation, including a high order of complexity, many steps in the process flow, many parameters to define, and multiple flow variants. Traditionally Mask Design has been performed in several discrete steps, each having its own set of tools, processes, data formats, and parameter sets. These include, for example, Boolean layer extraction, fill pattern generation, biasing, Optical Process Compensation (OPC), frame generation (assembling the patterns relevant to reticle and wafer alignment, automated bar code identification, masking/taping borders, process control monitors and test patterns); fracture (transforming design data formats into mask write tool formats); jobdeck generation (creating the mask write tool instruction set); and Mask Rule Checking (MRC). These separate, and often non-compatible, process flows make integration challenging. Additionally, the frame generation process typically has evolved in complexity ad hoc and is often not performed in a systematic manner that makes it easily adaptable to automation.

Since the introduction of OASIS 1.0, the OASIS file format has gradually become adopted across the semiconductor manufacturing industry for advanced technology nodes. However, within the range of possible OASIS format options, choices made during file creation can result in inefficiencies in mask data processing. This paper starts by pointing out the relation between generating OASIS files and mask data preparation runtime. We then present some strategies and methodologies on generating well-behaved OASIS files. We conclude with some comments on the OASIS standard for the future.

Mask manufacturing using E-Beam at 32 nm process node and below is failing to meet CD uniformity, CD linearity requirements due to the inherent systematic errors in the e-beam process. MPC-GC (Mask Process Correction through Geometric correction) is one technique, which moves the edges of input shapes inwardly or outwardly to compensate for the systematic errors. Since, geometric correction is done under some constraints there will always be further scope to improve the intensity profile of the mask layout to achieve better fidelity. In this paper, we discuss about an MPC flow to further enhance fidelity of the patterned shapes on the mask by adding dose correction on top of the geometric correction. We have developed NxMPC-DC tool as part of NxMDP¹ tool suite to achieve the above mentioned objective. If the input layout data is not fractured already, NxMPC-DC will use NxFracture² to carry out fracturing and then assign modulated dose values to the shots. NxMPC-DC would take the same mask process model as the one used for NxMPC-GC. Hence, in this proposed flow, the fidelity of the simulated contour would only improve beyond the MPC-GC corrected data as there would not be any conflict between the mask process models used for geometric and dose based corrections.

One step in MDP is the process of marking CD features via the jobdeck. These marks are usually further translated into specially formatted files used by optical metrology tools or CD SEM. There are various practices currently in use to accomplish the marking process, e.g.: by eye with a point and click GUI, by script using a list of known coordinates, by searching for a coordinate within a very limited neighborhood of a suspect coordinate, etc. However, all of these methods suffer from various shortcomings. They require extensive user intervention, or not all or enough marking places are found, or the coordinates that are supposed to be known are slightly off and cause mark placement scripts to fail, and so on.This paper details an approach using CATS MRCC-RPM, where a new pattern matching functionality is used to find locations suitable for mark placements. The location coordinates thus found are then passed to well known mark placing functionality to then place the marks.

When compared to conventional chrome absorber masks, electron beam patterning of EUV masks requires additional corrections to account for electron backscattering from the mirror and tantalum (Ta) based absorber layers. Current ebeam systems cannot correct for these additional backscattering effects with in-tool proximity effect correction (PEC) algorithms. Hence new methods of correction are needed, which require an implementation of the correction into the mask writer data prior to exposure. Where these corrections should be performed in the data flow between mask user and mask supplier, and who should calibrate and maintain the corrections is not clear. We present various approaches for model calibration as well as discuss the possible options for inserting mask process correction (MPC) into the mask process landscape. We report on an attempt to calibrate a correction for EUV masks using actual CD data, and an e-beam backscattering model. The resulting Point Spread Functions (PSF) were used to simulate and predict the measured CD data. We also explored the robustness of these models by varying the writing tool and mask blank characteristics. We conclude by recommending an appropriate flow for calibration and use of mask process correction and ownership of the model calibration, maintenance and the data correction processes.

Computational techniques have become increasingly important to improve resolution of optical lithography. Advanced computational lithography technologies, such as inverse lithography (ILT) and source mask optimization (SMO), are needed to print the most challenging layers, such as contact and metal, at the 20nm node and beyond. In order to deploy SMO and ILT into production, improvements and upgrades of mask manufacturing technology are required. These include writing, inspection, defect review, and repair. For example, mask plane inspection detects defect at highest resolution, but does not correlate accurately with scanner images. Aerial plane mask inspection and AIMSTM produce images close to those of a scanner, but except fot the latest AIMS-32TM, it does not have the flexibility needed to capture all the characteristics of free-form illumination. Advanced Computational Inspection and Metrology provides solutions to many of these issues.

Defect transport in development of EUVL mask blanks is an important issue for the near-term of the industry. One main issue affecting transport is how the defect may charge in the presence of plasma. In some cases, plasma may act to contain defects away from the mask surface. We show simulation results of the effect of plasma on defect transport demonstrating how the formation of plasma sheathes and a plasma potential act to confine highly negatively charged particles, such as defect particles would be.

With high NA (>0.33), and the associated higher angles of incidence on the reflective EUV mask, mask induced effects will significantly impact the overall scanner-performance. We discuss the expected effects in detail, in particular paying attention to the interaction between reflective coating and absorber on the mask, and show that there is a trade-off between image quality and mask efficiency. We show that by adjusting the demagnification of the lithography system one can recover both image quality and mask efficiency.

In electron proximity effect correction (PEC), the quality of a correction is highly dependent on the quality of the model. Therefore it is of primary importance to have a reliable methodology to extract the parameters and assess the quality of a model. Among others the model describes how the energy of the electrons spreads out in the target material (via the Point Spread Function, PSF) as well as the influence of the resist process. There are different models available in previous studies, as well as several different approaches to obtain the appropriate value for their parameters. However, those are restricted in terms of complexity, or require a prohibitive number of measurements, which is limited for a certain PSF model. In this work, we propose a straightforward approach to obtain the value of parameters of a PSF. The methodology is general enough to apply for more sophisticated models as well. It focused on improving the three steps of model calibration procedure: First, it is using a good set of calibration patterns. Secondly, it secures the optimization step and avoids falling into a local optimum. And finally the developed method provides an improved analysis of the calibration step, which allows quantifying the quality of the model as well as enabling a comparison of different models. The methodology described in the paper is implemented as specific module in a commercial tool.

As semiconductor manufacturing advances to sub-20-nm nodes, specification (size < 50 nm) for extremely fine particles on photomasks is getting more and more stringent. Photomask cleanliness, which seriously impacts manufacturing cycle time and productivity, is a serious challenge in the development of sub-20-nm node mask cleaning process. Several cleaning approaches, including the use of chemical and physical forces, are widely used in mask cleaning. In this study, we focus on the chemical force through zeta potential (ZP). ZP indicates the degree of repulsion between the particles and the mask surface (mostly quartz). In the nano-scale, stronger repulsion means easier removal of particles from mask surfaces. By controlling ZP of different chemicals from -10 mV to -150 mV in the cleaning process, the particle removal efficiency (PRE) is further improved by about 10%, especially for extremely fine particles. The ZP measurement methodology for different cleaning chemicals on quartz surface is also carried out. ZP is a helpful index in evaluating the performance of new chemicals for mask cleaning. To enhance photomask cleaning for sub-20-nm nodes, the chemical force needs to be increased because the physical force has been constrained to avoid pattern damages, especially when much smaller assistant features are commonly used to gain a greater lithography process window. How to choose a suitable cleaning approach for the next generation mask cleaning is very critical.

Better understanding of the effect of radiation on defectivity is essential to improve the stability of Ru-capped MoSi multilayer blanks. In this work, the effect of radiation exposure on the surface adhesion properties of Ru-capped MoSi multilayers was studied using optical radiation (172 nm, 532 nm, and 1064 nm). Regardless of wavelength, the surface adhesion of defects increases when exposed to radiation and scales with laser power. Changes in adhesion are compared to surface roughness. For different wavelengths, chemical modification of the surface and optical absorption of defects exhibit different contributions.

There has been a growing demand for more precise Mask CD MTT (Critical Dimension Mean to Target) control by shrinking the semiconductor device. Generally, The CD MTT is determined by patterning process such as writing, develop, and etch. But, additional CD MTT variation often occurs by cleaning process after patterning process. As a result, it is important to preserve the CD MTT for minimizing CD variation by cleaning process. The cleaning process of photomask is becoming more critical for 32nm node and below because the size of defect and SRAF pattern is in the same range. In order to achieve high first cleaning pass yields, intensive cleaning method depending on media not physical force is still essential to photomask manufacturing and these cleaning processes bring about considerable CD MTT change. Therefore, it is necessary to increase the durability of MoSi material of attenuated HTPSM (Half Tone Phase Shift Mask) by the new surface treatment method. In this study, we presented the plasma etching technique for Cr strip etch in the 2nd process of the attenuated HTPSM for minimizing CD variation by cleaning process. Diverse dry etching processes are investigated to improve the durability of the MoSi patterns. In order to evaluate the surface modification of the MoSi film, surface compositions are analyzed by XPS (X-ray Photoelectron Spectroscopy), TOF-SIMS (Time of Flight Secondary Ion Mass Spectrometry), and EELS (Electron Energy Loss Spectroscopy). The variation of CD MTT and optical properties are also evaluated by CD SEM and AIMS (Aerial Image Measurement System), respectively. The XPS analysis shows that sidewall passivation films are formed during the main etch process and then modified at the over etch step and additional in-situ O2 plasma treatment. The concentration of the MoO3 is increased when over etch step and in-situ O2 plasma treatment are added. The difference of CD shift between initial measurement and 2nd measurement after cleaning process depends on plasma etching conditions. Consequently, the increase in the peak intensity of MoO3 that is less soluble than that of MoO2 leads to preserve CD by cleaning chemicals.

Achieving mask blanks with defectivity less than 0.03 defects/cm2 at 30 nm SiO2 equivalent and above is one of the key goals for accomplishing high volume manufacturing capability for EUV lithography. Defect free blanks for lithography start from defect free substrates. Currently, defects on both LTEM and quartz substrates are dominated by pits, scratches, particles and residues left by the polishing processes used to achieve the roughness and flatness specifications of the substrates. Normally, such defects are extremely difficult to be removed and particles often leave pits as they are removed by cleaning. Standard cleaning processes relying on megasonic cavitations for particle removal are insufficient for removing such defects from substrates. It is well known that hydrofluoric acid is an etchant of fused silica (quartz) and buffered HF in different concentrations has been used in the past for cleaning quartz and silicon substrates. Ideally, an etch clean process should not increase the roughness of the substrate while cleaning. However, in the process of etching and removing the defects, the roughness of the substrates is invariably increased which is undesirable. The rate of roughness change is directly dependent on the concentration and time of exposure, which also affects the etch rate and defect removal rate. In this paper we report that a post polishing etch clean process has been developed for ULE and quartz substrates which meet the defectivity, roughness and flatness specifications for EUV blanks. We also examine the effects of substrate roughness on blank roughness, and inspection capability of substrates and blanks at different roughness levels using a defect inspection tool capable of inspecting defects down to 35 nm SiO2 equivalent size. Defect smoothing using etch clean processes have been proposed and demonstrated in the past using an anisotropic etch mechanism. This study focuses on complete removal of defects from EUV substrates, and therefore smoothing is not an issue. Multilayer blank deposition process is known to decorate defects on substrates. We use this as a technique to identify any defects that might be left on the substrate surface after etch cleaning. In most cases, we find that the substrates have low defectivity and do not affect the EUV requirements. We demonstrate that the etch clean process can be used to increase the yield of high quality ULE substrates to meet the high volume production requirements of euv masks.

As the feature size of the mask shrinks, the feature becomes more fragile and the potential for physical force damage during cleaning increases. At the same time, increased feature density of the mask makes it difficult to remove particles from congested trenches without physical force cleaning. Acoustic energy has the ability to suppress the hydro-dynamic boundary layer thereby transferring the physical force impact closer to particles trapped in the deep trenches of the mask. MegaSonic, which employs acoustic energy, is a preferred physical force cleaning technology for advanced masks. However MegaSonic can be extremely aggressive if the energy distribution is not contained within the narrowest process window available. In this paper, liquid media properties and their effect in controlling MegaSonic energy is evaluated. A chemistry is identified which provides favorable gaseous properties for controlling MegaSonic cavitation. The effect of this chemistry is characterized by measuring acoustic energy and Sonoluminscense. The phenomenon is further verified with pattern damage studies.

The Eco‐Snow Systems group of RAVE N.P., Inc. has developed a new cleaning technique to target several of the advanced and next generation mask clean challenges. This new technique, especially when combined with Eco‐Snow Systems cryogenic CO2 cleaning technology, provides several advantages over existing methods because it: 1) is solely based on dry technique without requiring additional complementary aggressive wet chemistries that degrade the mask, 2) operates at atmospheric pressure and therefore avoids expensive and complicated equipment associated with vacuum systems, 3) generates ultra‐clean reactants eliminating possible byproduct adders, 4) can be applied locally for site specific cleaning without exposing the rest of the mask or can be used to clean the entire mask, 5) removes organic as well as inorganic particulates and film contaminations, and 6) complements current techniques utilized for cleaning of advanced masks such as reduced chemistry wet cleans. In this paper, we shall present examples demonstrating the capability of this new technique for removal of pellicle glue residues and for critical removal of carbon contamination on EUV masks.

For 20 nm technology, rigorous electromagnetic field (EMF) simulation is important to predict correct lithography performance in mask development. Three mask absorbers with different total thickness and materials are used in the paper to explore the impact of thickness. The side wall profiles could also have the potential to change the process variation band (PV Band). By using rigorous EMF simulation to calculate a usual process variation band, the result shows the best focus shift changes through patterns, and leads to a CD impact caused by defocus. A new PV Band setting with side wall angle as a variable is used to show the significant impact.

Model-based Optical Proximity Correction (OPC) is widely used in advanced lithography processes. The OPC model contains an empirical part, which is calibrated by fitting the model with data from test patterns. Therefore, the success of the OPC model strongly relies on a test pattern sampling method. This paper presents a new automatic sampling method for OPC model calibration, using centroid-based clustering in a hybrid space: the direct sum of geometrical sensitivity space and image parameter space. This approach is applied to an example system in order to investigate the minimum size of a sampling set, so that the resulting calibrated model has the error comparable to that of the model built with a larger sampling set. The proposed sampling algorithm is verified for the case of a contact layer of the most recent logic device. Particularly, test patterns with both 1D and 2D geometries are automatically sampled from the layer and then measured at the wafer level. The subsequent model built using this set of test patterns provides high prediction accuracy.

LELE double patterning technology is being deployed for 20nm production. With the use of two separate litho-etch steps in the lithography of one layer, LELE doubles the pitch achievable in the tradional single litho-etch step. However, as wavelength of the light used in each litho-etch step is as before, the need for OPC remains, and is even more crucial.

In this paper, we will present the needs and mechanisms for simultaneous OPC for both masks, the extra freedom avaliable in DP OPC, and the extra consideration needed in developing LELE OPC recipe such as SRAF insertion. biasing.

As a result of repeated cleanings and exposure effects such as chrome migration or MoSi oxidation some photomasks in the semiconductor fabs exhibit changes in critical dimension uniformity (CDU) over time. Detecting these effects in a timely manner allows for better risk management and process control in manufacturing. By monitoring changes in film reflectance intensity due to the various degradation mechanisms it is possible to predict when they may begin to influence across chip line width variations (ACLV). By accurately predicting the magnitude of these changes it is possible for semiconductor manufacturers to replace the photomasks before they have an impact on yields. This paper looks at possible causes of CDU variations on reticles during use and how this information might be used to improve or monitor reticle CDU changes over time.

Haze formation on the patterned metal surface of reticles is a known problem for IC manufacturers that can impact device yield and increase operational costs due to the need for more frequent cleaning of the reticles. Storage of reticles in an ultraclean environment can reduce haze formation and reduce operational costs. We examined the contamination levels of a new type of reticle stocker that stores reticles in microenvironments which are continuously purged with extreme clean dry air (XCDA). Each microenvironment consists of twelve vertically stacked reticle storage slots which can be opened at any slot. The design of the microenvironment includes an XCDA supply that provides a homogeneous horizontal flow of XCDA between the reticles. Figure 1. Reduction of contamination levels inside the storage microenvironment as a function of XCDA flow rate. As shown in Fig. 1, continuous XCDA purge reduces the contaminant levels inside the microenvironment. The amount of reduction depends on the XCDA purge flow rate and the chemical species. Volatile organic substances can be reduced by more than two orders of magnitude. Humidity is reduced less because the plastic material of the storage microenvironment incorporates water in its matrix and can release moisture to the extremely dry atmosphere. Chemical filters applied to mini- or microenvironments typically reduce the contaminant levels only by 95-99% and do not reduce the humidity. To pick and place reticles, the reticle storage microenvironment must be opened. The transient contaminant levels inside the empty microenvironment show an increase at the moment when the microenvironment is opened. Under the given conditions, the microenvironment returns to equilibrium levels with a time constant of 105 seconds (see Fig. 2). Similar dynamic response was measured for IPA and acetone. Figure 2. Transient humidity when the storage microenvironment was opened for reticle handling. The impact of handling on reticles stored inside the microenvironment was found to depend on several factors. When the microenvironment is filled with reticles, the horizontal XCDA flow purges a smaller volume of air and therefore re-establishes the equilibrium condition more quickly than in an empty microenvironment. The recovery time constant of a filled microenvironment was measured as only 20 seconds compared with 105 seconds for an empty microenvironment. Reticles below and above the opened slot were found to act as "shield" for the rest of the microenvironment and reduce the impact of opening the microenvironment. Moreover, the impact depends on the distance between the storage position and the opened slot: the larger the distance the smaller the impact. The last two factors reduced the peak value in the transient humidity measurements to one third when the microenvironment was opened 5 slots away from the storage slot. GLOBALFOUNDRIES Fab 1 used the results of these studies to optimize the parameter settings for its reticle storage. The reticles are stored in microenvironments which utilize extremely low contaminant levels. Based on the current utilization profile of the reticle stocker, the storage microenvironments are opened for approximately 0.01% of the time the reticles are stored in the stocker. Even in the short opening times the contamination levels do not exceed the ITRS requirements for reticle storage (see ITRS 2011, YE3 limits for reticle pod interior, supporting ≤ 28 nm technology nodes).

To enhance global CDU attained by our EB mask writer EBM-8000, we examined extending the loading effect correction (LEC) function to treat plural of loading effects, for instance, develop and etch loading. Here, we propose a LEC dose composition method, assuming uniquely-defined relation between amount of dose modulation and resultant CD change. Sets of LEC dose maps (pairs of base dose maps and proximity backscattering ratio maps) are converted to sets of CD change maps which are summarized to create a set of dose maps used for writing. This paper describes the correction procedure and possible applications of the method.

Printing results as achieved with a proof-of-concept 50keV electron multi-beam mask exposure tool (eMET POC) within 1cm² specification write fields on 6” mask blanks are reported. The eMET POC consists of a column with 200x reduction optics. Inserted into the column is a CMOS addressable (max. 12.8 Gbits/s) blanking device, providing 256k (k=1024) programmable beams within 82μm x 82μm beam array fields. Multi-beam exposures are done on 150mm Si monitor wafers and 6” mask blanks moved at constant speed (up to 1.23 mm/s) with a high precision (1nm 1sigma) laser-interferometer controlled stage in stripes of 82 μm width (2μm overlap between adjacent stripes). Detailed evaluation results with respect to resolution, CDU, linearity, distortion control and stability, as well as OPC and ILT exposure capabilities are presented. Exposures on 0.1nm address grid are demonstrated.

Dose Margin has always been known to be a critical factor in mask making. This paper describes why the issue is far more critical than ever before with the 20-nm logic node and beyond using ArF Immersion lithography. Model-Based Mask Data Preparation (MB-MDP) had been presented [references] to show shot count improvements for these complex masks. This paper describes that MBMDP also improves the dose margin. The improvement predicted with theoretical simulation with D2S is confirmed by the results of real mask written by JBX-3200MV (JEOL) by HOYA.

Maskless electron beam lithography has the potential to extend semiconductor manufacturing to the sub-10 nm technology node. KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL) for high-volume 10 nm logic (16 nm HP). This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Lithography (HVL) at the 2X and 1X nm nodes. In this paper we introduce the Digital Pattern Generator (DPG) with integrated CMOS and MEMs lenslets that was manufactured at TSMC and IMEC. For REBL, the DPG is integrated to KLA-Tencor pattern generating software that can be programmed to produce complex, gray-scaled lithography patterns. Additionally, we show printing results for a range of interesting lithography patterns using Time Domain Imaging (TDI).

Previously, KLA-Tencor reported on the development of a Reflective Electron Beam Lithography (REBL) tool for maskless lithography at and below the 22 nm technology node¹. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. Ebeam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVL.

Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore’s law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes.

Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer.

Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.

Mask defectivity is often cited as a barrier to EUVL manufacturing, falling just behind low source power. Mask defectivity is a combination of intrinsic blank defects, defects introduced during the mask fabrication and defects introduced during the use of the mask in the EUV exposure tool. This paper works towards minimizing the printing impact of blank defects so that the final EUVL mask can achieve a lower defectivity. Multilayer defects can be created by a step or scratch as shallow as 1nm in the substrate. These small defects create coherent disruptions in the multilayer that can generate significant variations in mask reflectivity and induce clearly-defined, printable defects. If the optical properties of the defect can be well understood, nanomachining repair processes can be deployed to fix these defects. The purpose of this work is to develop new nanomachining repair processes and approaches that can repair complex EUVL mask defects by targeted removal of the EUVL mask materials. The first phase of this work uses nanomachining to create artificial phase defects of different types and sizes for both printability evaluation and benchmarking with simulation. Experimental results validate the concept, showing a reasonable match between imaging with the LBNL Actinic Inspection Tool (AIT) and simulation of the mask topography measured by AFM. Once the printability of various nanomachined structures is understood, the second phase of the work aims to optimize the process to repair real EUVL mask defects with surrounding absorber patterns.

The EUV-photomask is used as mirror and no longer as transmissive device. In order to yield defect-free reticles, repair capability is required for defects in the absorber and for defects in the mirror. Defects can propagate between the EUV mask layers, which makes the detection and the repair complex or impossible if conventional methods are used. In this paper we give an overview of the different defect types. We discuss the EUV repair requirements including SEM-invisible multilayer defects and blank defects, and demonstrate e-beam repair performance. The repairs are qualified by SEM, AFM and wafer prints. Furthermore a new repair strategy involving in-situ AFM is introduced. This new strategy is applied on natural defects and the repair quality is verified using state of the art EUV wafer printing technology.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The limitation of 1.35 NA posed by water-based lithography has led to the application of various resolution enhancement techniques (RET), for example, use of strong phase-shifting masks, aggressive OPC and sub-resolution assist features, customized illuminators, etc. The adoption of these RET techniques combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for a mask inspection engineer. Inspecting masks under their actinic-aerial image conditions would detect defects that are more likely to print under those exposure conditions. However, this also makes reviewing such defects in their low-contrast aerial images very challenging. On the other hand, inspecting masks under higher resolution or mask-plane inspection optics would allow for better viewing of defects post-inspection. However, such inspections generally would also detect many more defects, including critical and nuisance, thereby making it difficult to judge which are of real concern for printability on wafer. Hence, a comprehensive approach is needed in handling defects both post-aerial and post-high resolution inspections. This paper focuses on review of defects post high resolution or mask-plane inspections, especially in the wafer-fab environment. A later paper will focus on review of defects post aerial-image inspections.

To overcome the challenge of particle removal without pattern damage, it is important to control and optimize the physical force impact into a narrow energy distribution regime. This can be achieved by gaining in-depth knowledge into the fundamentals of physical cleaning methods as well as the process parameters affecting the performance of these systems. Droplet Spray is considered to be a gentle physical force technique. The droplet size and droplet velocity defines the kinetic energy of a droplet which transfers momentum and pressure onto the substrate surface resulting into particle removal or pattern damage. Droplet pressure is directly influenced by gas and liquid flow rate as well as nozzle design (orifice size, etc.) and process parameters like nozzle distance and scan speed across the substrate surface. In this paper, effect of process and hardware parameters on droplet pressure transfer are presented and related to kinetic energy and momentum as calculated from droplet velocity and size. Effect of these process parameters is also studied on pattern damage and particle removal efficiency. Distance, nozzle hardware, gas and liquid flow rate are found to be independent process parameters which show specific effects on nozzle performance; therefore they all are optimized individually.

Because EUV masks lack of a pellicle, they are prone to particle contamination and must be cleaned frequently. Despite the relatively good resistance of the TaN absorber lines to pattern damage by megasonic cleaning, the Ru cap can be easily damaged by it. We demonstrate that the type and concentration of the dissolved gas are critical factors in determining the cavitation that eventually introduces pits on the surface of Ru-capped multilayer films. In particular, oxygen creates many more pits than CO2 under similar conditions. In this paper, we present the results of SEMATECH’s extensive experimental studies of pit creation on Ru-capped multilayer EUV blanks by megasonics as a function of acoustic field power, gas type and concentration in ultra-pure water, and chemicals during sonication.

Extreme ultraviolet lithography (EUVL) is a leading candidate for next generation lithography (NGL). At 11nm technology node, the size of the minimum printable multi-layer (ML) mask defect is as small as 20nm. As a result, it is extremely difficult to produce defect-free ML mask blanks. Instead, by allowing a certain number of printable defects on the blank, the EUVL cost of ownership can be tremendously reduced. However, those printable blank defects must be mitigated later in the mask fabrication process in order not to sacrifice yield. One effective defect mitigation approach is to cover the defects by device patterns, such that the defects will no longer be printable. However, there can be billions of device patterns in one single layer which have to be shifted together within a certain margin due to the exposure alignment requirement. Thus an efficient way to cover all defects simultaneously via global device pattern shifting is sorely needed. In addition, it is very difficult to measure the position of each defect accurately with the current blank inspection tool, so the defect position inaccuracy has to be taken into consideration at the same time. This paper formulates the blank defect coverage problem into a rectilinear polygon shrinking and intersection problem and develops a highly efficient algorithm whose time complexity is linear with respect to the density of device patterns. In addition, within the shift margin there are usually multiple positions to locate a layout on a defective blank where all defects are simultaneously covered by the device patterns; our algorithm is able to report the optimal layout location with the maximum tolerance for the inspection inaccuracy.

This paper presents the extension of the well-established rigorous electromagnetic field (EMF) solver Waveguide for the efficient and fully rigorous simulation of patterned extreme ultraviolet (EUV) masks with multilayer defects using a rigorously computed multilayer defect data base combined with on demand computed absorber structures. Typical computation times are in the range of seconds up to a few minutes. The new simulation approach will be presented. Selected simulation examples and a defect repair example demonstrate the functionality and the capability to perform fast, highly accurate and flexible EUV multilayer defect computations.

For Extreme Ultra-Violet Lithography (EUVL), fabrication of defect free multi-layered (ML) mask blanks is one of the difficult challenges. ML defects come from substrate defects and adders during ML coating, cannot be removed, and are called as phase defect.

If we can accept ML blanks with certain number of phase defects, the blank yield will be drastically up. In order to use such blanks, the phase defects need to be identified and located during ML blank defect inspection before absorber patterning. To locate phase defects on the blanks accurately and precisely, Fiducial Marks (FM) on ML blanks are needed for mask alignment and defect location information. The proposed requirement of defect location accuracy is less than 10 nm [1].

In addition to the previous study for which FMs were etched by Focused Ion Beam (FIB) [2], we fabricated FMs by resist exposure by E-Beam (EB) writer and etching process, and inspected FMs with EUV Actinic full-field mask Blank Inspection (ABI) prototype developed at MIRAI-Selete, EB writer and other mask inspection tools. Then we estimated FM registration accuracy for several line widths and depths.

In this paper, we will present the result of feasibility study on the requirements of FM on EUVL mask by experiments to establish the phase defect mitigation method. And the optimum ranges of FM line width, depth, and fabrication method on EUVL mask based on above results are 3 - 5 m line width, not less than 100 nm depth FM etched into ML respectively.

Mask inspection is an outstanding challenge for Extreme Ultra-Violet Lithography (EUVL). The purpose of this investigation is to compare imaging characteristics of ArF and KrF inspection sources to imaging characteristics using a source at the Lyman-alpha line of Hydrogen at 121.6nm (HLA). HLA provides a raw resolution improvement of 37% to ArF and 51% to KrF, based on proportional wavelength scaling. The HLA wavelength is in an atmospheric transmission window, so a vacuum environment is not required. Our comparison uses rigorous vector imaging techniques to simulate partially coherent illumination schemes and reasonably accurate mask material properties and dimensions. Contrast is evaluated for representative spatial frequencies. Imaging and detection of defects are also considered with NILS and MEEF. The goal is high throughput inspection with maximum resolution, contrast, and sensitivity.

It is anticipated that throughout the process development phase for the introduction of EUV lithography, defect free substrates won’t be available – even at the manufacturing stage, non-repairable defects may still be present. We investigate EDA-based approaches for defect avoidance, such as reticle floor planning, shifting the entire reticle field (pattern shift), pattern shift in addition to layout classification (smart shift), and defect repair in the data prior to mask write. This investigation is followed by an assessment of the complexity and impact on the mask manufacturing process of the various approaches. We then explore the results of experiments run using a software solution developed on the Calibre platform for EUV defect avoidance on various mask blanks, analyzing its effectiveness and performance.

Backside defects are out of focus during wafer exposure by the mask thickness and cannot be directly imaged on wafer. However, backside defects will induce transmission variation during wafer exposure. When the size of backside defect is larger than 200 microns, the shadow of such particles will locally change the illumination conditions of the mask patterns and may result in a long range critical dimension (CD) variation on wafer depending on numerical aperture (NA) and pupil shape. Backside defects will affect both wafer CD and critical dimension uniformity (CDU), especially for two-dimensional (2D) structures. This paper focuses on the printability of backside defects on contact layer using annular and quadrupole illumination mode, as well as using different reticle blank material. It also targets for gaining better understanding of critical sizes of backside defects on contact layer for different reticle blanks. We have designed and manufactured two test reticles with repeating patterns of 28nm and 40nm technology node of contact layers. Programmed chrome defects of varying size are placed on the backside opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD. The test mask was printed on a bare silicon wafer, and the printed features measured for size by spatial sampling. We have investigated two contact layers with different illumination conditions. One is advance binary with single exposure; another is phase shift mask with double exposure. Wafer CD variation for different backside defect sizes are demonstrated for the two contact layers. The comparison between backside defect size with inter-field and intra-field CD variation is also discussed.

The mask inspection and defect classification is a crucial part of mask preparation technology and consumes a significant amount of mask preparation time. As the patterns on a mask become smaller and more complex, the need for a highly precise mask inspection system with high detection sensitivity becomes greater. However, due to the high sensitivity, in addition to the detection of smaller defects on finer geometries, the inspection machine could report large number of false defects. The total number of defects becomes significantly high and the manual classification of these defects, where the operator should review each of the defects and classify them, may take huge amount of time. Apart from false defects, many of the very small real defects may not print on the wafer and user needs to spend time on classifying them as well. Also, sometimes, manual classification done by different operators may not be consistent. So, need for an automatic, consistent and fast classification tool becomes more acute in more advanced nodes. Automatic Defect Classification tool (NxADC) which is in advanced stage of development as part of NxDAT1, can automatically classify defects accurately and consistently in very less amount of time, compared to a human operator. Amongst the prospective defects as detected by the Mask Inspection System, NxADC identifies several types of false defects such as false defects due to registration error, false defects due to problems with CCD, noise, etc. It is also able to automatically classify real defects such as, pin-dot, pin-hole, clear extension, multiple-edges opaque, missing chrome, chrome-over-MoSi, etc. We faced a large set of algorithmic challenges during the course of the development of our NxADC tool. These include selecting the appropriate image alignment algorithm to detect registration errors (especially when there are sub-pixel registration errors or misalignment in repetitive patterns such as line space), differentiating noise from very small real defects, registering grey level defect images with layout data base, automatically finding out maximum critical dimension (CD) variation for defective patterns (where patterns could have Manhattan as well as all angle edges), etc. This paper discusses about many such key issues and suggests strategies to address some of them based upon our experience while developing the NxADC and evaluating it on production mask defects.

Ever imagine life without a search engine? Now imagine if there was a search engine for reticle defects that allowed you to search, trend size, and relate defects on any reticle from any inspection tool, in any of your interconnected fabs, at any time with a performance similar to a typical Google search. What would you do with it? With EUV upon us and the uncertainly involving EUV defect classification, it is important that the process engineers have access to as much defect data as possible. Here such data is made available on Windows based PCs and tablet computers.

In previous conferences the status of the AIMS™ EUV project has been presented in which the basic layout scheme and preliminary design have been shown along with the targeted performance specification levels to be met. Presently the final design milestone of the project has been successfully completed and assembly of the prototype tool is underway. The final design concept will be presented along with the current status of the tool and simulated performance data.

Double patterning presents itself as one of the best candidates for pushing the limits of ArF lithography to 20nm technology node and below. It has the advantage of theoretically decreasing the minimum resolvable pitch by a factor of two, or the improvement of the process window by relaxing the lithographic conditions. Double patterning though has its own complexities. Not only sophisticated algorithms are required to simply split the design into two exposures, but these two exposures have to comply with the design manual rules. The number and the complexity of these rules tend to increase for more compact designs in terms of minimum CD and layout topology which in turns increase the coding burden on engineers to let the splitting code be aware of such numerous rules. In this context, we are proposing a new double patterning flow. It will be shown how the splitting can be done while taking into account numerous design rules. And finally, rules prioritization will be discussed in order to avoid conflicts between them.

To continue scaling the circuit features down, Double Patterning (DP) technology is needed in 22nm technologies and lower. DP requires decomposing the layout features into two masks for pitch relaxation, such that the spacing between any two features on each mask is greater than the minimum allowed mask spacing. The relaxed pitches of each mask are then processed on two separate exposure steps. In many cases, post-layout decomposition fails to decompose the layout into two masks due to the presence of conflicts. Post-layout decomposition of a standard cells block can result in native conflicts inside the cells (internal conflict), or native conflicts on the boundary between two cells (boundary conflict). Resolving native conflicts requires a redesign and/or multiple iterations for the placement and routing phases to get a clean decomposition. Therefore, DP compliance must be considered in earlier phases, before getting the final placed cell block. The main focus of this paper is generating a library of decomposed standard cells to be used in a DP-aware placer. This library should contain all possible decompositions for each standard cell, i.e., these decompositions consider all possible combinations of boundary conditions. However, the large number of combinations of boundary conditions for each standard cell will significantly increase the processing time and effort required to obtain all possible decompositions. Therefore, an efficient methodology is required to reduce this large number of combinations. In this paper, three different reduction methodologies are proposed to reduce the number of different combinations processed to get the decomposed library. Experimental results show a significant reduction in the number of combinations and decompositions needed for the library processing. To generate and verify the proposed flow and methodologies, a prototype for a placement-aware DP-ready cell-library is developed with an optimized number of cell views.

This paper provides DFM solutions on yield improvement based on a foundry’s perspective. We have created a novel work flow for efficient yield enhancement at different stages throughout the process of design-to-silicon. In the design environment, other than conforming to the conventional design rule manual, we may guide the designer to employ the well-characterized regular logic bricks that are built from process validated hotspots. Later, after design sign-off, layout manipulation or layout retargeting are implemented during the mask preparation stage to enlarge the process window when faced with a diversity of layout patterns in the design. At the same time, two crucial methods, namely layout analysis and layout comparison, are used to capture all layout related detractors. The first method can identify the process sensitive hotspots, which will be highlighted and anchored as process limiters during the patterning process. Layout comparison can be an efficient way to narrow down the yield roadblocks by debugging the yield loss on similar process and design styles. Another smart solution is creating customized process control monitoring structures (PCM), which are extracted from previous yield ramping lessons and process hotspots. These PCMs will be dropped into scribe lane of production tapeouts and serve as pioneer testkeys for the initial production ramp up.

Mask data preparation (MDP) typically involves multiple flows, sometimes consisting of many steps to ensure that the data is properly written on the mask. This may include multiple inputs, transformations (scaling, orientation, etc.), and processing (layer extraction, sizing, Boolean operations, data filtering). Many MDP techniques currently in practice require multiple passes through the input data and/or multiple file I/O steps to achieve these goals. This paper details an approach which efficiently process the data, resulting in minimal I/O and greatly improved turnaround times (TAT). This approach takes advanced processing algorithms and adapts them to produce efficient and reliable data flow. In tandem with this processing flow, an internal jobdeck mapping approach, transparent to the user, allows an essentially unlimited number of pattern inputs to be handled in a single pass, resulting in increased flexibility and ease of use.

Transformations and processing operations are critical to MDP. Transformations such as scaling, reverse tone and orientation, along with processing including sizing, Boolean operations and data filtering are key parts of this. These techniques are often employed in sequence and/or in parallel in a complex functional chain. While transformations typically are done "up front" when the data is input, processing is less straightforward, involving multiple reads and writes to handle the more intricate functionality and also the collection of input patterns which may be required to produce the data that comprises a single mask.

The approach detailed in this paper consists of two complementary techniques: efficient MDP flow and jobdeck mapping. Efficient MDP flow is achieved by pipelining the output of each step to the input of the subsequent step. Rather than writing the output of a particular processing step to file and then reading it in to the following step, the pipelining or chaining of the steps results in an efficient flow with minimal file I/O.

The efficient MDP flow is enhanced by a technique called jobdeck mapping which allows in essence an unlimited number of pattern inputs by taking each transformed pattern and including it in an input jobdeck. Making use of established jobdeck handling capabilities, the user-selected input pattern/transformation combinations are mapped to an input jobdeck which is processed by the advanced flow, allowing great flexibility and user control of the process.

Double Patterning (DP) is still the most viable lithography option for sub-22nm nodes. The two main types of DP are Litho Etch Litho Etch (LELE) and Self-Aligned Double Patterning (SADP). Of those two, SADP has the advantage of lower sensitivity to overlay error. However SADP imposes a lot of restrictions on the layout. One of the ways to do SADP decomposition is to use an LELE decomposer while prohibiting stitches, and to generate mandrel and trim masks from LELE masks using some Boolean characterization equations. In this paper, we propose an SADP decomposer based on an LELE decomposer that is used to decide which target polygons are mandrel and which are non-mandrel. However the core of the LELE decomposer has been made SADP-aware, such that it gives less priority to pairs of polygons separated by spacing values that are prohibited by SADP. Then, a mandrel and trim masks generator uses the LELE decomposer output and produces the final mandrel and trim masks. Experimental results show that adding SADPawareness to the core of the decomposer has decreased the average number of coloring conflicts by 38%. The proposed decomposer is faster than the previous SADP decomposition approaches that use Integer Linear Programming (ILP) and Satisfiability (SAT).

To evaluate photomask quality, the current method uses spatial imaging by optical inspection tools. This technique at 1Xnm node has a resolution limit because small defects will be difficult to extract. To simulate the mask error-enhancement factor (MEEF) influence for aggressive OPC in 1Xnm node, wide FOV contour data and tone information are derived from high precision SEM images. For this purpose we have developed a new contour data extraction algorithm with sub-nanometer accuracy resulting in a wide Field of View (FOV) SEM image: (for example, more than 10um x 10um square). We evaluated MEEF influence of high-end photomask pattern using the wide FOV contour data of "E3630 MVM-SEM^TM" and lithography simulator "TrueMask^TM DS" of D2S, Inc. As a result, we can detect the "invisible defect" as the MEEF influence using the wide FOV contour data and lithography simulator.

The Electron Optical System (EOS) is designed for the electron beam machine employing a vector scanned variable shaped beam (VSB) with the deflector. Most VSB systems utilize multi stage deflection architecture to obtain a high precision and a high-speed deflection at the same time. Many companies use the VSB mask writer and they have a lot of experiences about Image Placement (IP) error suffering from contaminated EOS deflector. And also most of VSB mask writer users are having already this error. In order to use old VSB mask writer, we introduce the method how to compensate unexpected IP error from VSB mask writer. There are two methods to improve this error due to contaminated deflector. The one is the usage of 2nd stage grid correction in addition to the original stage grid. And the other is the usage of uncontaminated area in the deflector. According to the results of this paper, 30% of IP error can be reduced by 2nd stage grid correction and the change of deflection area in deflector. It is the effective method to reduce the deflector error at the VSB mask writer. And it can be the one of the solution for the long-term production of photomask.

Electron multi-beam mask writers address the challenge of long mask write times for increasingly complex masks. The writing speed of the IMS multi-beam mask writer under consideration here depends on the data path and blanking device speed provided for exposing the patterns. It was initially believed that the maximum dose required for exposing the patterns could also be a limiting factor. We present a proximity effect correction scheme that improves image quality (compared to a dose-only correction) and allows for a maximum dose limit. We test this scheme with and without maximum dose limit, and compare the achieved image quality against that for a dose-only correction. The results of this simulation study are verified by comparing top down SEM images of resist structures from exposures using the different corrections.

Character projection (CP) exposure has some advantages compared with variable shaped beam (VSB) system; (1) shot count reduction by printing complex patterns in one e-beam shot, (2) high pattern fidelity by using CP stencil. In this paper we address another advantage of CP exposure, namely the shape correction of CP stencil for cancelling the pattern deformation on the substrate. The deformation of CP printings is decomposed into some elements. They are CP stencil manufacturing error, proximity effect, beam blur of the e-beam writer and resist blur. The element caused by beam blur of e-beam writer can be predicted by measuring the total beam blur obtained from CD-dose curves. The pattern deformation was corrected by applying the shape correction software system of D2S. The corrected CP stencil of 22nm-node standard cell was manufactured and standard cell patterns were exposed. We confirmed that our shape correction method is the appropriate solution for correcting deformation issue of CP openings. The beam blur required for the 1X nm dimensions was predicted from the exposure results of standard cell patterns with applying shape correction and CD-dose curves. We simulated the optical system to realize the required beam blur. As a result, the next electron optics has the resolving capability of 1X nm dimension.

The line-edge roughness (LER) of a photomask image has a measurable impact on the corresponding printed wafer LER. This impact increases as wafer exposures move from 193nm DUV to 13.5nm EUV wavelengths since the imaging tool is a low-pass filter with EUV passing more spatial frequencies. Even the high frequency mask LER may impact the wafer image by lowering its image log-slope (ILS). Studying the magnitude and frequency content of mask LER is a first step to reducing the wafer LER. The next step is to determine which components of mask line roughness actually contribute to the wafer line roughness. Order is imposed on this study by fabricating programmed LER patterns on an EUV mask to introduce controlled variations in LER spatial frequency and magnitude. More specifically, line-width roughness (LWR), LER and power spectral density (PSD) are extracted from 64nm and 90nm (1X) pitch lines on a programmed LER EUV photomask. The same mask is then exposed on the ASML EUV Alpha Demo Tool (ADT) at best focus and dose. Three chemically amplified EUV photoresists are evaluated using the programmed LER photomask through PSD and LWR comparisons and the highest performance resist is used for a comprehensive LER transfer analysis. Wafer LWR is extracted from 64nm and 90nm pitch lines and correlated back to the base mask patterns revealing an empirical LWR transfer function (LTF). Finally, the study is extended to 45nm (1X) pitch lines by deploying a pupil filter on the ADT to explore the effect on LWR as the feature sizes shrink.

We have developed a highly integrated methodology for patterning Extreme Ultraviolet (EUV) mask, which has been highlighted for the lithography technique at the 14nm half-pitch generation and beyond. The EUV mask is characterized as a reflective-type mask which is completely different compared with conventional transparent-type of photo mask. And it requires not only patterning of absorber layer without damaging the underlying multi reflective layers (40 Si/Mo layers) but also etching multi reflective layers. In this case, the dry etch process has generally faced technical challenges such as the difficulties in CD control, etch damage to quartz substrate and low selectivity to the mask resist. Shibaura Mechatronics ARESTM mask etch system and its optimized etch process has already achieved the maximal etch performance at patterning two-layered absorber. And in this study, our process technologies of multi reflective layers will be evaluated by means of optimal combination of process gases and our optimized plasma produced by certain source power and bias power. When our ARES™ is used for multilayer etching, the user can choose to etch the absorber layer at the same time or etch only the multilayer.

Dummy pattern fill is added to a layout of a reticle for the purpose of raising the pattern-density of specific regions. The pattern-density has also an influence on different process-steps which were performed when manufacturing a reticle (e.g. proximity effect of electron beam exposure process, developer, and etch-processes). Although the reticle processes are set up to compensate the influence of the pattern density, dummy pattern can have an influence onto the reticle CD. When the isolated features become “nested” by insertion of dummy pattern, the reticle CD variation is even larger because nested features exacerbate the proximity effect of an electron beam. Another reason is that the etch ratio as well as the develop dynamics during the reticle manufacturing process are slightly dependent on the local pattern-density of pattern. With different dummy pattern around the main feature, the final reticle CD will be changed. Wafer CD of main feature is also dependant on the surrounding patterns which will induce different boundary conditions for wafer exposure.

We have investigated three manufacturing sites for a 28nm first-metal layer reticle. Two of them were manufactured with a comparable process using the same advanced reticle binary blank material. For the third site a different reticle blank material with a relatively thin absorber layer thickness was used which was made with a comparable reticle process. The optical proximity correction (OPC) test patterns were designed with two different dummy patterns. The CD differences of the three reticles will be demonstrated for different dummy pattern and will be discussed individually. All three reticles have been exposed and the respective wafer critical dimension through pitch (CDTP) and linearity performance is demonstrated. Also the line-end performance for two dimensional (2D) structures is shown for the three sites of the reticle. The wafer CD difference for CDTP, linearity, and 2D structures are also discussed.

Microfabrication of high-resolution micro-optic devices requires <1/8λ (~60nm) precision both vertically and horizontally. More critical is the creation of 256-level grayscale masks to create sufficient vertical precision in the photoresist. Grayscale bimetallic photomasks are bi-layer thermal resists of Bismuth-on-Indium or Tin-on-Indium become controllably transparent by varying laser power thermally producing alloy oxide ranging ~3OD (unexposed) to <0.22OD (fully exposed). Previously, a direct-write multi-line CW Argon-ion laser writing system with feedbackcontrolled Gaussian beam achieved 256-level grayscale masks. The feedback system effectively reduced the average gray-level error from ±4.2 gray-levels in an open-loop approach to ±0.3 gray-levels in a closed-loop approach. Remaining gray-level errors were due to the Gaussian beam profile creating variations in gray-levels. Preliminary results show that a beam shaper creating a flattop beam helps reducing gray-level fluctuations. The multi-line Argon laser enables having multiple single beams separated from a single stabilized laser source. The single 514.5nm line used for writing gives better control of beam shape in the modulated laser beam. At the same time a lower power 457.9nm line introduced in the beam path to characterize the grayscale pattern both during and after the writing process. Filtering the writing laser line, sensor below the mask plate measures only the 457.9nm line enabling the high accuracy transparency measurements of the written mask near G-line (435.8nm). One target application is the creation of micro-lens arrays, which are lenses whose optical shape varies from lenslet to lenslet across the entire patterned surface of cm size. Laser direct-written grayscale masks enable relatively low cost, rapid turnaround mask production needed for creating such structures with microfabrication processes.

The acceptable tolerance level for CD signatures induced by any process step in the mask manufacturing process has been dramatically reduced with each technology node. Chemical amplified resists (CAR) are used extensively for first layer mask imaging. Therefor a post exposure bake (PEB) process is required after resist exposure, adding yet another potential source of CD signatures. Consequentially, the thermal imprint of the bake process must be further reduced to meet the requirements of future technology nodes.

The influence of the measurement devices (wireless and wired sensor arrays) used to optimize the hotplate, on the performance of the Post Exposure Bake (PEB) process is discussed in [1,2]. A concept of utilizing two wired sensor arrays, with wire connections attached in opposite locations on the sensor array surface, called “Mirror Bake” is introduced. Based on the individual hotplate optimization for each of those two sensor arrays, a combined bake recipe for the multi-zone hotplate is calculated. This method eliminates the systematic temperature non-uniformity introduced by the sensor array hardware, when optimizing the recipes with only one sensor array.

In this paper the “mirror bake” concept is validated by comparing the CD uniformity data of masks manufactured with a PEB process, optimized using a single standard sensor array vs. the “mirror bake” concept. The “mirror bake” concept achieved a CD uniformity improvement of up to 30% (CD range). During this work additional hardware influences from the sensor arrays were identified.

As lithography requirements mandate ever-thinner resist thickness, the need for in-situ monitoring has become more urgent. In this paper we present an in-situ optical methodology-based system to determine residual photoresist thickness during advanced photomask etch with < 1000 Å photoresist. Several types of phase-shift masks and photoresists were examined. A series of masks were etched to demonstrate the performance of the system. Results show an average accuracy of better than 2%, with a maximum absolute range of all tests within 8%.

Hotspot classification is an important step of hotspot management. Under possible center-shifting condition, conventional hotspot classification by calculating pattern similarity through overlaying two hotspot patterns directly is not effective. This paper proposes a hotspot classification method based on higher-order local autocorrelation (HLAC). Firstly, we extract the features of the hotspot patterns using HLAC method. Secondly, the principal component analysis (PCA) is performed on the features for dimension reduction. Thirdly, the simplified low dimensional vector features of the hotspot patterns are used in the pre-clustering step. Finally, detailed clustering using pattern similarity calculated by discrete 2-d correlation is carried out. Because the HLAC based features are shifting-invariant, the center-shifting problem caused by the defect location inaccuracy can be overcome during the pre-clustering process. Experiment results show that the proposed method can classify hotspots under center-shifting condition effectively and speed up the classification process greatly.

Proximity Effect Correction parameters for Electron Beam Lithography are of critical importance for Critical Dimension uniformity and pattern fidelity in the manufacture of Extreme Ultraviolet Lithography reticles¹. The values of these parameters are well known for simple substrates, such as silicon wafers, but complex substrates such as EUV blanks, composed of several layers of materials (quartz, molybdenum, silicon and ruthenium) present a challenge^2,3. The authors present a single exposure method for determining the PEC parameters for arbitrary substrates, demonstrated on silicon wafers and EUV reticles using a VB300 Gaussian EBL writer and patterns conducive to CDSEM metrology. The authors demonstrate the ability to utilize the parameters determined using this method to attain less than 3nm three-sigma CD uniformity across the pattern. The results of this empirical approach are compared to the results of Monte Carlo simulation to determine which layers in the EUV stack have the most impact on the optimal PEC parameters obtained.

TNO has developed the Rapid Nano scanner to detect nanoparticles on EUVL mask blanks. This scanner was designed to be used in particle qualifications of EUV reticle handling equipment. In this paper we present an end-to-end model of the Rapid Nano detection process. All important design parameters concerning illumination, detection and noise are included in the model. The prediction from the model matches the performance that was experimentally determined (59 nm LSE). The model will be used to design and predict the performance of future generations of particle scanners.