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Design for Manufacturability through Design-Process Integration VI
Editor(s): Mark E. Mason
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Volume Details

Volume Number: 8327
Date Published: 16 April 2012

Table of Contents
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Front Matter: Volume 8327
Author(s): Proceedings of SPIE
Implications of triple patterning for 14nm node design and patterning
Author(s): Kevin Lucas; Chris Cork; Bei Yu; Gerard Luk-Pat; Ben Painter; David Z. Pan
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Yield enhancement with DFM
Author(s): Seung Weon Paek; Jae Hyun Kang; Naya Ha; Byung-Moo Kim; Dae-Hyun Jang; Junsu Jeon; DaeWook Kim; Kun Young Chung; Sung-eun Yu; Joo Hyun Park; SangMin Bae; DongSup Song; WooYoung Noh; YoungDuck Kim; HyunSeok Song; HungBok Choi; Kee Sup Kim; Kyu-Myung Choi; Woonhyuk Choi; JoongWon Jeon; JinWoo Lee; Ki-Su Kim; SeongHo Park; No-Young Chung; KangDuck Lee; YoungKi Hong; BongSeok Kim
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Layout optimization through robust pattern learning and prediction in SADP gridded designs
Author(s): Jen-Yi Wuu; Mark Simmons; Malgorzata Marek-Sadowska
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Self-aligned double patterning (SADP) compliant design flow
Author(s): Yuangsheng Ma; Jason Sweis; Hidekazu Yoshida; Yan Wang; Jongwook Kye; Harry J. Levinson
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Design friendly double patterning
Author(s): Emek Yesilada
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Pattern matching for double patterning technology-compliant physical design flows
Author(s): Lynn T.-N. Wang; Vito Dai; Luigi Capodieci
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Design-of-experiments based design rule optimization
Author(s): Abde Ali Kagalwalla; Swamy Muddu; Luigi Capodieci; Coby Zelnik; Puneet Gupta
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Fully integrated litho aware PnR design solution
Author(s): Charlotte Beylier; Clement Moyroud; Fabrice Bernard Granger; Frederic Robert; Emek Yesilada; Yorick Trouiller; Jean-Claude Marin
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Replacing design rules in the VLSI design cycle
Author(s): Paul Hurley; Krzysztof Kryszczuk
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Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption
Author(s): Ahmad Abdulghany; Rami Fathy; Luigi Capodieci; Piyush Pathak; Sriram Madhavan; Shobhit Malik
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Local loops for robust inter-layer routing at sub-20 nm nodes
Author(s): Wenbin Huang; Daniel Morris; Neal Lafferty; Lars Liebmann; Kaushik Vaidyanathan; Kafai Lai; Larry Pileggi; Andrzej J. Strojwas
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A primer of physical design for lithographers
Author(s): Chi-Min Yuan
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Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs
Author(s): Yangang Wang; Mark Zwolinski; Andrew Appleby; Mark Scoones; Sonia Caldwell; Touqeer Azam; Philippe Hurat; Chris Pitchford
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Design level variability analysis and parametric yield improvement methodology
Author(s): Reinhard März; Martin Keck
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Analysis of layout-dependent context effects on timing and leakage in 28nm
Author(s): Patrick McGuinness; Puneet Sharma; Philippe Hurat
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Variability aware compact model characterization for statistical circuit design optimization
Author(s): Ying Qiao; Kun Qian; Costas J. Spanos
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Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node
Author(s): Kaushik Vaidyanathan; Siew Hoon Ng; Daniel Morris; Neal Lafferty; Lars Liebmann; Mitchell Bender; Wenbin Huang; Kafai Lai; Larry Pileggi; Andrzej Strojwas
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A novel methodology for triple/multiple-patterning layout decomposition
Author(s): Rani S. Ghaida; Kanak B. Agarwal; Lars W. Liebmann; Sani R. Nassif; Puneet Gupta
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Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning
Author(s): Weiling Kang; Yijian Chen
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Computational lithography work flows and design rule exploration automation
Author(s): S. Sethi; William Stanton; Kevin Lucas; Jay Hiserote; Duck-Hyung Hur; Rooli Choi
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Thickness-aware LFD for the hotspot detection induced by topology
Author(s): Jae-Hyun Kang; Naya Ha; Joo-Hyun Park; Byung-Moo Kim; Seung Weon Paek; Hungbok Choi; Kee Sup Kim; Ahmed Mohy; Shady Abdelwahed; Mohamed Imam
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The complexity of fill at 28nm and beyond
Author(s): Norma Rodriguez; Jie Yang; Bill Graupp; Jeff Wilson; Eugene Anikin
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In-design process hotspot repair using pattern matching
Author(s): Daehyun Jang; Naya Ha; Junsu Jeon; Jae-Hyun Kang; Seung Weon Paek; Hungbok Choi; Kee Sup Kim; Ya-Chieh Lai; Philippe Hurat; Wilbur Luo
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Clean pattern matching for full chip verification
Author(s): Satomi Nakamura; Tetsuaki Matsunawa; Chikaaki Kodama; Takanori Urakami; Nozomu Furuta; Shunsuke Kagaya; Shigeki Nojima; Shinji Miyamoto
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Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design
Author(s): Piyush Pathak; Sriram Madhavan; Shobhit Malik; Lynn T.-N. Wang; Luigi Capodieci
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Self-aligned double and quadruple patterning layout principle
Author(s): Koichi Nakayama; Chikaaki Kodama; Toshiya Kotani; Shigeki Nojima; Shoji Mimotogi; Shinji Miyamoto
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In-design hierarchical DFM closure for DFM-clean IP
Author(s): Vikas Tripathi; Jayathi Subramanian; Puneet Sharma; Kuang-Han Chen; Bala Kasthuri; Philippe Hurat; Larry Layton
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Automated yield enhancements implementation on full 28nm chip: challenges and statistics
Author(s): Shobhit Malik; Sriram Madhavan; Piyush Pathak; Luigi Capodieci; Ramy Fathy; Ahmad Abdulghany
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A study of pattern variability for device performance
Author(s): Tae-Heon Kim; Dae-Han Han; Ae-Ran Hong; Yong-Hyeon Kim; Joo-Sung Lee; Yun-Hye Chu; Kweon-Jae Lee; Yong-Jik Park
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Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs
Author(s): Yijian Chen; Weiling Kang; Qi Cheng
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Consideration of correlativity between litho and etching shape
Author(s): Ryoichi Matsuoka; Hiroaki Mito; Shinichi Shinoda; Yasutaka Toyoda
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Advanced techniques for design assembly and characterization for the 14nm node with LFD using a black box API
Author(s): Juliann Opitz; Andres Torres; Ioana Graur; Wael Manhawy; Suniti Kanodia; Marwah Shafee; Sarah Mohamed; Ahmed Hassand; Jeanne Bickford
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Fast optical proximity correction with timing optimization ready standard cells
Author(s): Yifan Qu; Chun Huat Heng; Arthur Tay; Tong Heng Lee
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Electrical design for manufacturability and lithography and stress variability hotspot detection flows at 28nmn
Author(s): Philippe Hurat; Jianhao Zhu; Edward Teoh
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Yield impacting systematic defects search and management
Author(s): Jing Zhang; Qingxiu Xu; Xin Zhang; Xing Zhao; Jay Ning; Guojie Cheng; Shijie Chen; Gary Zhang; Abhishek Vikram; Bo Su
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Model-based searching method to find the integrated critical failure on the wafer
Author(s): Bong-Soo Kang; No-Young Chung; Hyung-Kwan Park; Suk-Joo Lee; Ja-Hum Ku
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A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts
Author(s): Lynn T.-N. Wang; Sriram Madhavan; Shobhit Malik; Piyush Pathak; Luigi Capodieci
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