This PDF file contains the front matter associated with SPIE Proceedings Volume 8324, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Our world is three-dimensional, and so are the integrated circuits (ICs), they have always been. In the past, for a long time, we have been very fortunate, because it was enough to measure a simple critical dimension (CD), the width of the resist line, to keep IC production under acceptable control. This requirement has changed in the last few years to contour and now to three-dimensional measurements. Optical lithography is printing photoresist features that are significantly smaller than the wavelength of the light used, and therefore it is indispensable to use optical proximity correction (OPC) methods. This includes modeling and compensation for various errors in the lithography process down to sub-nanometer, essentially atomic levels. The process has to rely on sophisticated and complex simulations and on accurate and highly repeatable dimensional metrology. The necessary dimensional metrology is beyond the conventional one-dimensional line width measurements, and must include two - and three-dimensional measurements of the contours and shapes of structures. Contour metrology needs accurate and highly repeatable measurements on sets and individual OPC structures, for which the critical dimension measurement scanning electron microscope (CD-SEM) is the key metrology tool. Three-dimensional (3D) metrology is now indispensable for IC technology, but current metrology tools and methods cannot fulfill the requirements. We believe that with the implementation of new methods it is feasible to develop 3D metrology that will well serve IC production, even on structures in the few nanometer-size range.

3D IC integration employs advanced interconnect technologies including through-silicon vias (TSVs), bonding, wafer thinning, backside processing and fine pitch multi-chip stacking. In 2013, Mobile Wide I/O DRAM is expected to be one of the first high volume 3D IC applications. Many of the manufacturing steps in TSV processing and 3D integration can complicate inspection and metrology. This paper reviews a typical via-mid flow emphasizing the inspection and metrology challenges inherent in 3D integration. A preliminary look at the 2011 ITRS roadmap for 3D interconnect metrology is presented, including the gaps in currently available inspection and metrology tools.

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipments (such as CDSEM, AFM, Scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of Hybrid Metrology (HM) - a practice of combining measurements from multiple equipment types in order to enable or improve measurement performance. In this paper we extend our previous work on HM to measure advanced 1X node layers - EUV and Negative Tone Develop (NTD) resist as well as 3D etch structures such as FinFETs. We study the issue of data quality and matching between toolsets involved in hybridization, and propose a unique optimization methodology to overcome these effects. We demonstrate measurement improvement for these advanced structures using HM by verifying the data with reference tools (AFM, XSEM, TEM). We also study enhanced OCD models for litho structures by modeling Line-edge roughness (LER) and validate its impact on profile accuracy. Finally, we investigate hybrid calibration of CDSEM to measure in-die resist line height by Pattern Top Roughness (PTR) methodology.

A dose-focus monitoring technique using critical dimension scanning electron microscope (CD-SEM) is studied for onproduct applications. Our technique uses two target structures; one is a dense grating structure with iso-focal pitch for dose determination, and the other is a relatively isolated line grating with no assists for focus determination. The small sizes of these targets enable us to monitor dose and focus variations across the chip on a product wafer. The model which describes how the top and bottom CD depend on dose and focus deviations is the same as that for scatterometry dose-focus metrology, and monitoring precision is estimated to be the order of 1% for dose and 10~15nm for focus. The method has strong potential to apply to dose and focus monitoring of product wafers. By using a mask with a multitude of these targets, it is possible to study dose and focus variations across the wafer in great detail. The focus variation of pairs of such targets is measured for various separations between the two targets. As the separation distance increases from ~100μm to ~10mm, the focus variation increases from 10nm to 25nm. We think that the true focus variation between targets becomes near zero at the small separation distance, while the focus variation increases as separation distance increases because more variation sources such as wafer thickness variation are included at larger separation distances. Our small CD-SEM targets allow us to explore this kind of local spatial variation analysis.

Introduction of new material stacks, more sophisticated design rules and complex 3D architectures in semiconductor technology has led to major metrology challenges by posing stringent measurement precision and accuracy requirements for various critical dimensions (CD), feature shape and profile. Current CD metrology techniques being used in development and production such as CD-SEM, scatterometry and CDAFM, individually have intrinsic limitations that must be overcome. The approach of hybrid automated metrology seems necessary. Using multiple tools in unison is an adequate solution when adding their respective strengths to overcome individual limitations. Such solution will give the industry a better metrology solution than the conventional approach. Nevertheless, this is not enough since the industry is requested for 2D and 3D profiles information. Indeed, CD, height and/or Sidewall angle are information which is limited for future nodes production. Full profile information is necessary. In this paper, the first part will be dedicated to the introduction of contour object as a new standard for the semiconductor industry. This metric will take into account all pattern's profile information in order to overcome the limitations of simple CD and/or SWA information. The second part will present and discuss results concerning data fusion and its application to hybrid metrology. We will illustrate hybrid metrology with an application to CD-SEM enhancement with a reference technique such as the AFM3D or TEM technology. We will show that it could be possible to improve RMS error of CD-SEM by a factor of 78%. We think that such trend can be extended to all microelectronic levels in IC manufacturing and subsequently significantly reduce cycle time and improve production yield through easier hotspot detection.

In recent semiconductor manufacturing, hardmask is unavoidable requirement to further transfer the patterning from thin photoresist to underlayer. While several types of hardmask materials have been investigated, amorphous carbon has been attractive for good etching resistance and high-aspect-ratio resolution. However, it has fatal problem with lowering overlay controllability due to its high extinction coefficient (k). Thus, the correlation of alignment and overlay performance with varying hardmask materials is required to meet a tight overlay budget of 2x nm node and beyond. In this paper, we have investigated the effects of the hardmask materials with respect to the optical properties on the performance of overlay applicable to 2x nm memory devices.

Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes. Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated. How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product specific corrections per exposure and 10 term APC process control.

Overlay metrology performance is usually reported as repeatability, matching between tools or optics aberrations distorting the measurement (Tool induced shift or TIS). Over the last few years, improvement of these metrics by the tool suppliers has been impressive. But, what about accuracy? Using different target types, we have already reported small differences in the mean value as well as fingerprint [1]. These differences make the correctables questionable. Which target is correct and therefore which translation, scaling etc. values should be fed back to the scanner? In this paper we investigate the sources of these differences, using several approaches. First, we measure the response of different targets to offsets programmed in a test vehicle. Second, we check the response of the same overlay targets to overlay errors programmed into the scanner. We compare overlay target designs; what is the contribution of the size of the features that make up the target? We use different overlay measurement techniques; is DBO (Diffraction Based Overlay) more accurate than IBO (Image Based Overlay)? We measure overlay on several stacks; what is the stack contribution to inaccuracy? In conclusion, we offer an explanation for the observed differences and propose a solution to reduce them.

The extension of optical lithography to 2Xnm and beyond is often challenged by overlay control. With reduced overlay measurement error budget in the sub-nm range, conventional Total Measurement Uncertainty (TMU) data is no longer sufficient. Also there is no sufficient criterion in overlay accuracy. In recent years, numerous authors have reported new method of the accuracy of the overlay metrology: Through focus and through color. Still quantifying uncertainty in overlay measurement is most difficult work in overlay metrology. According to the ITRS roadmap, total overlay budget is getting tighter than former device node as a design rule shrink on each device node. Conventionally, the total overlay budget is defined as the square root of square sum of the following contributions: the scanner overlay performance, wafer process, metrology and mask registration. All components have been supplying sufficiently performance tool to each device nodes, delivering new scanner, new metrology tools, and new mask e-beam writers. Especially the scanner overlay performance was drastically decreased from 9nm in 8x node to 2.5nm in 3x node. The scanner overlay seems to reach the limitation the overlay performance after 3x nod. The importance of the wafer process overlay as a contribution of total wafer overlay became more important. In fact, the wafer process overlay was decreased by 3nm between DRAM 8x node and DRAM 3x node. We develop an analytical algorithm for overlay accuracy. And a concept of nondestructive method is proposed in this paper. For on product layer we discovered the layer has overlay inaccuracy. Also we use find out source of the overlay error though the new technique. In this paper, authors suggest an analytical algorithm for overlay accuracy. And a concept of non-destructive method is proposed in this paper. For on product layers, we discovered it has overlay inaccuracy. Also we use find out source of the overlay error though the new technique. Furthermore total overlay error data is decomposed into two parts: the systematic error and the random error. And we tried to show both error components characteristic, systematic error has a good correlation with residual error by scanner condition, whereas, random error has a good correlation with residual error as going process steps. Furthermore, we demonstrate the practical using case with proposed method that shows the working of the high order method through systematic error. Our results show that to characterize an overlay data that is suitable for use in advanced technology nodes requires much more than just evaluating the conventional metrology metrics of TIS and TMU.

As half pitch shrinks to sub 20nm dimensions, the latest hybrid IC (integrated circuit) designs include a greater number of features that approach the resolution limits of the scanner than in the previous generation of IC designs. This trend includes stringent design rules and complex, ever smaller optical proximity correction (OPC) structures. In this regime, a new type of mask, known as opaque MoSi on glass (OMOG), has been introduced to overcome the shortcomings of the well-established phase shift masks (PSM). As for lithography, scanner and mask determine ultimate intra-field performance as one approaches scanner resolution limits. Holistic lithography techniques have been developed to optimize the interrelated mask and scanner effects on critical dimension uniformity (CDU) and common process window (PW) for the most demanding sub 20nm node features. This paper presents an efficient and production worthy methodology for evaluating the CDU, PW, and 3D effect fingerprints of the latest immersion scanner and thin OMOG masks, and minimizing them using high-order optimizers of the latest holistic ArFi lithography.

Pitch and CD scaling have been the main drivers of wafer inspection (WI) requirements, with tighter pitches and smaller CD's pushing the adoption of inspection tools with greater capabilities. With the introduction of strained silicon, Hi-k / metal gates and tri-gate transistors, integration schemes are playing a prominent role in WI. The present paper explores, through FDTD aerial image simulations, the impact of device integration scheme on WI. Various defect types are simulated for planar gate, planar Hi-k / metal gate and tri-gate transistors and the impact to WI requirements are explored.

We implement coherent diffractive imaging (CDI) using a phase-matched high-harmonic generation (HHG) source at 13 nm, demonstrating reconstructed images with a record 22 nm resolution for any tabletop, light-based microscope. We also demonstrate the first reflection-mode CDI using a compact extreme ultraviolet (EUV) source, achieving ≈100 nm resolution. A clear path towards even higher spatial resolution reflection-mode tabletop imaging using apertured-illumination schemes will be discussed.

Through-focus scanning optical microscopy (TSOM) is a novel method [1-8] that allows conventional optical microscopes to collect dimensional information down to the nanometer level by combining 2D optical images captured at several through-focus positions, transforming conventional optical microscopes into truly 3D metrology tools for nanoscale to microscale dimensional analysis with nanometer scale sensitivity. Although not a resolution enhancement method, it has been shown to provide lateral and vertical measurement sensitivity of less than a nanometer [5], comparable to the dimensional measurement sensitivity of other critical dimension (CD) metrology tools. The technique is capable of measuring features far beyond the theoretical resolution limits of optical microscopy, because it can capture much richer data at many z-heights (i.e., through focus). Additionally, TSOM appears to decouple the measurement of profile dimensional changes at the nanoscale, such as small perturbations in sidewall angle and height, with little or no ambiguity, and may be able to analyze target dimensions ranging from as small as 10 nm up to many microns with similar nanometer-scale sensitivity. Furthermore, previous simulation and experimental work has shown this method to be applicable to a variety of target materials and structures, such as nanoparticles, semiconductor memory features, and buried structures under transparent films. Additionally, this relatively simple technique is inexpensive and has high throughput, making it attractive for a variety of semiconductor metrology applications, such as CD, photomask, overlay, and defect metrologies [8]. In-line defect metrology is continuously challenged by the aggressive pace of device scaling. It is expected that the conventional brightfield techniques currently used in semiconductor manufacturing will not be able to meet defect inspection requirements near the 11 nm node. Electron beam-based inspection is able to meet resolution limits well below the 11 nm node, but operates at a significantly lower throughput. It has therefore become necessary to explore alternative approaches that have the potential to meet both resolution and throughput requirements. This work will present TSOM results of simulations and supporting experiments to demonstrate the metrology application of TSOM to features at the ITRS 22 nm node [9], including measurement of linewidths down to 10 nm, showing the ability to measure changes in line height, sidewall angle, and pitch variations. By extension, these results will show the feasibility of applying TSOM to important contemporary metrology problems in measuring doublepatterned features and FinFETs. Additionally, we will theoretically explore the use of TSOM to inspect defects on gatelevel arrays with different CDs down to 15 nm. This theoretical work consisted of modeling the optical response of cross-sectional perturbations and several patterned defect types and sizes using illumination wavelengths ranging from visible to deep ultraviolet (DUV) under different illumination polarizations. The results indicate that TSOM may be able to detect small CD and profile changes in fins of FinFET structures as well as defects that currently challenge conventional brightfield optical methods. The simulation results also indicate an added advantage of the TSOM method to differentiate certain types of defects and their orientations by exhibiting different optical intensity patterns. These results will provide insight into the feasibility of TSOM for CD and yield enhancement metrology.

Smaller patterning dimensions and novel architectures are fostering research into improved methods of defect detection in semiconductor device manufacturing. This experimental study, augmented with simulation, evaluates scatterfield microscopy to enhance defect detectability on two separate 22 nm node intentional defect array wafers. Reducing the illumination wavelength nominally delivers direct improvements to detectability. Precise control of the focus position is also critical for maximizing the defect signal. Engineering of the illumination linear polarization and incident angle are shown to optimize the detection of certain highly directional defects. Scanning electron microscopy verifies that sub 15 nm defects can be measured experimentally using 193 nm wavelength light. Techniques are discussed for taking advantage of the complexities inherent in the scattering of highly directional defects within unidirectional patterning. Although no one single set of parameters can be optimized to detect all defects equally, source optimization is shown to be a realistic path towards improved sensitivity.

Single-column e-beam systems are used in production for the detection of electrical defects, but are too slow to be used for the detection of small physical defects, and can't meet future inspection requirements. This paper presents a multiplecolumn e-beam technology for high throughput wafer inspection. Multibeam has developed all-electrostatic columns for high-resolution imaging. The elimination of magnetic coils enables the columns to be small; e-beam deflection is faster in the absence of magnetic hysteresis. Multiple miniaturecolumns are assembled in an array. An array of 100 columns covers the entire surface of a 300mm wafer, affording simultaneous cross-wafer sampling. Column performance simulations and system architecture are presented. Also provided are examples of high throughput, more efficient, multiple-column wafer inspection.

In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication processes, in line SEM metrology measurements, and a new methodology to calibrate and correct in line roughness measurements, improving measurement accuracy. Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing was shown as a useful method for the fabrication of smooth suspended SiNW that are used to build gate-all-around MOSFETs [1]. Wires that were annealed in H₂ exhibit surface roughness below 1 nm along the full length of the 100 nm long suspended wires. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range. Such small differences in roughness values, provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and validate the experimental CD-SEM results.

As the feature size of the semiconductor device is becoming increasingly smaller and the transistor has become three-dimensional (e.g. Fin-FET structure), a simple Line Edge Roughness (LER) is no longer sufficient for characterizing these devices. Sidewall Roughness (SWR) is now the more proper metric for these metrology applications. However, current metrology technologies, such as SEM and OCD, provide limited information on the sidewall of such small structures. The subject of this study is the sidewall roughness measurement with a three-dimensional Atomic Force Microscopy (AFM) using tilted Z scanner. This 3D AFM is based on a decoupled XY and Z scanning configuration, in which the Z scanner can be intentionally tilted to the side. A sharp conical tip is typically used for imaging, which provides high resolution capability on both the flat surfaces (top and bottom) and the steep sidewalls.

Various reports state that LER/LWR has a significant impact on lithography-fabricated ICs, rendering it desirable to be able to determine the LER in-line so that it never exceeds certain specified limits. In our simulation work we deal with the challenge of measuring LER on CD-50nm resist gratings using plane- mount scatterometry. We show that there is a difference between LER and no-LER scatter signatures which first: depends on the polarization and second: is proportional to the amount of LER. Moreover - we show that the said difference can be best-fit to the difference between scatter signatures of two rigorously determined, specific no-LER CDs, which allows us to predict the sensitivity of ITRS' "manufacturable solution" for scatterometric LER measurement just by using computationally cheap 1D RCWA simulations. As it can be shown the sensitivity is not uniform for all realizations of the same CD (e.g. for different resist heights), so not in all gratings LER is equally easy to determine.

The aim of this work is to study the effects of noise on the parameters characterizing the size and roughness of contact edges when they are measured by the analysis of top-down SEM images. The applied methodology is based on the modelling of rough contact edges with controlled roughness parameters and the generation of synthesized top down SEM images with several contact edges and a distribution of Critical Dimension (CD) values (CD nonuniformity). The sources of noise can be the shot noise of SEM electron beam (Poisson-type) and the microscope electronics (Gaussiantype). First, we check out the validity of the model and then we apply it to evaluate the effects of noise in synthesized SEM images with smooth and images with rough contact edges. The results show that in all cases, noise lowers CD and correlation length while it increases the rms value. CD variation is increased with noise in images with smooth and identical contacts whereas it remains almost unaltered in images including rough contacts with CD nonuniformity. Furthermore, we find that the application of a noise smoothing filter before image analysis is able to rectify the values of CD (at small filter parameter) and of rms and correlation length (at larger filter parameters), whereas it leads to larger deviations from the true values of CD variation. Quantitative assessment of the model predictions reveals that the noise induced variations of CD and CER values are inferior to those caused by process stochasticity and material inhomogeneities.

Optical bright field wafer inspection followed by repeater analysis is used to find a maximum number of programmed and natural defects on a EUV patterned mask. Each aspect of the inspection methodology affecting the sensitivity of the wafer inspection is optimized individually. A special focus is given to the wafer stack. Simulation is used to predict the optimum stack properties and experimental verification is performed through exposures on the IMEC EUV Alpha Demo Tool. The final result is benchmarked against state-of-the-art patterned mask inspection and blank inspection to evaluate the capabilities and limitations of the optical wafer inspection. In addition, the locations obtained by each inspection technique (wafer and mask) were reviewed on wafer by means of a new automated methodology that is based on a tight stage accuracy of both inspection tool and review SEM.

Resolution enhancement techniques such as double patterning (DP) processes are implemented to achieve lower critical dimension (CD) control tolerances. However the design complications, overlay resulting from multiple exposures, and production cost limit the DP usage. EUVL offers the most promising patterning technology to be adopted for 14nm and beyond due to simplicity and cost advantage estimates. However, EUVL is also prone to number of patterning challenges that are unique to EUV, such as orientation dependent pattern placement errors resulting from mask shadowing effect, flare(leads to CD non-uniformity) and non-flatness (leads to overlay errors). Even though the shadowing effects can be corrected by means of OPC and mask stack design, there is a need to monitor the systemic errors due to HV bias in order to control the lithographic process. In this paper, we will report the measurement sensitivity of EUVL targets (CD, height and sidewall angle), systemic CD errors (H-V bias) and feedback for OPC correction by scatterometry. We will also report the measurement precision, accuracy and matching for EUV structures.

There has been much recent work in developing advanced optical metrology applications that use imaging optics for critical dimension measurements, defect detection and for potential use with in-die metrology. Sensitivity to nanometer scale changes has been observed when measuring critical dimensions of sub-wavelength features or when imaging defects below 20 nm using angle-resolved and focus-resolved optical data. However, these methods inherently involve complex imaging optics and analysis of complicated three-dimensional electromagnetic fields. This paper will develop a new approach to enable the rigorous analysis of three-dimensional through-focus optical images. We use rigorous electromagnetic simulation tools and statistical methods to evaluate sensitivities and uncertainties in the measurement of three dimensional layouts encountered in critical dimension, contour metrology and defect inspection.

Scatterometry is one of the most useful metrology methods for the characterization and control of critical dimensions (CD) and the detailed topography of periodic structures in microelectronics fabrication processes. Spectroscopic Ellipsometry (SE) and Normal Incidence Reflectometry (NI) based Scatterometry are the most widely used methodologies for metrology of these structures. Evolution of better optical hardware and faster computing capabilities led to the development of Mueller Matrix (MM) based Scatterometry (MMS). In this paper we present the first study of dimensional metrology using full Mueller Matrix (16 element) Scatterometry in the wavelength range of 245nm- 1000nm. Unlike SE and NI, MM data provides complete information about the optical reflection and transmission of polarized light through a sample. MM is a 4x4 transformation matrix (16 elements) describing the change in the intensities of incident polarized light expressed by means of a Stokes Vector. The symmetry properties associated with MM provide an excellent means of measuring and understanding the topography of the periodic nanostructures. Topography here refers to uniformity of the periodic structure. The advantage of MMS over traditional SE Scatterometry is the ability of MMS to measure samples that have anisotropic optical properties and depolarize light. The present study focuses on understanding the precision and accuracy of Mueller based Scatterometry with respect to other methodologies by a systematic approach. Several laterally complex nanoscale structures with dimensions in the order of nanometers were designed and fabricated using a state of the art E-beam pattering tool (VISTEC [R] 300). Later, Spectroscopic Mueller matrix (all 16 elements) and SE data were collected in planar diffraction mode for the samples using J.A. Woollam RC2 [TM] Spectroscopic Ellipsometer. NanoDiffract [TM] (Scatterometry software provided by Nanometrics Inc.) was used to model the nanostructures to precisely calculate the critical dimensions. Complementary techniques like SEM were used to compare the results obtained from Scatterometry. Finally, Mueller and SE based Scatterometry techniques were compared commenting on reliability of MM based Scatterometry.

As the semiconductor industry is moving to very low-k1 patterning solutions, the metrology problems facing process engineers are becoming much more complex. Choosing the right optical critical dimension (OCD) metrology technique is essential for bridging the metrology gap and achieving the required manufacturing volume throughput. The critical dimension scanning electron microscope (CD-SEM) measurement is usually distorted by the high aspect ratio of the photoresist and hard mask layers. CD-SEM measurements cease to correlate with complex three-dimensional profiles, such as the cases for double patterning and FinFETs, thus necessitating sophisticated, accurate and fast computational methods to bridge the gap. In this work, a suite of computational methods that complement advanced OCD equipment, and enabling them to operate at higher accuracies, are developed. In this article, a novel method for accurately modeling OCD profiles is presented. A finite element formulation in primal form is used to discretize the equations. The implementation uses specialized finite element spaces to solve Maxwell equations in two dimensions.

Incoherent Optical Scatterometry (IOS) is a well-established metrology technique in the semiconductor industry to retrieve periodic grating structures with high accuracy from the signature of the diffracted optical far field. With shrinking dimensions in the lithography industry, finding possible improvements in wafer metrology is highly desirable. The grating is defined in terms of a finite number of geometrical shape parameters (height, side-wall angles, midCD etc.). In our method the illumination is a scanning focused spot from a spatially coherent source (laser) within a single period of the grating. We present a framework to study the increment in sensitivity of Coherent Fourier Scatterometry (CFS) with respect to the IOS. Under suitable conditions, there is a more than fourfold enhancement in sensitivity for grating shape parameters using CFS. The dependence of scanning positions on the sensitivity analysis is also highlighted. We further report the experimental implementation of a Coherent Fourier Scatterometer. The simulated and experimental far fields are compared and analyzed for the real noise in the experimental configuration.

We studied the potential of optical scatterometry to measure the full 3D profile of features representative to real circuit design topology. The features were selected and printed under conditions to improve the measurability of the features by scatterometry without any loss of information content for litho monitoring and control applications. The impact of the scatterometry recipe and settings was evaluated and optimal settings were determined. We have applied this strategy on a variety of structures and gathered results using the YieldStar angular reflection based scatterometer. The reported results show that we obtained effective decoupling of the measurement of the 3 dimensions of the features. The results match with predictions by calibrated lithographic simulations. As a verification we have successfully performed a scanner matching experiment using computational Pattern Matcher (cPM) in combination with YieldStar as a metrology tool to characterize the difference between the scanners and verify the matching. The results thus obtained were better than using CD-SEM for matching and verification.

The uncertainty associated with scanning electron microscopy (SEM) metrology is significant because SEM image brightness is complexly related to the size and shape of the feature, its material, the geometry of the pattern, as well as SEM setup. While regularly used methods of extracting critical dimensions (CD) rely on image brightness analysis, the myCD software uses a physical model of the SEM in order to improve the accuracy of measurements. Metrology below 10 nm was studied in this paper. Patterns were fabricated using electron beam lithography and nanoimprint; they were imaged by SEM and examined using myCD. Factors that are important for metrology at the sub-10 nm size range were studied using advanced Monte Carlo software; the beam size, voltage, detector and linewidth were varied. SEM images were processed using myCD, which utilizes an analytic model of the SEM and so does not require any libraries. The top and bottom sizes, as well as wall angles and line width roughness were analyzed. The CD and profile results from top down SEM images were compared to the vertical crossections. The challenges of sub-10 nm metrology are discussed, mainly regarding the quality of SEM images and the physics of image formation.

The critical dimension atomic force microscope (CD-AFM), which is used as a reference instrument in lithography metrology, has been proposed as a complementary instrument for contour measurement and verification. Although data from CD-AFM is inherently three dimensional, the planar two-dimensional data required for contour metrology is not easily extracted from the top-down CD-AFM data. This is largely due to the limitations of the CD-AFM method for controlling the tip position and scanning. We describe scanning techniques and profile extraction methods to obtain contours from CD-AFM data. We also describe how we validated our technique, and explain some of its limitations. Potential sources of error for this approach are described, and a rigorous uncertainty model is presented. Our objective is to show which data acquisition and analysis methods could yield optimum contour information while preserving some of the strengths of CD-AFM metrology. We present comparison of contours extracted using our technique to those obtained from the scanning electron microscope (SEM), and the helium ion microscope (HIM).

Critical Dimension AFM (CD-AFM) is a widely used reference metrology. To characterize modern semiconductor devices, very small and flexible probes, often 15 nm to 20 nm in diameter, are now frequently used. Several recent publications have reported on uncontrolled and significant probe-to-probe bias variation during linewidth and sidewall angle measurements [1,2]. Results obtained in this work suggest that probe bending can be on the order of several nanometers and thus potentially can explain much of the observed CD-AFM probe-to-probe bias variation. We have developed and experimentally tested one-dimensional (1D) and two-dimensional (2D) models to describe the bending of cylindrical probes. An earlier 1D bending model reported by Watanabe et al. [3] was refined. Contributions from several new phenomena were considered, including: probe misalignment, diameter variation near the carbon nanotube tip (CNT) apex, probe bending before snapping, distributed van der Waals-London force, etc. The methodology for extraction of the Hamaker probe-surface interaction energy from experimental probe bending data was developed. To overcome limitations of the 1D model, a new 2D distributed force (DF) model was developed. Comparison of the new model with the 1D single point force (SPF) model revealed about 27 % difference in probe bending bias between the two. A simple linear relation between biases predicted by the 1D SPF and 2D DF models was found. This finding simplifies use of the advanced 2D DF model of probe bending in various CD-AFM applications. New 2D and three-dimensional (3D) CDAFM data analysis software is needed to take full advantage of the new bias correction modeling capabilities.

The novel method of sub-nanometer accuracy (uncertainty) for the line width measurement and line edge detection using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement and standardization of line edge detection. In accordance with the proposed method, the traceability and reference metrology are established using Si lattice structures and edge detection of Si line with metal coating. First, the interface of SiO2-Air is defined using image intensity of STEM dark field images after metal coating. Second, an image magnification is calculated using 2D Fourier analysis of the images. Third, the edge positions are detected. Using the proposed method, the expanded uncertainty (3 sigma) less than 0.3 nm for the line width of 50 nm is established.

The focused ion beam (FIB) milling tool is an important component of reference metrology and process characterization, both as a supporting instrument for bulk sample preparation before forwarding to the transmission electron microscope (TEM) and other instruments and as an in situ measurement instrument using angled scanning electron microscopy. As features grow denser, deeper and more demanding, full-profile reference metrology is needed, and this methodology will only grow in importance. Thus, the ability to extract accurate dimensional and profile information out of the crosssectional faces produced by FIB milling is critical. For features that demonstrate perfect symmetry in the plane of the cross section, analyzing images and extracting metrology data are straightforward. However, for industrial materials, symmetry is not a safe assumption: as features shrink, the line edge and sidewall roughness increases as a percentage of the overall feature dimension. Furthermore, with the introduction of more complex architectures such as 3D memory and FinFETs, the areas of greatest interest, such as the intersections of wrap-around gates, cannot be assumed to be symmetrical in any given plane if cut placement is not precisely controlled. Therefore it is important to establish the exact location and repeatability of the cross-section plane, both in terms of coordinate placement and effective angle of the milled surface. To this end, we prepared designed-in line edge roughness samples in the Albany Nanotech facility using SEMATECH's AMAG6 metrology reticle. The samples were thoroughly characterized before being milled by a non-destructive, sidewall-scanning atomic force microscope (AFM). These samples are then milled and measured under varying process and setup parameters using a single-beam FIB with angled SEM. We established methodologies that allow precise alignment of the cut planes of slice-and-view FIB milling to 3D-AFM scan lines to compare repeated sections throughout a feature. This gives us a large amount of data to test the accuracy and repeatability of cut placement using various alignment and recipe setup schemes.

Alternate techniques for obatining metrology data from advanced semiconductor device structures may be required. Automated STEM-based dimensional metrology (CD-STEM) was developed for complex 3D geometries in read/write head metrology in teh hard disk drive industry. It has been widely adopted, and is the process of record for metrology. Fully automated S/TEM metrology on advanced semiconductor gate structures is viable, with good repeatability and robustness. Consistent automated throughput of 10 samples per hour was achieved. Automated sample preparation was developed with sufficient throughput and quality to support the automated CD-STEM.

Local-distortion of CD-SEM image can be detected and compensated by a unique technique: View-Shift method. As design rule of semiconductor device is getting shrunk, metrology by critical dimension scanning electron microscope (CD-SEM) is not only for measuring dimension but also shape, such as 2D contour of hot-spot pattern and OPC calibration-pattern. Accuracy of the shape metrology is dependent on the local image-distortion that consists of two components: magnification distortion and shape distortion. The magnification distortion can be measured by pitchcalibration method, that measures pitch of an identical line pattern at a lot of locations in image. However, this method cannot measure the shape distortion, that is for instance, bending of a uniform-width line. To measure accurately and quickly the image-distortion, we invented the View-Shift method, in which images of uniquetexture sample are taken before and after an image-shift by about 100nm. Between the two images we measure displacements of the unique-textures found at each grid-point spread over the image. Variation of the local displacements indicates the local image-distortion. In this work, we demonstrate a method to compensate the image-distortion detected by the View-Shift method. Due to the image-distortion, edge-points determined in SEM-image have already been dislocated. Such dislocation can be relocated to compensate the detected local-distortion. Onsite and on-demand compensation right before CD-SEM measurement for process monitoring is possible because we can quickly apply the View-Shift method and complete the compensation in a few minutes.

The continuous development of three-dimensional chip/wafer stacking technology has created the metrology requirements for in-line 3D manufacturing processes. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at ITRI (Industrial Technology Research Institute). An IR metrology tool including broadband infrared microscopic imaging module and a specific infrared laser confocal module is developed for the thinned wafers thickness measurement with spatial resolution of 0.5 μm. An existing spectral reflectometer is used and enhanced by implementing novel theoretical model and measurement algorithm for HDTSV inspection. It is capable of measuring via depth/bottom roughness/bottom profile in one shot measurement. A metrology module based on two sets of dual-channel capacitive sensors for metallization film thickness measurement is applied to make critical process control in the fab. We will share real metrology results and discuss possible solutions for 3D interconnect processing.

Laboratory-based X-ray microscopy combined with computational tomography imaging is demonstrated to have advantages over other methods of inspecting through-silicon vias (TSVs). We show that the 8 keV X-rays used by Nano X-ray Computed Tomography (NanoXCT^TM) are capable of imaging voids inside filled vias before and after annealing without cross-sectioning the TSV. A series of - TSV arrays filled conformally and from the bottom up were inspected by the X-ray microscope before and after annealing. Pre-existing voids in the seamline were observed in conformally filled TSVs before annealing, while bottom up-filled TSVs do not have a seamline or voids. The same TSV samples were repeatedly annealed at 225^oC, and 300^oC. After annealing, the X-ray micrograph of the same TSV array showed void growth in only the conformally filled TSV. In addition, X-ray measurements show the total volume of void growth increased with annealing temperature.

3D IC integration continues to increase in complexity, employing advanced interconnect technologies such as throughsilicon vias (TSVs), wafer-to-wafer (W2W) bonding, and multi-chip stacking. As always, the challenge with developing new processes is to get fast, effective feedback to the integration engineer. Ideally this data is provided by nondestructive in-line metrology, but this is not always possible. For example, some form of physical cross-sectioning is still the most practical way to detect and characterize TSV copper plating voids. This can be achieved by cleaving, followed by scanning electron microscope (SEM) inspection. A more effective physical cross-sectioning method has been developed using an automated dual-beam focused ion beam (FIB)-SEM system, in which multiple locations can be sectioned and imaged while leaving the wafer intact. This method has been used routinely to assess copper plating voids over the last 24 months at SEMATECH. FIB-SEM feedback has been used to evaluate new plating chemistries, plating recipes, and process tool requalification after downtime. The dualbeam FIB-SEM used for these studies employs a gallium-based liquid metal ion source (LMIS). The overall throughput of relatively large volumes being milled is limited to 3-4 hours per section due to the maximum available beam current of 20 nA. Despite the larger volumetric removal rates of other techniques (e.g., mechanical polishing, broad-ion milling, and laser ablation), the value of localized, site-specific, and artifact-free FIB milling is well appreciated. The challenge, therefore, has been to reap the desired FIB benefits, but at faster volume removal rates. This has led to several system and technology developments for improving the throughput of the FIB technique, the most recent being the introduction of FIBs based on an inductively coupled plasma (ICP) ion source. The ICP source offers much better performance than the LMIS at very high beam currents, enabling more than 1 μA of ion beam current for fast material removal. At a lower current, the LMIS outperforms the ICP source, but imaging resolution below 30 nm has been demonstrated with ICP-based systems. In addition, the ICP source allows a wide range of possible ion species, with Xe currently the milling species of choice, due to its high mass and favorable ion source performance parameters. Using a 1 μA Xe beam will have an overall milling rate for silicon some 20X higher than a Ga beam operating at 65 nA. This paper will compare the benefits already seen using the Ga-based FIB-SEM approach to TSV metrology, with the improvements in throughput and time-to-data obtained by using the faster material removal capabilities of a FIB based on an ICP ion source. Plasma FIB (PFIB) is demonstrated to be a feasible tool for TSV plating void metrology.

Currently there are no in-line TSV (through silicon via) etch profile metrology tools suitable for use in high volume manufacturing. Cross-section SEM analysis can be utilized for process development, but it is a destructive technique. In our research, a dark-field optical microscope tool is developed to in-line non-destructively measure the via profile. It is capable of measuring images with high contrast between the measuring object and the surrounding background field. As the name implies, the background is dark and the measuring object is relatively bright. Thus, a tiny structure of object can be more clearly resolved compares to the conventional bright-field optical microscope method. Analysis algorithms are developed to analyze the bottom profile and the sidewall profile of the vias separately. In this paper, vias with CDs (critical dimensions) from 30 um to 200 um are measured, and the experimental results are verified by the cross-section SEM results.

We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

Currently, the performance of overlay metrology is evaluated mainly based on random error contributions such as precision and TIS variability. With the expected shrinkage of the overlay metrology budget to < 0.5nm, it becomes crucial to include also systematic error contributions which affect the accuracy of the metrology. Here we discuss fundamental aspects of overlay accuracy and a methodology to improve accuracy significantly. We identify overlay mark imperfections and their interaction with the metrology technology, as the main source of overlay inaccuracy. The most important type of mark imperfection is mark asymmetry. Overlay mark asymmetry leads to a geometrical ambiguity in the definition of overlay, which can be ~1nm or less. It is shown theoretically and in simulations that the metrology may enhance the effect of overlay mark asymmetry significantly and lead to metrology inaccuracy ~10nm, much larger than the geometrical ambiguity. The analysis is carried out for two different overlay metrology technologies: Imaging overlay and DBO (1st order diffraction based overlay). It is demonstrated that the sensitivity of DBO to overlay mark asymmetry is larger than the sensitivity of imaging overlay. Finally, we show that a recently developed measurement quality metric serves as a valuable tool for improving overlay metrology accuracy. Simulation results demonstrate that the accuracy of imaging overlay can be improved significantly by recipe setup optimized using the quality metric. We conclude that imaging overlay metrology, complemented by appropriate use of measurement quality metric, results in optimal overlay accuracy.

We report an analysis of measurements of overlay targets fabricated in a single lithography step in a resist film. With patterns printed in a single step the expected result is zero, providing a rare opportunity to qualify the measurement error completely. Our results allow validation of a complete model for this error, which includes precision and TIS terms that vary as 1/√L, where L is the total pattern length in each target. Removing the precision and TIS effects shows that the remaining errors, which are usually undetectable, also vary as 1/√L. This residual error is very small (0.1nm or less) for the very large targets normally used in scanner qualification, but exceed the ITRS goals for overlay measurement uncertainty in traditional image-based overlay targets smaller than 25x25μm. As the industry drives towards smaller overlay targets it is important to consider the impact on complete measurement uncertainty, and to maximize the information content of each target. We show that acceptable uncertainty in 10x10μm targets is possible using targets patterned with dense gratings that can be measured by both diffraction and imaging tools.

In this study, we proposed the concept of high order field-by-field correction for Matched Machine Overlay (MMO) error minimization and we have validated it through experiments. Because scanners have unique grid fingerprint, MMO value between machines is higher than the one of Single Machine Overlay (SMO). In some cases, the localized grid distortion mainly contributes to the MMO value. However, this localized grid distortion cannot be flatten by a normal correction method such as 10-parameter correction. Until now, in order to flat the localized grid distortion, ultimate correction capability can be realized by combining 6-parameter field-by-field correction and intra-field high order correction methods. However 6-parameter could be not enough to follow the diversity of local distortion. In this study, for further improvement of MMO, high order field-by-field correction capability was investigated and the results were compared. Base on simulation, we found that the field-by-field correction was a successful way to lower the MMO value of EUV vs. ArF immersion scanners. By experimental demonstration, it showed that field-by-field correction was more effective to correct localized grid distortion and the gain via high order model was about 0.5 nm. These results will be helpful to achieve the MMO specification for the next generation device.

Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are presented for target-sizes down to 10 × 10 μm². The μDBO technology enables selection of only the diffraction efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm² reference targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay metrology.

With the shrinkage of semiconductor device scales, advanced semiconductor industries face tremendous challenges in process control. As lithography and etch processes are pushed to get smaller dimensions, the overlay and wiggling control are hot issues due to the limiting of pattern performance. Many chip makers are using Double Patterning Technology (DPT) process to overcome design rule limitations but they are also concerned about overlay control. In DPT process, obtaining accurate overlay data by measuring overlay marks with traditional metrology is difficult because of the difference of shape and position between cell pattern and overlay marks. Cell to overlay mark miss-match will occur when there is lens aberration or mask registration error. Therefore, the best way to obtain accurate overlay data without error is to measure the real cell itself. The overlay of the cell array using DPT process can be measured by analyzing the relative position of the 2nd exposed pattern to the 1st exposed pattern. But it is not easy to clearly distinguish a 1st layer and 2nd layer in a patterned cell array image using CD SEM. The Design Based Metrology (DBM)-system can help identify which cell pattern is a 1st or 2nd layer, so overlay error between the 1st and 2nd layers at DPT process can be checked clearly. Another noticeable problem in advanced processing is wiggling. The wiggling of a pattern become severe by the etch process and must be controlled to meet electrical characteristics of what the semiconductor device requires. The 1st stage of wiggling control is to understand the level of wiggling which is crucial to device performance. The DBM-system also can be used for quantification of wiggling by determining specially designed parameters. In this paper we introduce overlay verification and wiggling quantification through new methodology for advanced memory devices.

A new method for indicating the image quality of overlay measurement is proposed in this paper. Due to the constraint of the overlay control tolerance, the overlay metrology requirement has become very stringent. Current indicators such as the total measurement uncertainty (TMU) are insufficient to guarantee a good overlay measurement. This paper describes two quality indicators, the contrast index (CI) and the asymmetry index (AI). The CI is a crucial quality indicator that affects the overlay accuracy greatly. The AI, based on an imaging process with modified cross-correlation operation, shows alignment mark robustness in both the x and the y directions. For determination of the best recipe, the box-in-box overlay marks are measured to obtain the images with different conditions. The conventional TMU indicators are used first to sieve out the better choices. Then the CI and AI can help to judge whether the overlay results are reliable and can be applied to monitoring of process variations.

The control of line-edge or line-width roughness (LER/LWR) is a challenge especially for future devices that are fabricated using extreme-ultraviolet lithography. Accurate analysis of the LER/LWR plays an essential role in this challenge and requires the noise involved in scanning-electron-microscope (SEM) images to be reduced by appropriate image processing prior to analyses. In order to achieve this, the authors simulated SEM images using the Monte-Carlo method and detected line edges in experimental and these theoretical images after noise filtering using new imageanalysis software. The validity of these simulation and software was confirmed by a good agreement between the experimental and theoretical results. In the case when the image pixels aligned perpendicular (crosswise) to line edges were averaged, the variance var(φ) that was additionally induced by the image noise decreased with the number N_PIX,X of averaged pixels but turned to increase for relatively large N_PIX,X's. Real LER/LWR, however, remained unaffected. On the other hand, averaging image pixels aligned parallel (longitudinal) to line edges not only reduced var(φ) but smoothed the real LER/LWR. As a result, the nominal variance of the real LWR, obtained using simple arithmetic, monotonically decreased with the number NPIX,L of averaged pixels. Artifactual oscillations were additionally observed in power spectral densities. var(φ) in this case decreased in an inverse proportion to the square root of N_PIX,L according to the statistical mechanism clarified here. In this way, image processing has a marked effect on the LER/LWR analysis and needs to be much more cared and appropriately applied. All the aforementioned results not only constitute a solid basis of but improve previous empirical instructions for accurate analyses. The most important instruction is to avoid the longitudinal averaging and to crosswise average an optimized number of image pixels consulting the equation derived in this study.

Photoresist shrinkage (a.k.a. line slimming) is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features [1][2][3][4][5]. In terms of metrology gauge metrics, it influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. This error source will furthermore be a factor in CDSEM metrology on such polymer materials into the era of EUV lithography, such that learning to work around this issue will continue to be necessary. Recent work has demonstrated improved understanding of the trends in the shrinkage response depending on electron beam and target parameters in the static measurement case [2][3][4][5][6]. Another recent work has highlighted a second mode of shrinkage that is apparent over time and progresses as a function of time between consecutive measurements, a form of "dynamic shrinkage" that appears to be activated by electron beam, in which the activated feature perpetually and logarithmically shrinks [7][8]. In this work, we will explore both the static and dynamic shrinkage behaviors of various EUV photoresists. The static shrinkage behaviors will be tested for compliance with the SEMATECH shrinkage model [5][6], and further studies will confirm whether or not the dynamic effects are observable. Knowledge of secondary trends in dynamic shrinkage will also be further explored, including how these vary with electron beam energy, activation dose, feature size, and other parameters.

Critical dimension measurement is the most essential metrology needed in nanofabrication processes and the practice is most commonly executed using SEMs for its flexibility in sampling, imaging, and data processing. In bit patterned media process development, nanoimprint lithography (NIL) is used for template replication and media fabrication. SEM imaging on templates provide not only individual dot size, but also information for dot size distribution, the location of dots, pitch and array alignment quality, etc. It is very important to know the SEM measurement limit since the feature nominal size is less than 20 nm and the dot feature size and other metrics will relate to the final media performance. In our work an analytical SEM was used. We performed and compared two imaging analysis approaches for metrology information. The SEM beam was characterized using BEAMETR test sample and software for proper beam condition setup. A series of images obtained on a 27 nm nominal pitch dot array patterns were analyzed by conventional brightness intensity threshold method and physical model based analysis using myCD software. Through comparison we identified the issues with threshold method and the strength of using model based analysis for its improvement in feature size and pitch measurement uncertainty and accuracy. TEM cross sections were performed as accuracy reference for better understanding the source of measurement accuracy deviation.

ArF lithography is still the main technology in the most advanced processes of semiconductor fabrication. Being able to reliably measure and characterize these lithographic processes in-depth is becoming more and more critical. Critical Dimension-Scanning Electron Microscope (CD-SEM) continues to be the work horse tool for both in-line critical dimension (CD) metrology and characterization of ArF photoresist pattern. CD shrink of ArF photoresist has been one of the major challenges for CD-SEM metrology, and it becomes more difficult to measure shrinkage accurately for smaller feature size than ~50nm. The authors have developed a new measurement technique of photoresist shrinkage which measures CD difference between shrunk and non-shrunk sites after etching. There are many imaging and image processing parameters in CD-SEM which need to be optimized to obtain small shrinkage and good precision. There is a trade-off relationship between shrinkage and precision, and a comprehensive and systematic methodology is required for optimization of parameters. The authors have developed an optimization method that uses Taguchi method, where only 18 experiments are required. We can predict shrinkage, precision and relative CD offset for any combination of measurement parameter settings used in the 18 experiments by Taguchi method, and these predicted data can be used for optimization. A new concept of secondary reference metrology is also introduced in this paper to reduce the number of measurement by a reference metrology tool.

Advanced integrated circuit (IC) manufacturing requires high quality metrology for process disposition and control in order to achieve high yields. As the industry advances in high volume manufacturing of 3x and 2x nm nodes with the associated advanced materials and complex structures, understanding and reducing film and critical dimension (CD) measurement uncertainty is more critical than ever. Optical film metrology is used for measurement of critical film parameters such as n & k, thickness and composition, while optical CD metrology is used for measurement of CD, sidewall angle (SWA), height, and other structure-related parameters. Both optical film and CD metrologies utilize advanced structure modeling that includes fitting parameters of the device stack for multiple layers simultaneously. These methods have been proven and established in both R&D and high volume manufacturing scenarios. As film stacks and structures become more complex and design tolerances shrink, however, additional parameters need to be included in the modeling, in some cases leading to reduced parameter precision and unwanted parameter correlation. In this paper we discuss a new methodology, Data Feed Forward, that utilizes multiple metrology steps, and the feed forward of the derived parameters to next metrology steps, for improved measurement sensitivity and quality. In addition, we discuss Data Feed Forward requirements for fab-wide implementation.

Diffraction-based overlay (DBO) technologies have been developed to address the overlay metrology challenges for 22nm technology node and beyond. Most DBO technologies require specially designed targets that consist of multiple measurement pads, which consume too much space and increase measurement time. The traditional empirical approach (eDBO) using normal incidence spectroscopic reflectometry (NISR) relies on linear response of the reflectance with respect to overlay displacement within a small range. It offers convenience of quick recipe setup since there is no need to establish a model. However it requires three or four pads per direction (x or y) which adds burden to throughput and target size. Recent advances in modeling capability and computation power enabled mDBO, which allows overlay measurement with reduced number of pads, thus reducing measurement time and DBO target space. In this paper we evaluate the performance of single pad mDBO measurements using two 3D targets that have different grating shapes: squares in boxes and L-shapes in boxes. Good overlay sensitivities are observed for both targets. The correlation to programmed shifts and image-based overlay (IBO) is excellent. Despite the difference in shapes, the mDBO results are comparable for square and L-shape targets. The impact of process variations on overlay measurements is studied using a focus and exposure matrix (FEM) wafer. Although the FEM wafer has larger process variations, the correlation of mDBO results with IBO measurements is as good as the normal process wafer. We demonstrate the feasibility of single pad DBO measurements with faster throughput and smaller target size, which is particularly important in high volume manufacturing environment.

We have created a model that uses discriminant function analysis to predict failures in etched hole patterning of the type that induces an open-contact failure by using critical dimension scanning electron microscope (CDSEM) measurement values of after-development resist hole patterning. The input variables of the best model were found to be the resist hole CD, the difference in resist hole CD between that of the 50% secondary electron (SE) threshold and that of the 20% SE threshold, and ellipticity. The model indicates that a tapered resist profile is one of the main causes of the open-contact failure in etched hole patterning. The model is applicable not only to lithography process optimization but also to lithography process control, where the focus center of optical exposure at resist patterning is determined not only from the perspective of resist CD but also from the perspective of suppressing the failures of etched hole patterning.

There are two competing costs that occur in off line semiconductor processing metrology. One is the cost of operating the metrology tool, and the other is the loss in terms of processing cost and yield due to the time lapse between the occurrence and the correction of a process fault. Virtual metrology (VM) is an alternative scheme which takes data produced by the processing tool in real time (e.g. plasma etching data during isolation trench formation) and predicts an outcome of the wafer (e.g. critical dimension of the trench) utilizing an empirical model. Although VM prediction quality is not as good as that of conventional metrology, it produces an immediate, low cost prediction for each wafer going through a process. In real life, we envision that practical metrology schemes will involve a synergistic blend of VM and actual metrology, the latter being used for the needed periodic recalibration of the VM empirical model. In this work, we formulate the costs associated with Type I and Type II errors that result from a blended metrology scheme, and propose a general framework that can be used to quickly lead to the optimal design of such schemes given the characteristics of the process in question. We also explore the effects of a faulty process (by means of mean shift) on the cost analysis.

High volume semiconductor manufacturing yields require that critical resist feature profile is continually controlled for uniformity and centering. One reason is the small working distance of high numerical aperture lenses. Indeed, reducing process windows require more precise dimensional control. The variation of the critical dimensions can generally be attributed to the lack of the focus and/or dose control. A methodology to control the two lithographic parameters and to construct a focus and dose budget for all components (tool, layer, resist, and reticle) has been developed. This paper presents a run-to-run control called FDO1 (Focus Dose Optimization) using in-line CD metrology. We have confirmed that this method controls the photoresist shape and the photoresist width accurately and reduces the CD variation for 28 nm devices by 50%.

CD Metrology plays a critical role in the successful disposition of a semiconductor patterning process and eventually a product. With the advancements in the semiconductor technology such as sub-22 nm nodes, advanced patterning processes such as double patterning, dual-damascene processes, EUV patterning and the complex 3D device architectures such as FinFET devices, via-in-trench, elongated contacts have challenged the current state of CD metrology in terms of capability, measurement quality and time-to-solution. For these nodes, either the CD-metrology solution does not exists or it's not meeting the requirements resulting in gaps. CD-AFM providing reference metrology for resist and dielectric patterns is limited by the probe geometry. Due to probe geometry limitations CD-AFM is challenged in measuring the true bottom CD (< 15 nm from bottom), sub-5 nm foot and undercut, sub-40 nm trenches, charged samples, small CD high aspect ratio structures like via in trench, deep trench (DT) and through silicon via (TSV), and various CDs of interest in the FinFET type 3D devices. TEM cross section is used as another reference metrology for dielectric patterns but it is subject to error in sample preparation (especially for contacts in sub-22 nm nodes) and limited statistics. CD-SEM and scatterometry which are workhorse metrology, needing reference metrology for measurement accuracy, also face challenge in measurement of advanced patterning. Therefore, there is a critical need to enhance current and develop new 3D CD metrology techniques for advanced patterning technology. This paper reports an innovative non-destructive 3D CD metrology solution based on nanomolding of the master structure (via in trench, charged sample, trench < 40 nm, FinFET and EUV patterns) followed by the CD-AFM measurements with potential to address various metrology gaps. Nanoscale molding of the master produces an inverted replica where the top CD and profile correspond to the bottom CD and profile of the master enabling the measurements using currently existing CD-AFM capabilities which otherwise is not possible. The paper reports the nanomolding optimization study exploring different molding materials and methods on a variety of master samples and structures where the current CDAFM capability is limited. CD-AFM measurements of the master and the mold are compared where the master can be measured via conventional CD-AFM to understand the accuracy of the nanomolding approach. Measurement of the common region in the master and molded replica allowed the self-referencing to ensure accuracy of the CD measurements. TEM cross section has been used as a secondary reference for additional validity of this approach. Successful molding of a small region of interest on a 300 mm wafer demonstrates the non destructive inline 3D CD metrology potential of nanomolding assisted CD-AFM 3D metrology. Molding-assisted metrology is faster and statistically robust compared to the TEM metrology and does not require to break the wafer. Molding of charged (buried) master sample with suitable polymer allows the accurate metrology of such samples. Nanomolding assisted measurement of CD in FinFET devices can help break the cross correlation of different parameters in scatterometry which is otherwise challenged in such cases. In summary, the innovative nanomolding assisted 3D CD-Metrology approach has shown the potential to enhance the CD-AFM capabilities as a non destructive physical 3D CD metrology solution and turn some of the red sections in the ITRS metrology roadmap to yellow or green. This is a major step in bridging the metrology gap posed by the advanced patterning technology.

In-line, non-destructive process control metrology of high aspect ratio (HAR) holes and trenches has long been a known gap in metrology. Imaging the bottoms of at-node size contact holes in oxide with aspect rations beyond 10:1 has not yet been demonstrated. Nevertheless, holes and trenches of 30:1, 40:1, or even 60:1 will soon enter production, with these etches being applied to various homogeneous and multi-layer stacks of Si and SiO2. The need comes from Moore's Law and increasing functional density on microchips, on which true 3D memory devices will soon be manufactured. These can take many different forms, but a common building block will be these ultra-HAR etched features. In this work, we show experimental results and simulations from the NIST JMONSEL program to assess the feasibility of measuring such features using both conventional low voltage scanning electron microscopy (SEM) and higher beam energies and low vacuum conditions to ameliorate charging. In our measurements, higher voltage SEM did not improve upon conventional critical dimension (CD)-SEM. Simulations suggest the reason is a failure to overcome a negative oxide potential. Although a signal can in principle be detected from the bottom of contact holes in typical imaging conditions in the CD-SEM, it is likely that it will be very small and possibly below the noise floor.

ITRS Roadmap requires defect size measurement below 10 nanometers and challenging classifications for both blank and patterned wafers and masks. Atomic force microscope (AFM) is capable of providing metrology measurement in 3D at sub-nanometer accuracy but has long suffered from drawbacks in throughput and limitation of slow topography imaging without chemical information. This presentation focus on two disruptive technology developments, namely high speed AFM and quantitative nanomechanical mapping, which enables high throughput measurement with capability of identifying components through concurrent physical property imaging. The high speed AFM technology has allowed the imaging speed increase by 10-100 times without loss of the data quality. Such improvement enables the speed of defect review on a wafer to increase from a few defects per hour to nearly 100 defects an hour, approaching the requirements of ITRS Roadmap. Another technology development, Peak Force Tapping, substantially simplified the close loop system response, leading to self-optimization of most challenging samples groups to generate expert quality data. More importantly, AFM also simultaneously provides a series of mechanical property maps with a nanometer spatial resolution during defect review. These nanomechanical maps (including elastic modulus, hardness, and surface adhesion) provide complementary information for elemental analysis, differentiate defect materials by their physical properties, and assist defect classification beyond topographic measurements. This paper will explain the key enabling technologies, namely high speed tip-scanning AFM using innovative flexure design and control algorithm. Another critical element is AFM control using Peak Force Tapping, in which the instantaneous tip-sample interaction force is measured and used to derive a full suite of physical properties at each imaging pixel. We will provide examples of defect review data on different wafers and media disks. The similar AFM-based defect review capacity was also applied to EUV masks.

Photoacoustic spectroscopy is a powerful tool for characterizing thin films. In this paper we demonstrate a new photoacoustic technique that allows us to precisely characterize the mechanical properties of ultrathin films. We focus an ultrafast laser onto a nano-patterned thin film sample, launching both surface acoustic waves (SAWs) and longitudinal acoustic waves (LAWs). Coherent extreme ultraviolet pulses are then used to probe the propagation dynamics of both the SAWs and LAWs. The resulting photoacoustic signal on both short (picosecond) and long (nanosecond) time scales yields important information. In the first 100ps, a fast oscillation followed by an echo signal corresponds to LAWs traveling inside the nanostructures and the thin film, from which the LAW velocities in the two materials can be extracted. On longer time-scales, SAW oscillations are observed. By combining the measured SAW frequency with the wavelength (determined by the nanostructure period) the SAW velocity can be accurately determined, even for very short wavelength surface acoustic waves with very small penetration depths. Using this technique, the elastic properties, including the Young's modulus and Poisson ratio for the thin film, can be obtained in a single measurement, this technique can be extended to sub-10nm thin films.

Semiconductor see-through-silicon metrology and inspection applications use traditionally InGaAs based cameras due to perfect spectral sensitivity. But InGaAs cameras do not carry equivalent advantages as Silicon based imagers such as pixel size, pixel array resolution and through-put etc. This paper first reviews the novel technologies which dramatically enhance silicon imagers' sensitivity for this see-through silicon application. Inspection through-put is analyzed based on multiple system implementation:, start-stop scan mode vs. continuous scan mode, 2D cameras vs. TDI line scan cameras, against to traditional InGaAs camera based continuous scan platform. The simulation data shows that systematic through-put based on 2D silicon cameras can be competitive to today's InGaAs system, while TDI line scan system can be much faster than system based on near future's high resolution and high speed InGaAs cameras.

Optical scatterometry is crucial to advanced nodes due to its ability of non-destructively and rapidly retrieving accurate 3D profile information.^{1, 2, 3} In recent years, an angle-resolved polarized reflectometry-based scatterometry which can measure critical dimensions, overlay, and focus in single shot has been developed.^{4, 6, 20} In principle, a microscope objective collects diffracted light, and pupil images are collected by a detector. For its application of calibrating lithography models, the pupil images are fit to a database pre-characterized usually by rigorous electromagnetic simulation to estimate dimensional parameters of developed resist profiles.⁵ The estimated dimensional parameters can then be used for lithography model calibration. In this work, we propose a new method which directly utilizes the pupil images to calibrate lithography models without needing dimensional parameter estimation. To test its feasibility and effectiveness by numerical simulation, a reference lithography process model is first constructed with a set of parameter values complying with ITRS. A to-be-calibrated process model is initialized with a different set of parameter values from those of the reference model. Rigorous electromagnetic simulation is used to obtain the pupil images of the developed resist profiles predicted by both process models. An optimization algorithm iteratively reduces the difference between the pupil images by adjusting the set of parameter values of the to-be-calibrated process model until the pupil image difference satisfies a predefined converging criterion. This method can be used to calibrate both rigorous first-principle models for process and equipment development and monitoring, and fast kernel-based models for full-chip proximity effect simulation and correction. Preliminary studies with both 1D and 2D aperiodic and periodic layouts indicate that when the pupil image difference is minimized, the lithography model can be accurately calibrated.

As the feature sizes continue to shrink, more overlay metrology data are needed to meet tighter overlay specifications which ensure high device yield. This study investigates the advantages of process corrections to overlay errors using various reduced measurement wafer schemes, and the improvement in yield that is realized using optimized overlay correction models. The capacitor layer of a 4x node DRAM product is chosen for verifying the sampling schemes in the experiment, because overlay errors of this layer are sensitive to device yield. The test wafers are split into five groups; four groups are sampled using various schemes and overlay correction models, and one group has a programmed overlay error. The post-correction overlay residuals in full wafer, baseline sampling and optimized sampling agree closely with predictions that are based on raw measurements. A scheme with iHOPC (intrafield high order process correction) partial third-order terms with a CPE (correction per exposure) function provides the best overlay performance. The averaged device yields of reduced sampling schemes are comparable with those of the full wafer scheme, however the reduction of the number of measurements that is made in optimized sampling reduce the metrology tool time by 26% from that required using the current scheme of factory. Therefore, the cost of metrology can be further reduced by applying the proposed optimized sampling map in the routine operations of fab.

Distributions of via Depth and bottom CD for TSV wafer have been studied by scanning interference microscopy (Unifire 7900, Nanometrics Inc.). We plotted whole wafer maps for each via depth and bottom CD and found useful relationship between them (i.e. via depth is in inverse proportion to bottom CD in general). Average values of via depth and bottom CD are ~60um and ~4um and their standard deviation values are 1.28% and 5.14% respectively. We also demonstrated kinds of defects at via top (or bottom) which can cause disturbance of total via count during 3D inspection. Our results can be a good introduction to scanning interference tool as a monitoring tool for TSV high volume manufacturing.

Improving Critical Dimension Uniformity (CDU) for spacer double patterning features is a high priority for double patterning technology. In spacer double patterning the gaps between the spacers are established through various processes (litho, etch, deposition) with different process fingerprints and the CDU improvement of these gaps requires an improved control solution. Such a control solution is built upon two pillars: metrology and a control strategy. In this paper Spacer Patterning Technology CDU control using an angle resolved scatterometry tool is evaluated. CD results obtained with this scatterometer on CDU wafers are measured and the results are correlated with those from the traditional CD-SEM. CD wafer fingerprints are compared before and after applying the advanced control strategy and CDU improvements are reported. Based on the results it is concluded that scatterometry qualifies for a spacer process CDU control loop in a manufacturing environment.

This work presents software tools that enable engineers to make relevant SEM measurement decisions in the EDA environment, presented in the optimal context for the engineer, and pass them seamlessly into the SEM environment. We present the tools and interfaces leveraged in this solution and explore the benefits of enabling OPC modeling engineers to make metrology-related decisions within the OPC environment. New opportunities for automation of metrologyrelated OPC tasks are also discussed.

The 22nm Spacer Self Aligned Double Patterning (SADP) process developed at Applied Materials' Maydan Technology Center was used to characterize small particle defects in the four critical steps of the process flow: Lithography, APF Etch, Spacer Deposition, Spacer Open. Small Particle defect contamination poses a risk to yield in each of the SADP process steps (Lithography, Deposition and Etch) and requires an understanding of their sources and impact on each subsequent step. The defect inspection was carried out using two different inspection platforms; DFinder^TM which is designed for detection of 3D defects and UVision ^TM 3 which is designed for detection of 2D defects. Small particle defects (smaller than 60nm), in the Lithography and APF Etch process steps were shown to become "killer" defects at the Spacer Open step. More study is needed to develop inspection strategies based on a wider range of defect types.

The main difficulty related to DoseMapper correction is to generate an appropriate CD datacollection to feed DoseMapper and to generate DoseRecipe in a user friendly way, especially with a complex process mix. We could heavily measure the silicon and create, in feedback mode, the corresponding DoseRecipe. However, such approach in a logic fab becomes a heavy duty due to the number of different masks / product / processes. We have observed that process CD variability is significantly depending on systematic intrawafer and intrafield CD footprints that can be measured and applied has generic pre-correction for any new product/mask process in-line. The applied CD correction is based on a CD (intrafield: Mask + Straylight & intrawafer: Etch Bias) variability "model" handled by the FAB APC (Advanced Process Control). - Individual CD profile correction component are generated "off-line" (1) for Intrafield Mask via automatic CD extraction from a Reticle CD database (2) for Intrafield Straylight via a CD "model" (3) for Intrawafer Etch Bias via engineering input based on process monitoring. - These CD files are handled via the FAB APC/automation system which is remotely taking control of DoseMapper server via WEB services, so that CD profiles are generated "off-line" (before the lot is being processed) and stored in a profile database while DoseRecipes are created "real-time" on demand via the automation when the lot comes to the scanner to be processed. DoseRecipe and CD correction profiles management is done via the APC system. The automated DoseRecipe creation is now running since the beginning of 2011 contributing to bring both intrafield and intrawafer GATE CDu below 1nm 3sigma, for 45/40 & 28nm nodes.

As DRAM design advances from planar to vertical integration, process control of the recessed gate, generated by etching after patterning in vertical DRAM, is very critical because of the impact on device electrical characteristics and subsequent effect on yield. 3D Scatterometry Critical Dimension (3D SCD) technology is a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing. In this paper, the latest KLA-Tencor AcuShape^TM modeling software with 3D SCD capability is used in the modeling and solution development, and the SpectraShape^TM 8660 is used for data collection and CD measurement. Recess gate measurements were taken in the active cell area having a non-orthogonal structure. The SCD measurement results were successfully confirmed to correlate well with cross-section Scanning Electron Microscope (X-SEM) and electrical performance data.

Scatterometry-based metrology measurements for advanced gate after-develop inspection (ADI) and after-etch inspection (AEI) structures have been well proven¹. This paper discusses the metrology challenges encountered in implementing a production-worthy methodology for accurately measuring gate ADI middle CD (MCD) and sidewall angle (SWA) to monitor focus and exposure dose. A Multi-Target Measurement (MTM) methodology on KLA-Tencor's SpectraShape 8810 was evaluated on its ability to characterize and measure FEM (Focus Exposure Matrix) and EM (Exposure Matrix) wafers. The correlation of MCD and SWA to the focus and exposure dose was explored. CD-SEM measurements were used as a reference to compare the accuracy of scatterometry MCD measurements. While there was no reference tool available to compare scatterometry SWA measurements, the SWA and focus tracking on the FEM wafer were verified. In addition to the MTM methodology evaluation, a fleet of four SpectraShape 8810 tools was evaluated to measure the fleet's capability for in-line monitoring in high volume manufacturing. The final results confirmed that the Multi-Target Measurement approach on SpectraShape 8810 is an effective solution for gate ADI metrology and the robust fleet matching performance would enable in-line monitoring use.

At the 28nm node using 300mm wafers, oxide step height in STI CMP transient gate after-etch inspection (TG AEI) wafers is a critical parameter that affects device performance and should be monitored and controlled. For production process control of this kind of structure, a metrology tool must utilize a non-destructive measurement technique, and have high sensitivity, precision and throughput [1]. This paper discusses a scatterometry-based measurement method for monitoring critical dimension step height in STI CMP instead of traditional measurement methods such as atomic force microscopy (AFM). The scatterometry tool we used for our investigations was the KLA-Tencor SpectraShape 8810, which is the most recent model of the spectroscopic critical dimension (SCD) metrology tools that have been implemented in production for process control of TG AEI structures. AFM was used as a reference metrology technique to assess the accuracy performance of the SpectraShape8810. The first objective of this paper is to discuss the best azimuth angle and floating parameters for scatterometry measurement of the step height feature in TG AEI wafers. Second, this paper describes the tool matching performance of SpectraShape 8810 and correlation to AFM determined using a DOE of TG AEI wafers.

Diffraction Based Overlay (DBO) is widely evaluated by numerous authors, results show DBO can provide better performance than Imaging Based Overlay (IBO). However, DBO has its own problems. As well known, Modeling based DBO (mDBO) faces challenges of low measurement sensitivity and crosstalk between various structure parameters, which may result in poor accuracy and precision. Meanwhile, main obstacle encountered by empirical DBO (eDBO) is that a few pads must be employed to gain sufficient information on overlay-induced diffraction signature variations, which consumes more wafer space and costs more measuring time. Also, eDBO may suffer from mark profile asymmetry caused by processes. In this paper, we propose an alternative DBO technology that employs a dedicated overlay mark and takes a rigorous modeling approach. This technology needs only two or three pads for each direction, which is economic and time saving. While overlay measurement error induced by mark profile asymmetry being reduced, this technology is expected to be as accurate and precise as scatterometry technologies.

With the introduction of 450 mm wafers, which are considerably larger than the currently largest wafers of 300mm, handling with side grippers is no longer possible and backside grippers are required. Backside gripping increases the possible buildup of particles on the backside of the wafers with possible cross-contamination to the front-side. Therefore, regular backside cleaning is required. Three vacuum compatible cleaning methods were selected. Tacky rollers and highvoltage cleaning were selected for particles and plasma cleaning for molecular layers. A test-bench was designed and constructed implementing these three cleaning methods. The first experiments show promising results for the plasma cleaner and the tacky roller.

As overlay budget continues to shrink, an improved analysis of the different contributors to this budget is needed. A major contributor that has never been quantified is the accuracy of the measurements. KLA-Tencor developed a quality metric, that calculates and attaches an accuracy value to each OVL target. This operation is performed on the fly during measurement and can be applied without affecting MAM time or throughput. Using a linearity array we demonstrate that the quality metric identifies targets deviating from the intended OVL value, with no false alarms.

Controlling overlay performance has become one of the key lithographic challenges for advanced integrated circuit manufacturing. Overlay error budgets of 4 nm in the 2x node require careful consideration of all potential error sources. Overlay data modeling is a key component for reducing systematic wafer and field variation, and is typically based on ordinary least squares (OLS) regression. OLS assumes that each data point provides equally reliable information about the process variation. Weighted least squares (WLS) regression can be used to improve overlay modeling by giving each data point an amount of influence on the model which depends on its quality. Here we use target quality merit metrics from the overlay metrology tool to provide the regression weighting factors for improved overlay control in semiconductor manufacturing.

As the cost of manufacturing high-end semiconductors continues to increase, the value of combining and streamlining metrology steps also increases. The two critical metrology steps for litho control are 1) overlay and 2) CD. In this study, the authors demonstrate the capability of just such a combination CD and Overlay metrology solution to improve not only the cost of manufacturing but also the quality of data and information feedback for better scanner control in high volume production. The authors demonstrate how using imaging and scatterometry technology on a single platform can provide a comprehensive litho control solution for both CD and overlay in the litho module. In the study, the authors will use full stack wafers from an advanced process node running in high volume manufacturing. Specifically, data will be generated using PROLITH for lithographic simulations for optimal target designs and then empirical data will be collected using the Archer 300 LCM from which optimal target selection and system performance will be determined and validated on wafers using this advanced process technology.

Overlay control in advanced integrated circuit (IC) manufacturing is becoming one of the leading lithographic challenges in the 3x and 2x nm process nodes. Production overlay control can no longer meet the stringent emerging requirements based on linear composite wafer and field models with sampling of 10 to 20 fields and 4 to 5 sites per field, which was the industry standard for many years. Methods that have emerged include overlay metrology in many or all fields, including the high order field model method called high order control (HOC), and field by field control (FxFc) methods also called correction per exposure. The HOC and FxFc methods were initially introduced as relatively infrequent scanner qualification activities meant to supplement linear production schemes. More recently, however, it is clear that production control is also requiring intense sampling, similar high order and FxFc methods. The added control benefits of high order and FxFc overlay methods need to be balanced with the increased metrology requirements, however, without putting material at risk. Of critical importance is the proper control of edge fields, which requires intensive sampling in order to minimize signatures. In this study we compare various methods of overlay control including the performance levels that can be achieved.

The metrology and inspection of contact hole layers is an extremely complex task. At feature sizes below 45 nm, an aspect ratio higher than 1:10 is required. SEM metrology and electron beam defect inspection both face extreme difficulties due to the fact that the secondary electrons from the bottom of the contact holes are absorbed by the walls and do not reach the detector. In this paper, the pre-charging of a large area before taking images of the hole was explored. An understanding of the physics involved in contrast formation and optimization of the system setup may improve SEM imaging. Pre-charge and imaging were simulated using CHARIOT Monte Carlo software with varying pre-charge and observation conditions. It was found that at specific parameters in the e-beam setting, image contrast is sufficient for metrology and defect inspection. The simulations involved high aspect ratio contact holes without defects, as well as with two types of defects: the remaining under-etched layer at the bottom, and a particle defect at the bottom. The experimental results of the e-beam defect inspection and CD-SEM of the contact holes involving the flood beam are presented. The results of the simulation qualitatively agreed with the measured data.

Development of an advanced design node for NAND flash memory devices in semiconductor manufacturing requires accelerated identification and characterization of yield-limiting defect types at critical front-end of line (FEOL) process steps. This enables a shorter development cycle time and a faster production ramp to meet market demand. This paper presents a methodology for detecting defects that have a substantial yield impact on a FEOL after-develop inspection (ADI) layer using an advanced broadband optical wafer defect inspector and a scanning electron microscope (SEM) review tool. In addition, this paper presents experimental data that demonstrates defect migration from an ADI layer to an after-clean inspection (ACI) layer, and provides clear differentiation between yield-impacting critical defects and noncritical defects on the layers. The goal of these studies is to determine the feasibility of implementing an inspection point at ADI. The advantage of capturing yield-limiting defects on an ADI layer is that wafers can be reworked when an excursion occurs, an option that is not always possible for ACI layers. Our investigation is divided into two parts: (1) Inspection of an ADI layer with high sensitivity to find an accurate representation of the defect population and to gain understanding on the propagation of defects from the ADI layer to the ACI layer; and, (2) Inspection of an ACI layer to develop an understanding of unique defects generated by the ACI process step. Overall, this paper discusses the advantages of baselining defectivity at ADI process levels for accelerated development of advanced design node memory devices.

Overlay continues to be one of the key challenges for lithography in semiconductor manufacturing, especially in light of the accelerated pace of device node shrinks. This reality will be especially evident at 20nm node where DPL and multi-layer overlay will require 4nm or less in overlay control across many critical layers in order to meet device yield entitlements. The motivation for this paper is based on improving DPL overlay control in face of the high complexity involved with multi-layer overlay requirements. For example, the DPL-2nd-litho layer will need to achieve tight registration with the DPL-1st-litho layer, and at the same time, it will need to achieve tight overlay to the reference-litho layer, which in some cases can also be a DPL layer. Of course, multi-level overlay measurements are not new, but the combination of increased complexity of multi-DPL layers and extremely challenging overlay specifications for 20nm node together will necessitate a better understanding of multi-level overlay control, specifically in terms of root cause analysis of multi-layer related overlay errors and appropriate techniques for improvement In this paper, we start with the identification of specific overlay errors caused by multi-layer DPL processing on full film stack product wafers. After validation of these findings with inter-lot and intra-lot controlled experiments, we investigate different advanced control techniques to determine how to optimize overlay control and minimize both intra-lot and inter-lot sources of error. A new approach to overlay data analysis will also be introduced that combines empirical data with target image quality data to more accurately determine and better explain the root cause error mechanism as well as provide effective strategies for improved overlay control.

For our first impression, defect inspector is considered to be a non-destructive equipment in an advanced Fab. When doing ADI inspection, only defect check is performed and photoresist keeps the same without any physical or chemical change. But is this true for now? I don't think so. Many phenomena or evidences tell us - in advanced processes, defect inspection does play more at the inspection step than what we expected before. Inspection can no longer be regarded as non-destructive. Some thing really happens when ADI inspection is executed. As a result, product suffers yield drop eventually. In the experiment below, different ArF resists among various processes are tested and investigated. Some ArF resists do react on UV light and contraction occurs. Basic studies and experiments based on our limited resources, equipment and time are carried out. We try to find out the mechanism and prove it.

The earliest semiconductor device manufacturing employed optical microscopes for measurement and control of manufacturing process. The introduction of Critical Dimension Scanning Electron Microscope (CD-SEM) in 1984 provided a tremendous increase in capability for process monitoring and has been the standard for in-line metrology for over 25 years. The advantages of CD-SEM are highly accurate and stable measurement reproducibility at very specific locations throughout the device. The evolution of CD-SEM in Metrology has included improved resolution, development of advanced measurement and pattern recognition algorithms, all required by performance improvement demands from the market. Current conventional metrology using in-line CD-SEM involves measuring about ten points per wafer (one or more points per one chip). At a magnification of over x150k (Field of View is about 1μm²). In contrast, the area of measurement pattern on chip is much larger than the area of CD-SEM measurement (mm² : (on chip) versus μm² : (CDSEM measurement)). This would mean that the result of CD-SEM measurement is influenced by local pattern variation. The very stringent requirements placed on in-line Metrology for the last couple of technology nodes has produced an additional metrology methodology, beyond the CD-SEM, that involves large area measurements with very high precision for the most critical levels. We will refer to this methodology as "Macro Area Measurements". We reported the applicability of using a CD-SEM Macro Area Measurements methodology in SPIE2011 (797124). In the results, we were able to validate a new methodology that we called "Macro Area Measurement" which is demonstrated to successfully detect small process variations with the same throughput and reduced damage to the pattern. This time, we investigated the additional applicability of using a CD-SEM Macro Area Measurement methodology in this paper. The areas investigated focused on the following points: 1) Measurement repeatability related to CD-SEM measurement 2) Optimization of the measurement parameters using new function 3) Verification of Macro Area Measurement with a leading -edge device In the results, we are able to validate "Macro Area Measurements methodology which is demonstrated to successfully detect further small process variations with the almost same throughput and reduced damage to pattern.

Nanoemitters (NEs) are a promising replacement for electron sources in producing field emission CD-SEMs and CDTEMs. So far, NEs have been fabricated by, e.g. carbon nanotubes or nanowhiskers of conductive materials. Here, we present a new method to manufacture NEs using electron beam induced processing (EBIP) - a method well established in the nanofabrication of super sharp probes for scanning probe microscopy - and show their unique performance. NEs manufactured by EBIP combine a high density, diamond-like carbon core (HDC/DLC) with high aspect ratio and tip sharpness, and a highly conductive coating. The EBIP process allows for the batch-fabrication of NEs at larger scales with desired sharpness, shape, mechanical stability and conductivity. NEs, which can easily be mounted into existing SEM/TEM assemblies, have been operated for > 5.000 h without any sign of degradation at a comparatively constant beam current of 3 μA, wherein maximum current oscillations of 10% occurred, while current oscillations were less than 3% over a time span of several minutes. Due to the cold operating temperature and small tip radius, the resolution improved up to 30% compared to a standard Schottky thermal field emitter. The improvement is significant in the low voltage range below 5 kV.

There is a need for pristine vacuum environments free of carbon contamination in many lithography tools. Carbon is a particularly irksome contaminant due to its ubiquity and its reactivity with energetic electron or EUV photon beams. When residual hydrocarbons land on a surface that is being impinged by an energetic beam, they will crack and reform as less mobile deposits. Carbon buildup cause loss in image resolution resulting in line width measurement increases during multiple CD-SEM scans, and on EUV optics it can lead to lower reflectivity and throughput of a lithography system. A new downstream plasma cleaner has been developed to clean larger chambers at lower pressures and higher RF plasma power (50W) and operates efficiently with current turbomolecular pumps. Cleaning rates can be measured by using a quartz crystal microbalance (QCM) with its surface previously contaminated with hydrocarbons. Rates have been measured at over 1 nm/minute at a distance of over 0.5 m from the plasma source. The cleaner can be used with room air, oxygen gas mixtures, and hydrogen gas. Although it is slightly larger than the currently available Evactron® De-Contaminator, it still has a compact footprint which allows it to be easily installed on lithography tools. This paper will explore the operation of the new plasma cleaner, examining the effect of the cleaning rate due to changes in various conditions including power, pressure and distance from the plasma source.

Roughness transfer from Litho to Etch has been evaluated. The impact of Line width roughness (LWR) or Line edge roughness (LER) is getting larger with shrink of semiconductor devices. In this study, the roughness measurement by using a single frame SEM image was brought in to avoid resist shrinkage, and image enhance technique is used to compensate low S/N ratio in this one frame image. CD-AFM was used as reference, and LWR measured by CD-AFM was compared to the results of one frame enhanced image taken by CD-SEM. And roughness spectrum analysis was used for evaluation of roughness characteristics taken by CD-SEM and CD-AFM, and its transition by resist shrink or by etching process. It was enabled to observe the resist roughness profile with minimum shrink by using one frame enhanced image, then roughness transfer between Litho and Etch was evaluated by comparing in exactly the same position as pre- and post-etch. As a result, it was confirmed that transferred roughness by etching was remaining the peak and valley profile in resist observed by CD-SEM, but the roughness amplitude was reduced in higher frequency domain. This result consists with the roughness characteristics comparison from Litho to Etch. This also means roughness characteristics analysis shows the actual nanoscopic event.

Line-end gap measurement for OPC calibration is a challenge for metrology. Even for CD-SEM, the rounded shape of the line end makes it very difficult to measure precisely. We have presented preliminary results of the application of scatterometry to these challenging structures using an angle resolved polarized scatterometer: ASML YieldStar [1]. In this paper, the exercise was extended to several different structures combining multiple line-end gap situations. Systematic comparison with CD-SEM is performed and discussed. Lithographic behavior of the main parameters is analyzed. Strengths and limits of the technique will be shown. Once validated, the metrology is used to build an OPC model and correct our test vehicle.

Effectively patterning the intended design on the wafer for all possible geometries allowed by the design rule document is one of the most critical challenges for semiconductor manufacturing. Despite new lithography techniques like OPC, double patterning and the latest patterning simulation methods, and on-wafer evaluation using brightfield inspection and SEM review tools, patterning problems still occur and can result in a major delay in the qualification of a technology or product. Of particular concern are shorts and opens that cause product chip failure. Initial discovery of yield issues when a chip is being functionally tested is highly undesirable. A system for in-line, die to database (D2DB) comparison using E-beam inspection has been developed to address this risk. This system offers a substantial new line of defense against these patterning issues. The D2DB system is described along with a methodology for applying it for pattern fidelity inspection. Some examples illustrating the system operation are presented.

Scatterometry has been proven to be effective in critical dimension (CD) and sidewall angle (SWA) measurements with good precision and accuracy. In order to study the effectiveness of scatterometry measurement of line edge roughness (LER), calibration samples with known LER have to be fabricated precisely. The relationship between ITRS LER specifications and the feature dimension design of the LER calibration samples is discussed. Electron-beam-direct-write lithography (EBDWL) has been widely used in nanoscale fabrication and is a natural selection for fabricating the designed calibration samples. With the increasingly demanding requirement of lithography resolution in ITRS, the corresponding LER feature of calibration samples becomes more and more challenging to fabricate, even for EBDWL. Proximity effects in EBDWL due to electron scattering can cause significant distortion of fabricated patterns from designed layouts. Model-based proximity effect correction (MBPEC) is an enhancement method for EBDWL to precisely define fine resist features. The effectiveness of MBPEC depends on the availability of accurate electron-beam proximity effect models, which are usually described by point spread functions (PSFs). In this work, a PSF in a double- Gaussian function form at a 50 kV accelerating voltage, an effective beam size, and a development threshold energy level of the resist are calibrated with EBDWL exposure tests. Preliminary MBPEC results indicate its effectiveness in calibration sample fabrication.

It is getting harder to minimize feature size to satisfy bit growth requirement. 3D NAND flash memory has been developed to meet bit growth requirement without shrinking feature size. To increase the number of memory cells per unit area without shrinking feature size, we should increase the number of stacked film layers which finally become memory cells. Wafer warpage is induced by the stress between film and wafer. Both of film stress and wafer warpage increase in proportion to stacked film layers, and the increase of wafer warpage makes CD uniformity worse. Overlay degradation has no relation with wafer warpage, but has indirect relation with film stress. Wafer deformation in film deposition chamber is the source of overlay degradation. In this paper, we study the reasons why CD uniformity and overlay accuracy are affected by film stress, and suggest the methods which keep CD uniformity and overlay accuracy safe without additional processes.

As feature sizes decrease, requirements on critical dimension uniformity have become very strict. To monitor variations in lithography process and perform advanced process control it is important to establish a fast and accurate measurement technique for characterizing critical dimension, sidewall angle and height of the resist profile. Various techniques for feature measurement such as CD-SEM, AFM, FE-SEM, and scatterometry have been developed. Among these techniques, scatterometry has both high accuracy and a non-deconstructive measurement modality. It thus provides advantages of low-cost, high throughput, and robustness. Angle-resolved scatterometry has already been shown to provide in-line feedback information necessary for tight process control. In present paper, we introduce a novel angle-resolved scatterometer with pupil optimization. The intensity distribution of the incident light in the pupil plane is optimized considering the feature and the image sensor response properties, which improve the measurement performance of the scatterometer. A first order analysis of measurement sensitivity at different polarization conditions is carried out on resist-coated wafers with 45nm and 22nm features using Rigorous Coupled- Wave analysis (RCWA). Based on the criteria defined as the sum of the absolute difference of the relative intensity values between the nominal and varied conditions in the pupil, the sensitivity of the new technique and traditional scatterometer is compared. Simulation results show that, for 45nm feature, the sensitivity in s and p-polarization is increased by 400% and 300% respectively. While for 22nm feature, the sensitivity is increased by 200% and 130%. Reproducibility of measurement is also analyzed on 45nm and 22nm features using a Monte Carlo method and models for detector noise. Comparison of reproducibility for CD, sidewall angle, and resist height measurement is demonstrated.

Strong correlation between de-protection induced thickness reduction and amplified chemical reaction in the exposed area of the chemically amplified resist (CAR) during post-exposure bake (PEB) has been established. The optical properties of the resist film due to the thickness reduction can be detected using a spectroscopic ellipsometer. In this paper, a rotating polarizer spectroscopic ellipsometer is developed and a proposed control scheme is presented for signature profiles matching. With the implementation of the control scheme, wafer-towafer critical dimensions (CD) uniformity is improved by 5 times.

As the pattern size shrinkage, it becomes more important to control the critical size of various pattern shapes at a semiconductor production line. Recently, in a semiconductor process with 20 nm nodes size or less the common optical and even EB inspection tool have considerable limitation to detect critical physical defects. From these backgrounds, we have developed the high-sensitivity fixed point inspection tool based on Review-SEM as the product accomplishment judgment tool for below 10nm size defects on critical size devices. We examined the basic performance of this inspection tool, optimized inspection parameters including beam condition and image processing. Then, the defect detection performance was evaluated using various real advanced memory device containing various critical defects. In this paper, we report these results and show the effectiveness of this inspection tool to the advanced memory devices.

OPC model calibration techniques that use SEM contours are a major reason for the modern day improved fitting efficiency in complex mask design compared to conventional CD-based calibration. However, contour-based calibration has a high computational cost and requires a lot of memory. To overcome this problem, in conventional contour-based calibration, the SEM contour is sampled uniformly at intervals of several nanometers. However, such sparse uniform sampling significantly increases deviations from real CD values, which are measured by CD-SEM. We also have to consider the shape errors of 2D patterns. In general, the calibration of 2D patterns requires higher frequency sampling of the SEM contour than 1D patterns do. To achieve accurate calibration results, and while considering the varied shapes of calibration patterns, it is necessary to set precise sampling intervals of the SEM contour. In response to these problems, we have developed a SEM contour sampling technique in which contours are sampled at a non-uniform rate with arbitrary mask shapes within the allowable sampling error. Experimental results showed that the sampling error rate was decreased to sub-nm when we reduced the number of contour points.

The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.

The library search is a widely used method for reconstruction of diffraction structures in optical scatterometry. In library search, an optimized set of geometrical parameters for a diffraction structure can be achieved by searching for a best match between the measured signatures and the simulated ones. The search speed and accuracy is the key to guarantee the effectiveness of this method, and some a priori geometrical model is necessary. Once the actual geometrical model of a measured signature is different from the model used in the establishment of library, the search result will be meaningless. Therefore, the classification and recognition of the geometrical profile for a measured signature is critical. In this paper, we develop two support vector machine (SVM) classifiers to deal with issue. One classifier is used to identify the geometrical profile of a diffraction structure from its measured signature, and the other one is to map the whole search range of the identified diffraction structure into a smaller one. By using some reliable and mature search algorithms, we can fast and accurately reconstruct the geometry profile of a diffraction structure in this optimized small range. Simulation and experiment have demonstrated that the SVM classifiers can identify the geometrical profile of one-dimensional trapezoidal gratings accurately, and the SVM-based library search strategy can achieve a fast and accurate extraction of parameters for diffraction structures.

The shrinking of design rule requires the short wavelength light used in the optical inspection system. However, the existence of the condition that the long wavelength light becomes effective for the defect detection in line/space structure is known. Calculation results using numerical simulation showed that the probe light can penetrate to the line/space structure depending on the polarization even though the light has long wavelength. A new model was introduced to make theoretical explanation of this abnormal behavior of long wavelength light and the mechanism of optical penetration was clarified. In this model, the averaged extinction coefficient was calculated in consideration of the wavelength and the period of the line/space structure. Using this model, the transmittance was calculated and compared with simulations. The fact that the calculation result is agreed with the simulations showed this model's utility. This result shows that the probe light can reach to the bottom of line/space structure in the inspection system for semiconductor devices even though the light has long wavelength. It means that the long wavelength light can be used effectively for the defect detection of the micro periodic structure in the semiconductor inspection system.

Shrinkage behavior caused by a single-line scan of an electron beam over a photoresist line was studied, including shrinkage distribution in the photoresist-line direction. As single-line scan is the minimum unit of controllable electron-beam irradiation during scanning-electron-microscope-image (SEM-image) processing, the minimum amount of shrinkage should be observed in the condition. A new method for evaluating the minute amount shrinkage and the shrinkage distribution caused by a single-line scan was developed. According to the results of evaluations with this method, the shrinkage of a 50-nm-wide photoresist line caused by a single-line scan is less than 0.1 nm under landing energies of 200, 300, and 500 eV and probe current of 8 pA. This shrinkage is more than ten times smaller than the typical amount of shrinkage caused by a standard two-dimensional scan. This result indicates the possibility of a significant reduction of photoresist shrinkage during SEM measurements. The evaluations also show that the shrinkage caused by a single-line scan distributes more than about 30 nm in the photoresist-line direction, which is wider than the simulated electron-scattering range. Moreover, the evaluations show that the shrinkage distribution is narrower at higher position of the photoresist-line. This tendency suggests that the wide shrinkage-distribution does not stem from the distribution of the back-scattered electrons (BSEs) which enter the side wall of the photoresist line from the spaces nearby, because the incidents of BSEs distribute wider at higher position of the photoresist-line. Hence, shrinkage occurs in a wider region of the photoresist line than the region where electrons (including directly incident electrons and BSEs) reach. This result suggests that in order to interpret the photoresist-shrinkage mechanism it is important to clarify how the microscopic volume-reduction caused by electron-molecule interactions is integrated into macroscopic photoresist-pattern deformation. An elastic deformation is a plausible mechanism for this macroscopic photoresist-shrinkage process.

As transistor dimensions shrinks, the requirement for wafer critical dimensions control is becoming increasingly challenging. The intra-field critical dimension uniformity (CDU) of the features on the reticle is one of the many sources of wafer CD variation. In this paper, we study how the CDU on the reticle can be obtained by using the intensity information collected during reticle inspection (iCDU^TM) on the KLA-Tencor TeraScan reticle inspection tool. The collected CDU information of the reticle is then applied as an intra-field dose correction function to improve wafer intra-field CD uniformity. Using this method of extracting the reticle CDU from the intensity information allows for simple integration into a high-volume production environment and an improved capability for intra-field CDU correction without the need to expose any wafers for CD measurement nor any GDS design information. The ability to apply iCDU on prototype devices on first pass run can also accelerate device development.

Result of the testing contain the reference surface errors and test surface errors in the high-accuracy Phase shifting interferometer which test the relative phase between the two surface. The test accuracy can be achieved by removing the error of reference surface. In this case, one of body of so-called absolute testing must be used which can test the systematic errors, including the reference surface, of the instrument to be used to improve the test accuracy. The accuracy of the interferometer needs different methods to determine in the high accuracy testing. Even-Odd function method and rotation shear method is introduced in this paper. We use the Zygo interferometer Verifire Asphere to do the experiment and analyze the errors caused by data processing and interpolation. The result of the experiment can determine the accuracy of our arithmetic.

We report on theoretical and experimental investigations into electrostatic chuck designs for use in future e-beam lithography on 450 mm Silicon wafers. Ultra-low thermal expansion glass (ULE) and Si infiltrated Silicon Carbide (SiSiC) designs were evaluated by finite element modeling, subject to a mass budget of 8 kg. In addition to massive chucks, light-weight designs were created by applying bore holes through the chuck body below its surface. Considerable chuck bending under gravity is observed with classical kinematic 3-point mounts. Out-of-plane distortions of about 1250 (650) nm and 400 (200) nm for the massive and light-weight designs of ULE (SiSiC), respectively, were calculated. The corresponding surface in-plane distortions for a chucked Si wafer of standard thickness 925 μm amount to about 3 (1.6) nm for the massive and 1 (0.5) nm for light-weight designs of ULE (SiSiC), respectively. By using the standard 6^th order polynomial correction upon e-beam writing, these values can be reduced to ≤0.7 nm for the massive designs with both materials. Various pin-pattern configurations for an ideally flat chuck surface were adopted to determine resulting wafer bending under the influence of electrostatic forces. At a typical electrostatic pressure of about 18 kPa, a square pin pattern of pin-pitch 3.5 mm and pin-diameter 0.5 mm results in wafer in-plane distortions <0.5 nm, which is considered tolerable for obtaining the desired total overlay accuracy of <4 nm. The pin structure manufacturing process for a corresponding ULE chuck surface was experimentally tested and verified. A nearly elliptic ULE plate, slightly larger than the wafer, was structured with a Chromium hard-mask and subjected to low pressure reactive ion etching to generate the pin-pattern. A homogeneity of about 7 % was obtained for the etching process, which is fully sufficient with respect to resulting variations in electrostatic attraction.

In the process of lithography for semiconductor devices, the disuse of semiconductor devices is caused by the several hundred nanometer size pollutants generated by photochemical reactions, which is called by the haze. Therefore, the real time visual detection system is needed to inspect hazes before the existence of disuse semiconductor devices. We proposed and experimentally confirmed the concept of the real time scanning detection system for the defect on the photo-mask by interference fringes generated between the light wave scattered by small defect on the photo-mask and the reflected light wave from the rest area of the front surface.

Overlay performance has been a critical factor for advanced semiconductor manufacturing for years. Over time these requirements become more stringent as design rules shrink. Overlay mark design and selection are the first two steps of overlay control, and it is known that different overlay mark designs will have different responses to process conditions. An overlay mark optimized for traditional process might not be suitable for SADP (self-aligned double patterning) technology due to changes in lithography and etching process conditions. For instance, the traditional BIB (box-in-box) target defined by the core mask becomes a template structure in SADP flow, the pitch and cycle of the overlay mark is further changed after spacer formation and core film removal hence the mark recognition and robustness have been challenging for the subsequent process layers. The comprehensive study on the methodology of overlay mark design and selection is still not available for SADP process. In this paper, various types of overlay marks were designed to comply with the SADP process to get rid of the weaknesses of traditional targets. TMU (total measurement uncertainty) performance was adopted to determine the optimal overlay marks for meeting production overlay control requirements in SADP process flow. The results have suggested the segmented marks outperform to non-segmented marks on image contrast as well as TMU.

The demands on atomic force microscopy (AFM) as a reference technique for precisely determining surface properties and structural designs of multiple patterns in the semiconductor industry are steadily increasing. With the aim to meet ITRS requirements and simultaneously improve the accuracy of AFM-based critical dimension (CD) measurements at constant resolution, the AFM tip more and more becomes a factor crucially determining the AFM performance. In this context, AFM tip limitations are given by lack of sharpness with too large tip radii/diameter, insufficient wear resistance, and high total cost, which does not conform to production environment needs. One technical approach to overcome these tip limitations is provided by electron beam induced processing (EBIP), which allows for manufacturing AFM tips of desired sharpness, shape, and mechanical stability. Here, we present T-shape-like 3D-AFM tips made of bulk amorphous, high density diamond-like carbon (HDC/DLC), and compare their performance and wear resistance to standard silicon tips. We show the advantages of this approach for the semiconductor industry, in particular on AFM3D technology in order to answer to sub-28 nm nodes requirements, and present tips with 15 nm diameter at 10 nm vertical edge height.

Physical vapor deposition (PVD) aluminum films present unique challenges when detecting particulate defects with a Surface Scanning Inspection System (SSIS). Aluminum (Al) films 4500Å thick were deposited on 300mm particle grade bare Si wafers at two temperatures using a Novellus Systems INOVA® NExT,.. Film surface roughness and morphology measurements were performed using a Veeco Vx310® atomic force microscope (AFM). AFM characterization found the high deposition temperature (TD) Al roughness (Root Mean Square 16.5 nm) to be five-times rougher than the low-TD Al roughness (rms 3.7 nm). High-TD Al had grooves at the grain boundaries that were measured to be 20 to 80 nm deep. Scanning electron microscopy (SEM) examination, with a Hitachi RS6000 defect review SEM, confirmed the presence of pronounced grain grooves. SEM images established that the low-TD filmed wafers have fine grains (0.1 to 0.3 um diameter) and the high-TD film wafers have fifty-times larger equiaxed plateletshape grains (5 to 15 um diameter). Calibrated Poly-Styrene Latex (PSL) spheres ranging in size from 90 nm to 1 μm were deposited in circular patterns on the wafers using an aerosol deposition chamber. PSL sphere depositions at each spot were controlled to yield 2000 to 5000 counts. A Hitachi LS9100® dark field full wafer SSIS was used to experimentally determine the relationship of the PSL sphere scattered light intensity with S-polarized light, a measure of scattering cross-section, with respect to the calibrated PSL sphere diameter. Comparison of the SSIS scattered light versus PSL spot size calibration curves shows two distinct differences. Scattering cross-section (intensity) of the PSL spheres increased on the low-TD Al film with smooth surface roughness and the low-TD Al film defect detection sensitivity was 126 nm compared to 200 nm for the rougher high- TD Al film. This can be explained by the higher signal to noise attributed to the smooth low-TD Al. Dark field defect detection on surface scanning inspection systems is used to rapidly measure defectivity data. The user generates a calibration curve on the SSIS to plot the intensity of the light scattering derived at each National Institute of Standards and Technology (NIST) certified PSL deposition spot that was deposited. It is not uncommon for the end user to embark upon the time consuming process of attempting to "push" the maximal SSIS film specific sensitivity curve beyond the optical performance capability of the SSIS. Bidirectional reflectance distribution function (BRDF) light scattering modeling was utilized as a means of determining the most appropriate polarity prior to the SSIS recipe creation process. The modeling utilized the Al refractive index (n) and extinction coefficient (k) and the SSIS detector angles and laser wavelength. The modeling results allowed predetermination of the maximal sensitivity for each different Al thickness and eliminate unnecessary recipe modification trial-and-error in search of the SSIS maximal sensitivity. The modeling accurately forecasted the optimal polarization and maximal sensitivity of the SSIS recipe, which, by avoiding a trial and error approach, can result in a substantial savings in time and resources.

Jet-and-Flash Imprint Lithography (J-FIL) has demonstrated capability of high-resolution patterning at low costs. For accurate pattern transfer using J-FIL, it is necessary to have control of the residual layer thickness (RLT) of cured resist underneath features. Variation in RLT leads to critical dimension variation, thereby degrading device performance. Substrate nanotopography and feature density variation are two unavoidable sources of variation in RLT uniformity. The first part of this paper demonstrates the effect of these parameters on RLT variation. Through experiments and modeling, it has been observed that flatter wafers with lower nanotopography and thinner RLT lead to better RLT uniformity. However, for studying RLT variation, accurate metrology is critical. Currently, all metrology is done using destructive cross-section scanning electron microscopy (SEM), which may not be sufficient for process control. To this end, nondestructive optics-based methods, including the Through-focus Scanning Optical Microscopy (TSOM) method have been explored in this paper. Simulations reveal the potential to measure mean RLT, RLT variation, and uncertainty in feature dimension to an accuracy of 1 nm. Experimental validation and calibration are works in progress. Subsequent development of this technique can lead to a viable in-line metrology solution for RLT underneath features.

A novel through-focus scanning optical microscopy (TSOM) method that yields nanoscale information from optical images obtained at multiple focal planes will be used here for nanoparticle dimensional analysis. The TSOM method can distinguish not only size differences but also shape differences among nanoparticles. Size evaluation based on simulations will be presented along with experimental data for nanoparticles and nanodots with sizes below 100 nm. Size determination using an experimentally created library will also be presented.

As the semiconductor industry advances to smaller design rules, Photoresist performance is critical for the tight lithography process. Critical Dimension (CD), Side Wall Angle (SWA) and Photoresist height, which are critical for the final semiconductor patterning, depend on the Photoresist chemistry. Each Photoresist batch has to be qualified to verify that it can achieve the required quality specifications. Photoresist qualification is done by exposing Photoresist and monitoring outcome after developing. In this work, Archer 300LCM scatterometry-based Optical CD (OCD) was evaluated using Dow 193 Immersion Top Coat Free Photoresist and Anti Reflection Layers (ARL). As part of the sensitivity analysis, changes in Photoresist thickness, ARL thickness and Photoresist formulation were evaluated. Results were compared to CD-SEM measurements. The CD sensitivity was evaluated on two grating dense line and space features with nominal Middle CD (MCD) values of 37nm and 75nm. Sensitivity of the OCD for Photoresist parameters was demonstrated.

Many of the challenges in improving operational processes in wafer fabrication, such as throughput and on-time delivery, can be impacted by scheduling. While individual area predictive scheduling can provide significant benefit, especially for bottleneck tool sets, coordinated multiple area scheduling on top of individual area scheduling can address all of the challenges from a fab-wide optimized perspective. Thus we must leverage the technology of a predictive area scheduler into a fab-wide coordinated WIP optimization solution. In this coordinated solution the area predictive schedulers draw from the same set of scheduling services to achieve area objectives. These objectives are governed by a higher layer fab-level WIP management plan that determines how individual areas should be optimized to support overall fab scheduling objectives. In considering the implementation plan for predictive scheduling, the bottleneck process, which is oftentimes lithography, has been targeted first. As we expand the scheduling solution, we must focus on other potential bottleneck processes, and also look at processes that interact with the bottleneck process. The predictive multi-area scheduling and WIP optimization approach presented provides a framework for addressing individual area predictive scheduling as part of a coordinated effort to optimize scheduling to achieve fab-wide objectives.

We evaluate diffraction-based overlay (DBO) metrology using two test wafers. The test wafers have different film stacks designed to test the quality of DBO data under a range of film conditions. We present DBO results using traditional empirical approach (eDBO). eDBO relies on linear response of the reflectance with respect to the overlay displacement within a small range. It requires specially designed targets that consist of multiple pads with programmed shifts. It offers convenience of quick recipe setup since there is no need to establish a model. We measure five DBO targets designed with different pitches and programmed shifts. The correlations of five eDBO targets and the correlation of eDBO to image-based overlay are excellent. The targets of 800nm and 600nm pitches have better dynamic precision than targets of 400nm pitch, which agrees with simulated results on signal/noise ratio. 3σ of less than 0.1nm is achieved for both wafers using the best configured targets. We further investigate the linearity assumption of eDBO algorithm. Simulation results indicate that as the pitch of DBO targets gets smaller, the nonlinearity error, i.e., the error in the overlay measurement results caused by deviation from ideal linear response, becomes bigger. We propose a nonlinearity correction (NLC) by including higher order terms in the optical response. The new algorithm with NLC improves measurement consistency for DBO targets of same pitch but different programmed shift, due to improved accuracy. The results from targets with different pitches, however, are improved marginally, indicating the presence of other error sources.

In a conventional lithography process with Al film structure, the photo resist pattern is removed by two methods: wet etch or wet etch combine with dry strip process. There were some problems in these kinds of processes. Pattern collapsed after wet etch process due to the photo resist (PR) adhesion capability reduced. Contact angle can be the index to measure the adhesion capability. So as to prevent the pattern collapsed issue, a high-temperature plasma treatment step was added after wet etch. But it induces another issue. IC devices fabrication in Al interconnect process, 0.5wt% Cu is generally used in Al film deposition for better Al electron migration performance. The high-temperature Plasma with high potentiality of CuAl₂ precipitation, which will form a residue cause the metal line bridge induce yield loss. In this paper, we modify the rework procedure and lower the plasma processing temperature to the "room temperature" to prevent the pattern collapsed issue and the CuAl₂ precipitation. The modified rework procedure is not only improved the defect, WAT and yield, but also reduce the cycle time of resist remove process.

This article presents results from a heuristic automated defect classification algorithm for reticle inspection that mimics the classification rules. AHDC does not require CAD data, thus it can be rapidly deployed in a high volume production environment without the need for extensive design data management. To ensure classification consistency a software framework tracks every defect in repeated inspections. Through its various image based derived metrics it is shown that such a system manages and tracks repeated defects in applications such as haze induced defect growth.