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Design for Manufacturability through Design-Process Integration V
Editor(s): Michael L. Rieger
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Volume Details

Volume Number: 7974
Date Published: 25 March 2011

Table of Contents
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Front Matter: Volume 7974
Author(s): Proceedings of SPIE
Moore's Law in the innovation era
Author(s): Mark Bohr
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Using templates and connectors for layout pattern minimization in 20nm and below technology nodes
Author(s): Tejas K. Jhaveri; Andrzej J. Strojwas
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Lithographic variation aware design centering for SRAM yield enhancement
Author(s): Kanak Agarwal
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Multi-selection method for physical design verification applications
Author(s): Salma Mostafa; J. Andres Torres; Peter Rezk; Kareem Madkour
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Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation
Author(s): Keisuke Hirabayashi; Naohiro Kobayashi; Hidemichi Mizuno; Tomoo Onodera; Tsuyoshi Oguro; Philippe Hurat; Arindam Chatterjee; Koichi Seki
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Lithography aware design optimization using ILT
Author(s): Jaeyoon Jeong; Seokyun Jeong; Changhoon Ahn; Yongsun Jang; Sukjoo Lee; Thomas Cecil; Donghwan Son; Tatung Chow; David Kim
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Is manufacturability with double patterning a burden on designer? Analyses of device and circuit aspects
Author(s): Rasit Onur Topaloglu
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A new fast resist model: the Gaussian LPM
Author(s): Chris A. Mack
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Methodology for balancing design and process tradeoffs for deep-subwavelength technologies
Author(s): Ioana Graur; Tina Wagner; Deborah Ryan; Dureseti Chidambarrao; Anand Kumaraswamy; Jeanne Bickford; Mark Styduhar; Lee Wang
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Double patterning compliant logic design
Author(s): Yuangsheng Ma; Jason Sweis; Chris Bencher; Yunfei Deng; Huixiong Dai; Hidekazu Yoshida; Bimal Gisuthan; Jongwook Kye; Harry J. Levinson
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Single exposure contacts are dead. Long live single exposure contacts!
Author(s): Henning Haffner; Martin Ostermayr; Hideki Kanai; Chan Sam Chang; Bradley Morgenfeld; Jujin An; Meng Luo; Haoren Zhuang
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Integrated model-based retargeting and optical proximity correction
Author(s): Kanak B. Agarwal; Shayak Banerjee
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Validation of process cost effective layout refinement utilizing design intent
Author(s): Sachiko Kobayashi; Atsuhiko Ikeuchi; Kazunari Kimura; Toshiya Kotani; Satoshi Tanaka; Suigen Kyoh; Shimon Maeda; Soichi Inoue
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New double patterning technology for direct contact considering patterning margin and electrical performance
Author(s): Soo-Han Choi; A-Young Je; Jae-Seok Yang; Chul-Hong Park; Sang-Hoon Lee; Young-Kwan Park
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Performance and manufacturability trade-offs of pattern minimization for sub-22nm technology nodes
Author(s): Vyacheslav V. Rovner; Tejas Jhaveri; Daniel Morris; Andrzej Strojwas; Larry Pileggi
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Decomposition-aware standard cell design flows to enable double-patterning technology
Author(s): Lars Liebmann; David Pietromonaco; Matthew Graf
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Layout decomposition of self-aligned double patterning for 2D random logic patterning
Author(s): Yongchan Ban; Alex Miloslavsky; Kevin Lucas; Soo-Han Choi; Chul-Hong Park; David Z. Pan
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A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation
Author(s): Mark C. Simmons; Jae-Hyun Kang; Youngkeun Kim; Joung Il Park; Seung weon Paek; Kee-sup Kim
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Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks
Author(s): Ashesh Parikh; Siew Dorris; Tom Smelko; Walter Walbrick; Pushpa Mahalingam; John Arch; Kent Green; Vishal Garg; Peter Buck; Craig West
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Self-aligned double-patterning (SADP) friendly detailed routing
Author(s): Minoo Mirsaeedi; J. Andres Torres; Mohab Anis
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Partial least squares-preconditioned importance sampling for fast circuit yield estimation
Author(s): Yu Ben; Costas J. Spanos
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Applications of DBV (design-based verification) for steep ramp-up manufacture
Author(s): Tae Heon Kim; Dae-Han Han; Yong-Hyeon Kim; Min-Chul Han; Hong-Ji Lee; Ae-Ran Hong; Yoon-Min Kim; In-Ho Nam; Yong-Jik Park; Kyung-Seok Oh
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Rerouting and guided-repair strategies to resolve lithography hotspots
Author(s): Reinhard März; Kai Peter; Kay Engelhardt
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Accurately predicting copper interconnect topographies in foundry design for manufacturability flows
Author(s): Daniel Lu; Zhong Fan; Ki Duk Tak; Li-Fu Chang; Elain Zou; Jenny Jiang; Josh Yang; Linda Zhuang; Kuang Han Chen; Philippe Hurat; Hua Ding
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Characterization of the performance variation for regular standard cell with process nonidealities
Author(s): Hongbo Zhang; Yuelin Du; Martin D. F. Wong; Kai-Yuan Chao
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Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching
Author(s): Jen-Yi Wuu; Fedor G. Pikus; Malgorzata Marek-Sadowska
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Fast process-hotspot detection using compressed patterns
Author(s): Peter Rezk; Wael ElManhawy
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In-design DFM CMP flow for block level simulation using 32nm CMP model
Author(s): Naya Ha; Jinwoo Lee; S. W. Paek; Kee Sup Kim; Kuang Han Chen; Aaron Gower-Hall; Tamba Gbondo-Tugbawa; Philippe Hurat
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Hotspot detection using image pattern recognition based on higher-order local auto-correlation
Author(s): Shimon Maeda; Tetsuaki Matsunawa; Ryuji Ogawa; Hirotaka Ichikawa; Kazuhiro Takahata; Masahiro Miyairi; Toshiya Kotani; Shigeki Nojima; Satoshi Tanaka; Kei Nakagawa; Tamaki Saito; Shoji Mimotogi; Soichi Inoue; Hirokazu Nosato; Hidenori Sakanashi; Takumi Kobayashi; Masahiro Murakawa; Tetsuya Higuchi; Eiichi Takahashi; Nobuyuki Otsu
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The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate
Author(s): Jeong-Geun Park; Sang-wook Kim; Seong-Bo Shim; Sung-Soo Suh; Hye-Keun Oh
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Defect-aware reticle floorplanning for EUV masks
Author(s): Abde Ali Kagalwalla; Puneet Gupta; Duck-Hyung Hur; Chul-Hong Park
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Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes
Author(s): Eitan Shauly; Allon Parag; Hafez Khmaisy; Uri Krispil; Ofer Adan; Shimon Levi; Sergey Latinski; Ishai Schwarzband; Israel Rotstein
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Aerial image retargeting (AIR): achieving litho-friendly designs
Author(s): Ayman Yehia Hamouda; James Word; Mohab Anis; Karim S. Karim
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Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs
Author(s): Philippe Hurat; Rasit O. Topaloglu; Ramez Nachman; Piyush Pathak; Jac Condella; Sriram Madhavan; Luigi Capodieci
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Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device
Author(s): Yu-Jin Pyo; Soo-Han Choi; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo; Gyu-Tae Kim
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