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Design for Manufacturability through Design-Process Integration IV
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Volume Details

Volume Number: 7641
Date Published: 10 March 2010

Table of Contents
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Front Matter: Volume 7641
Author(s): Proceedings of SPIE
Application of the cost-per-good-die metric for process design co-optimization
Author(s): Tejas Jhaveri; Umut Arslan; Vyacheslav Rovner; Andrzej Strojwas; Larry Pileggi
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Taming the final frontier of optical lithography: design for sub-resolution patterning
Author(s): Lars W. Liebmann; Jongwook Kye; Byung-Sung Kim; Lei Yuan; Jean-Pierre Geronimi
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Realizing a 45-nm system on chip in the age of variability
Author(s): Laurent Le Cam; Andy Appleby; Philippe Hurat; Benoit Carpentier; Kuang-Han Chen; Nishath Verghese
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Joint-optimization for SRAM and logic for 28nm node and below
Author(s): Staf Verhaegen; Michael C. Smayling; Peter De Bisschop; Bart Laenens
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Layout pattern minimization for next-generation technologies
Author(s): Tejas Jhaveri; Andrzej J. Strojwas
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16nm with 193nm immersion lithography and double exposure
Author(s): Valery Axelrad; Michael C. Smayling
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Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels
Author(s): Scott W. Jessen; Steven L. Prins; James W. Blatchford; Brian W. Dillon; Christopher J. Progler
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3D physical modeling for patterning process development
Author(s): Chandra Sarma; Amr Abdo; Todd Bailey; Will Conley; Derren Dunn; Sajan Marokkey; Mohamed Talbi
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Systematic failure debug and defective pattern extraction for FPGA product yield improvement
Author(s): Cinti Chen; Joe W. Zhao; Ping Zhang; Raymond Y. Xu
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Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell
Author(s): Yongchan Ban; Yuansheng Ma; Harry J. Levinson; Yunfei Deng; Jongwook Kye; David Z. Pan
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Process sizing aware flow for yield calculation
Author(s): Chi-Min Yuan
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Foundry verification of IP and incoming designs for manufacturing variability
Author(s): Li-Fu Chang; Julia Fu; Josh Yang; Elain Zou; Philippe Hurat; Nishath Verghese; Hua Ding
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45nm transistor variability study for memory characterization
Author(s): Kun Qian; Costas J. Spanos
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Variability aware timing models at the standard cell level
Author(s): Eric Y Chin; Cooper S Levy; Andrew R. Neureuther
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Measurement and optimization of electrical process window
Author(s): Tuck-Boon Chan; Abde Ali Kagalwalla; Puneet Gupta
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Development of a design intent extraction flow for mask manufacturing
Author(s): Kokoro Kato; Masakazu Endo; Tadao Inoue; Masaki Yamabe
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Design intention application to tolerance-based manufacturing system
Author(s): Sachiko Kobayashi; Satoshi Tanaka; Suigen Kyoh; Shimon Maeda; Masanari Kajiwara; Soichi Inoue; Koji Nakamae
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45nm-generation parameter-specific ring oscillator monitors
Author(s): Lynn T.-N. Wang; Nuo Xu; Tsu-Jae King Liu; Andrew R. Neureuther
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A kernel-based DFM model for process from layout to wafer
Author(s): Yiwei Yang; Zheng Shi; Litian Sun; Ye Chen; Zhijuan Hu
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Stat-LRC: statistical rules check for variational lithography
Author(s): Aswin Sreedhar; Sandip Kundu
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DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction
Author(s): Jie Yang; Norma Rodriguez; Olivier Omedes; Frank Gennari; Ya-Chieh Lai; Viral Mankad
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Demonstrating the benefits of template-based design-technology co-optimization
Author(s): Lars Liebmann; Jason Hibbeler; Nathaniel Hieter; Larry Pileggi; Tejas Jhaveri; Matthew Moe; Vyacheslav Rovner
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The role of strong phase shift masks in Intel's DFM infrastructure development
Author(s): Richard Schenker; Vivek Singh; Yan Borodovsky
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Decomposition strategies for self-aligned double patterning
Author(s): Yuansheng Ma; Jason Sweis; Chris Bencher; Huixiong Dai; Yongmei Chen; Jason P. Cain; Yunfei Deng; Jongwook Kye; Harry J. Levinson
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Towards nanoimprint lithography-aware layout design checking
Author(s): Hayden Taylor; Duane Boning
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Using a highly accurate self-stop Cu-CMP model in the design flow
Author(s): Kyoko Izuha; Takashi Sakairi; Shunichi Shibuki; Monalisa Bora; Osama Hatem; Ruben Ghulghazaryan; Norbert Strecker; Jeff Wilson; Noritsugu Takeshita
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Improving copper CMP topography by dummy metal fill co-optimizing electroplating and CMP planarization
Author(s): Li-Fu Chang; Zhong Fan; Daniel Lu; Alex Bao
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Library-based performance-based OPC
Author(s): Siew-Hong Teh; Chun-Huat Heng; Arthur Tay
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Tracking of design related defects hidden by random defectivity in production environment
Author(s): J. C. Le Denmat; V. Charbois; L. Tetar; M. C. Luche; G. Kerrien; F. Robert; E. Yesilada; F. Foussadier; L. Couturier; L. Karsenti; M. Geshel
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Device performances analysis of standard-cells transistors using silicon simulation and build-in device simulation
Author(s): Eitan N. Shauly; Allon Parag; Uri Krispil; Israel Rotstein
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Detection of OPC conflict edges through MEEF analysis
Author(s): Li-Fu Chang; Chang-Il Choi; Guojie Cheng; Abhishek Vikram; Gary Zhang; Bo Su
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Practical use of the repeating patterns in mask writing
Author(s): Masahiro Shoji; Tadao Inoue; Masaki Yamabe
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EM calibration based on Post OPC layout analysis
Author(s): Aswin Sreedhar; Sandip Kundu
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OPC on a single desktop: a GPU-based OPC and verification tool for fabs and designers
Author(s): Ilhami Torunoglu; Ahmet Karakas; Erich Elsen; Curtis Andrus; Brandon Bremen; Pururav Thoutireddy
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A GPU-based full-chip inverse lithography solution for random patterns
Author(s): Ilhami Torunoglu; Ahmet Karakas; Erich Elsen; Curtis Andrus; Brandon Bremen; Boris Dimitrov; Jeffrey Ungar
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Line width roughness effects on device performance: the role of the gate width design
Author(s): V. Constantoudis; E. Gogolides; G. P. Patsis
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