With the continuous shrinkage of feature dimensions on IC in the semiconductor industry, the measurement uncertainty is becoming one of the major components that have to be controlled in order to guarantee sufficient production yield. Already at the R&D level, we have to cope up with the accurate measurements of sub-40nm dense trenches and contact holes coming from 193 immersion lithography or E-Beam lithography. By using top-down CD-SEM it is currently impossible to extract profile information. Moreover, electron proximity effect leads to non-negligible CD bias in the final measurements. To enable measurement of challenging dimensions with better measurement and reduced measurement uncertainty we have explored and fine tuned an alternative 3D-AFM mode (so-called DT mode) for CD measurements purpose. Theoretically, this mode is supposed to be dedicated only for height measurement but for certain applications it could be extended to reach the nanometer scale accuracy of CD-measurements employing certain optimized scan parameters. In this paper, we will present and discuss results obtained related to the use of this particular mode for CD measurement purpose versus conventional 3D-AFM CD Mode that shows important limitations for aggressive trenches dimensions measurements. We will also present some results related to the use of advanced 3D-AFM tips (typically of 28nm diameter) that have been used with the enhanced DT mode parameters. Example of applications will be shown with typical sub-45nm trenches measurements dedicated to advanced lithography process development that will demonstrate that we have succeed to push ahead the limit of the 3D-AFM technology in measuring the tight dimensions that would allow to continue its use for current and upcoming technology nodes. Finally, we introduce the concept of hybrid metrology in order to smartly use the benefit of reference metrology (i.e 3D-AFM) through the optimization of CD-SEM algorithm that could be used for example for OPC model optimization.

In this paper we demonstrate the robustness of the Mueller matrix polarimetry used in multiple-azimuth configuration. We first demonstrate the efficiency of the method for the characterization of small pitch gratings filling 250 μm wide square boxes. We used a Mueller matrix polarimeter directly installed in the clean room has motorized rotating stage allowing the access to arbitrary conical grating configurations. The projected beam spot size could be reduced to 60x25 μm, but for the measurements reported here this size was 100x100 μm. The optimal values of parameters of a trapezoidal profile model, acquired for each azimuthal angle separately using a non-linear least-square minimization algorithm, are shown for a typical grating. Further statistical analysis of the azimuth-dependent dimensional parameters provided realistic estimates of the confidence interval giving direct information about the accuracy of the results. The mean values and the standard deviations were calculated for 21 different grating boxes featuring in total 399 measured spectra and fits. The results for all boxes are summarized in a table which compares the optical method to the 3D-AFM. The essential conclusion of our work is that the 3D-AFM values always fall into the confidence intervals provided by the optical method, which means that we have successfully estimated the accuracy of our results without using direct comparison with another, non-optical, method. Moreover, this approach may provide a way to improve the accuracy of grating profile modeling by minimizing the standard deviations evaluated from multiple-azimuths results.

Advanced 193 nm lithographic processes will require defocus control for product wafers in order to meet CD and profile requirements in the future. Dose control is already required. The interaction of product wafer materials with lithography requires additional controls beyond tool monitoring. While scatterometry has demonstrated excellent ability to extract effective defocus and dose information from monitor wafers, the addition of product film stacks introduces several issues for this technique. The additional complexity of model generation and the sensitivity to under-layer thickness and optical property variation are among these. A CDSEM technique for lithography focus monitoring overcomes these issues provided it has sufficient precision and relative accuracy. In this paper, we report on comparative studies of two CDSEM techniques. One technique uses angled e-beam to better view the sidewall for edge width measurement. The angle of the beam from normal incidence is considerably larger than previously explored thereby enabling sensitive measurements on shallower structures. The other technique introduces new target designs particularly suited to CDSEM measurement that have enhanced sensitivity to focus and dose. Implementation of these techniques requires expanded sampling during the course of a single measurement in order to suppress roughness. The small target size of these structures enables applications with targets in product kerf and embedded within the circuit. In summary, these methods enable the measurement of dose and focus variations on product wafers.

As optical lithography pushes towards the 32nm node and as the k₁ factor moves toward 0.25, scanner performance and operational stability are the key enablers to meet device scaling requirements. Achieving these requirements in production requires stable lithography tools and processes. Stable performance is tracked with respect to pattern to pattern overlay, nominal focus and critical dimension uniformity (CDU). Within our paper we will characterize the intrinsic lithographic performance of the scanner and will discuss a new method of machine control to improve the stability and thus the overall performance of the lithographic solution. This is achieved by measuring specific monitor wafers, modeling the results by a new software algorithm and constantly feeding back corrective terms to the scanner. Diffraction-based optical dimensional scatterometry was selected because of its precision, its ability to measure overlay and focus with a single metrology recipe and its capability to generate greater amounts of measurement data in a shorter time period than other metrology techniques and platforms. While monitor wafer performance can be indicative, we will discuss the impact of the new control loop on product. We will take a closer look at possible interactions with the existing process control loops and work through the configuration of both internal and fab control loops. We will show improvements in the focus performance on product wafers by using scatterometry as well. Most importantly we will demonstrate that the newly implemented control loop resulted in a significant improvement of the CD and overlay performance of critical product layers. This had a very positive impact on overall process variation and the rework rate at lithography.

We have developed the new technology to measure focus variations in a field or over the wafer quickly for exposure tool management. With the new technology, 2-dimensional image(s) of the whole wafer are captured with diffraction optics, and by analyzing the image signal(s), we are able to get a focus map in an exposure field or over the entire wafer. Diffraction-focus curve is used instead of a CD-focus curve to get the focus value from the image signal(s). The measurements on the production patterns with the production illumination conditions are available. We can measure the field inclination and curvature from the focus map. The performance of the new method was confirmed with a test pattern and production patterns.

A powerful new inspection technology enables the excursion control of fast patterning processes. Full images of 300mm wafers are captured and processed to extract CD uniformity information of contact hole and line-space patterns. Suitable masking filters are applied to process and analyze the information from active logic and/or memory areas separately. Characteristic process tool signatures can then be detected based on die, exposure field and wafer-level pattern variations. Based on inspection times of a few seconds per wafer, rapid monitoring of 100% of processed wafers at full surface is feasible. CD-imaging is demonstrated for the monitoring of key patterning process steps in gate formation. Use cases for stand-alone, integrated and smart sampling strategies are discussed.

As critical dimension (CD) control requirements increase and process windows decrease, it is now of even higher importance to be able to determine and separate the sources of CD error in an immersion cluster, in order to correct for them. It has already been reported that the CD error contributors can be attributed to two primary lithographic parameters: effective dose and focus. In this paper, we demonstrate a method to extract effective dose and focus, based on diffraction based optical metrology (scatterometry). A physical model is used to describe the CD variations of a target with controlled focus and dose offsets. This calibrated model enables the extraction of effective dose and focus fingerprints across wafer and across scanner exposure field. We will show how to optimize the target design and the process conditions, in order to achieve an accurate and precise de-convolution over a larger range of focus and dose than the expected variation of the cluster. This technique is implemented on an ASML XT:1900Gi scanner interfaced with a Sokudo RF^3S track. The systematic focus and dose fingerprints obtained by this de-convolution technique enable identification of the specific contributions of the track, scanner and reticle. Finally, specific corrections are applied to compensate for these systematic CD variations and a significant improvement in CD uniformity is demonstrated.

Numerous metrology tools, techniques and methods are used by the industry to setup and qualify exposure tools for production. Traditionally, different metrology techniques and tools have been used to setup dose, focus and overlay optimally and they do so independently. The methods used can be cumbersome, have the potential to interfere with each other and some even require an unacceptable amount of costly exposure tool time for data acquisition. In this work, we present a method that uses an advanced angle-resolved scatterometry metrology tool that has the capability to measure both CD and overlay. By using a technique to de-convolve dose and focus based on the profile measurement of a well characterized process monitor target, we show that the dose and focus signature of a high NA 193nm immersion scanner can be effectively measured and corrected. A similar approach was also taken to address overlay errors using the diffraction based overlay capability of our metrology tool. We demonstrate the advantage of having a single metrology tool solution, which enables us to reduce dose, focus and overlay signatures to a minimum.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD corrections using Dose Mapper^TM. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose Mapper^TM dose recipe created before the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper.

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVision^TM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

For many critical lithography applications the main contributor to wafer intra-field CD variation is the reticle CD variation. Current practice is that the input data needed to correct the effect of the reticle on the wafer CD is gathered using wafer exposures and SEM or scatterometry analysis. This approach consumes valuable scanner time and adds wafer costs. In this work we evaluate the potential for Intra-Field CD non-uniformity (CDU) correction based on aerial image reticle measurements for a complex 2D structure, including peripheral structures. The application selected is a 45nm rotated brick wall structure (active area DRAM). A total of 10 line / space structures (both horizontal and vertical) through pitch represent the periphery. Mask qualification has been performed using the newly developed Zeiss WLCD32 metrology tool, which measures wafer level CD on masks using aerial imaging technology. Excellent correlation is shown between intra-field wafer data and WLCD32 data. Furthermore, a comparison is made between the correction potential of ASML DoseMapper recipes based on wafer data and on WLCD32 mask data, indicating that the potential CDU improvement via both approaches is similar. Exposures with the resulting dose recipes have been used to confirm this predicted correction potential in a realistic setting.

As well as measuring CD, monitoring pattern profile is becoming important for semiconductor metrology. Illuminating the wafer and detecting the reflective light, reflective light intensity in the Fourier space includes the information of CD and pattern profile variation by form birefringence effect. CD change and profile variation could be detected separately for the actual wafer. Mathematical simulation is presented the background of our unique approach. The detail results of CD and pattern profile monitor is shown in this paper.

This work describes the implementation and performance of AGILE focus corrections for advanced photo lithography in volume production as well as advanced development in IBM's 300mm facility. In particular, a logic hierarchy that manages the air gage sub-system corrections to optimize tool productivity while sampling with sufficient frequency to ensure focus accuracy for stable production processes is described. The information reviewed includes: General AGILE implementation approaches; Sample focus correction contours for critical 45nm, 32nm, and 22nm applications; An outline of the IBM Advanced Process Control (APC) logic and system(s) that manage the focus correction sets; Long term, historical focus correction data for stable 45nm processes as well as development stage 32nm processes; Practical issues encountered and possible enhancements to the methodology.

Rapid, inline inspection of wafers and reticles for minimum pitch defects is expected to be a significant technical challenge at the 11nm node. With the possible future adoption of EUV lithography, increasingly exotic materials and complex device architectures, projecting end user requirements is a difficult feat 4 to 5 years out. The present work progresses through projections of these requirements and surveys the various options available to the industry, supported by microscopy simulations. The main conclusion is that the industry needs to support pathfinding projects to develop super-resolution techniques, wavelength scaling and highly multiplexed, high defect contrast ebeam inspection.

As technology node of memory devices is approaching around 30nm, the process window is becoming much narrower and production yield is getting more sensitive to tiny defects which used to be not, if ever, so critical. So it would be very hard to expect the same production yield as now in near future. It is possible to classify wafer defects into systematic and random defects. Systematic defects can be also divided into design related and process related defects. Narrow process window, generally, is thought to be the source of these systematic defects and we have to extend process window with Design for Manufacturing (DFM) and control process variation with Advanced Process Control (APC) to ensure the production yield. The sensitivity of random defects, however, has something to do with the smaller design rule itself. For example, the narrower spaces between lines are subject to bridge defects and the smaller lines, to pinch defects. Die to data base (DB) Design Based Metrology (DBM) has mainly been in use for detecting systematic defects and feedback to DFM and APC so far. We are trying to extend the application of DBM to random defects control. The conventional defect inspection systems are reaching its highest limit due to the low signal to noise ratio for extremely small feature sizes of below 40nm. It is found that Die to DB metrology tool is capable of detecting small but critical defects with reliability.

New techniques recently developed at the National Institute of Standards and Technology using bright-field optical tools are applied to signal-based defect analysis of features with dimensions well below the measurement wavelength. A key to this approach is engineering the illumination as a function of angle and analysis of the entire scattered field. In this paper we demonstrate advantages using this approach for die-to-die defect detection metrology. This methodology, scatterfield optical microscopy (SOM), is evaluated for defect inspection of several defect types defined by Sematech on the Defect Metrology Advisory Group (DMAG) intentional defect array (IDA) wafers. We also report the systematic evaluation of defect sensitivity as a function of illumination wavelength. Theoretical simulations are reported that were carried out using a fully three-dimensional finite difference time domain (FDTD) electromagnetic simulation package. Comprehensive modeling was completed investigating angle-resolved illumination to enhance the detection of several defect types from the IDA wafer designs. The defect types covered a variety of defects from the IDA designs. The simulations evaluate the SOM technique on defect sizes ranging from those currently measurable to those the industry considers difficult to measure. The simulations evaluated both the 65 nm IDA metal-1 M1 trench and the polysilicon stack and more recent 13 nm linewidth logic cells.

Considerable effort is directed towards the development of next-generation lithography processes, addressing the need for transistor densification to meet Moore's Law. The aggressive design rule shrinkage requires very tight process windows and induces various types of pattern failure with lithography process variations. Since the lithography process is critical in the wafer fabrication process, the requirements for high sensitivity defect detection in the lithography process becomes tighter as design rules shrink. Analysis of the root cause of the defects and of their interaction with various light sources and optics systems configurations for wafer inspection is essential for understanding the detection limits and requirements from advanced inspection systems targeting future lithography inspection applications. In this work, we present an analysis of wafer defects light scattering and detection for a variety of 3xnm design rule resist structures with various polarizations and optics configurations, at the visible, at UV and at DUV wavelengths. The analysis indicates on the defect scattering and inspection performance trends for a variety of resist structures and defect types, and shows that control of the polarization of the optical inspection system is critical for enhanced scattering and detection sensitivity. The analysis is performed also for the 2xnm and 1xnm design rules showing the advantages of polarized DUV illumination over unpolarized and visible illumination.

In this study, a 3x-nm after development inspection (ADI) wafer with focus exposure matrix (FEM) was inspected with both an advanced optical system and an advanced electron beam inspection (EBI) system, and the inspection results were carefully examined. We found that EBI can capture much more defects than optical system and it also can provide more information about within reticle shot defect distribution. It has high capture rate of certain critical defects that are insensitive to optical system, such as nano-bridges. We also studied the critical dimension (CD) variations caused by the optical inspection and EBI.

A case study of drastic photolithography defectivity reduction on i-line and Deep-UV (DUV) tools is presented. We show how this result is linked with reduction of Airborne Molecular Contamination (AMC) in clean room by combined installation of novel type of filters on tracks and on the recirculation air treatment. The root cause was identified to be the presence of acetic acid in clean room created by a reaction with the filters (mounted on track tools to exclude ammonia contamination of the process) and the photo solvent itself (here mainly 1-methoxy-2-propanol acetate: PGMEA). Crucial for the project success was the use of a real time monitoring tool to detect the sources of Volatile Organic Compounds (VOC). Finally, a model of chemical reaction of satellite defects creation is discussed based on a Time of Flight Static SIMS (TOF SSIMS) analysis together with new AMC specification for acetic acid for the photolithography area.

We established guidelines for accurately analyzing line-edge and line-width roughness (LER and LWR) basing on the recent discrete power-spectral-density (PSD) method. Extraction of correlation length ζ requires a plateau of PSD in a small-wave-number region. This requirement is met by letting a ratio of inspection length L to ζ be larger than 4π. Analysis errors caused by scanning-electron-microscope image noise are determined by ratios of measurement interval Δy to ζ and of noise-induced variance var(φ) to LWR variance var(w). The ratios need to be at most 20/35 and 1, respectively. var(φ) is reduced by averaging image pixels perpendicularly to lines. This averaging does not smooth LWR, unlike parallel averaging. Statistical noise, i.e. jaggy of PSDs, is another noise source that is caused by a finiteness of the number NFT of Fourier transforms averaged to obtain PSDs. The jaggy level decreases with NFT and with a decrease in Δy. Under the above Δy, NFT should preferably be 50 or larger. The total variance of this study was larger than the sum of var(w) and var(φ). The additional roughness results from a long-range correlation that exceeds the limit of this study. It will be analyzed in our forthcoming report.

LER and LWR have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research done on sources of gate leakage, we found leakage current (Ioff) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures , and dimensions vary significantly. In this paper we present metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). We will show how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout , but surprisingly, not dependent on proximity effects.

Line edge roughness (LER) is an increasingly important issue as lithography scales down. Currently LER is usually measured using scanning electron microscopy (SEM) tools; however, using optical techniques to measure LER may have potential benefit due to less resist damage and higher throughput. In this paper, we explore the detection and potential measurement of LER using dark field spectroscopic reflectometry. We provide a proof of feasibility by showing LER spectra collected on several different applications, which behave consistently with scattering from small particles (Rayleigh) and decrease sharply with wavelength. Additionally, the dependence of the spectra on film thickness bears resemblance to thin film measurements. Finally, we also provide preliminary simulation results showing similar spectral characteristics to the measured spectra.

In this work, for the purpose of contact-hole process control, new metrics for contact-hole edge roughness (CER) are being proposed. The metrics are correlated to lithographic process variation which result in increased electric fields; a primary driver of time-dependent dielectric breakdown (TDDB). Electric field strength at the tip of spoke-shaped CER has been simulated; and new hole-feature metrics have been introduced. An algorithm for defining critical features like spoke angle, spoke length, etc has been defined. In addition, a method for identifying at-risk holes has been demonstrated. The number of spike holes can determine slight defocus conditions that are not detected though the conventional CER metrics. The newly proposed metrics can identify contact holes with a propensity for increased electric field concentration and are expected to improve contact-hole reliability in the sub-40-nm contact-hole process.

Methods of extracting information regarding critical dimensions (CD) in scanning electron microscopes (SEM) are currently based on image brightness. This brings significant uncertainty of the measured results because image brightness has a complex relation to the size and shape of feature, its material, geometry of the pattern as well as SEM setup. A model based extraction of CDs out of SEM images has been developed. The analysis is based on an understanding of physical principles involved in the formation of the SEM signal. Some parameters, such as beam voltage and materials, should be known to the operator as the input data along with the SEM image. The output results of the myCD software are contours of lines, linewidth at the top, bottom, and in the middle of the line, line edge roughnessess at each edge, line width roughness, and wall angles at each edge. In addition, averaged values over all lines present in the image are also displayed. The model based analysis of SEM images may considerably improve accuracy of CD measurements in SEM.

In contour metrology the CD-SEM (critical dimension scanning electron microscope) assigns a continuous boundary to extended features in an image. The boundary is typically assigned as a simple function of the signal intensity, for example by a brightness threshold or gradient. However, the neighborhood of different points along the feature boundary may vary considerably. Some parts of the boundary may have close neighboring features while others are relatively isolated. Neighboring features can obstruct the escape of secondary electrons. Varying proximity of neighbors therefore represents an influence on detected intensity. An intensity difference caused by a neighborhood difference can be incorrectly interpreted as a contour shift, for example when the contour passes from an isolated neighborhood to a dense one. The magnitude of this offset variation is estimated using images produced by JMONSEL, a Monte Carlo simulator of SEM secondary electron imaging, from simple model test patterns with varying neighborhoods. Similar structures were subsequently measured by both SEM and atomic force microscopy (AFM). Apparent shifts (i.e., errors) on the order of 0.5 nm to 1.0 nm for each edge were observed in both modeled and measured SEM images as compared to AFM when edge positions were assigned by using a fixed image brightness contour. Assignment of edges by brightness relative to the local background and local maximum brightness resulted in measurements that were less sensitive to neighborhood differences.

The aggressive design rules of deep sub-micron technology using Cu metal over Wplugs, makes process monitoring and characterization a real challenge. Lack of metal coverage above contact may cause yield degradation due to un-predicted contact resistance. Due to proximity effects and Optical-Proximity-Correction (OPC) restrictions, different layout configuration of metal-over-contact may results in different contact coverage by the metal. From metrology point-of-view, the ability to control process latitude of two constituent layers in the semiconductor process is critical. The basic way to develop and control Metal over Contact process with a CD-SEM is to measure the contact plugs through the metal trenches. This approach proposes a significant metrological challenge. There is no edge topography, only material contrast, and only part of the Contact can be seen. Hence, innovative algorithms and image processing techniques are required to accurately measure the metal-over-contact area coverage. In this paper, we demonstrate a reliable characterization and monitoring method. A dedicated test chip was designed for this purpose, having ~650 of different layout configurations and dimensions, in one nanometer variation. The methodology flow consists of using systematic Edge-Contour-Extraction (ECE). The physical parameters extracted from the ECE measurements analysis are used for several purposes: (i) identification of design-rule verification, (ii) contact resistance calculation based on the metal-over-contact coverage area, (iii) reliable feedback for OPC correction efficiency.

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, challenging mask defect dispositioning more than ever. To address these challenges in mask inspection and defect dispositioning, new mask inspection technologies have been developed that not only provide high resolution masks imaged at the same wavelength as the scanner, but that also provide aerial images by using both: software simulation and hardware emulation. The original mask patterns stored by the optics of mask inspection systems can be recovered using a patented algorithm based on the Level Set Method. More accurate lithography simulation models can be used to further evaluate defects on simulated resist patterns using the recovered mask pattern in high resolution and aerial mode. An automated defect classification based on lithography significance and local CD changes is also developed to disposition tens of thousands of potential defects in minutes, so that inspection throughput is not impacted.

Workhorse metrology such as CD-SEM is used during process development, process control, and optical proximity correction model generation and verification. Such metrology needs to be calibrated to handle various types of profiles encountered during IC fabrication. Reference metrology is used for calibration of workhorse metrology. There is an astounding need for sub-half and sub-quarter nanometer measurement uncertainty in the near future technology nodes as envisaged in the International Technology Roadmap for Semiconductors. In this regime of desired measurement uncertainty all metrology techniques are deemed limited and hybrid metrology appears promising to offer a solution. Hybrid metrology is the use of multiple metrology techniques, each with particular strength, to reduce the overall measurement uncertainty. CD-AFM makes use of a flared probe in order to scan the sidewalls and bottom of the pattern on a wafer to provide 3D profile and CD measurements at desired location on the profile. As the CD shrinks with technology nodes especially the space, the size of the AFM probe also needs to shrink while maintaining the flared geometry specifications. Unfortunately the fabrication of such probes is a challenge and new techniques are required to extend reference metrology to the smallest space and hole of interest. This paper proposes a reference system combining CD-AFM and patterning simulation model. This hybrid metrology system enables CD metrology in a space not measurable directly by conventional CD-AFM probe. The key idea is to use the successfully measured profile and CD information from the CD-AFM to calibrate or train the patterning simulation optical and resist model. Ability of this model to predict profile and CD measurement is verified on a physically measured dataset including cross sections and additional CD-AFM measurements. It is hypothesized that this model will be able to predict profile and CD measurements in otherwise immeasurable geometries. Being based on optics and materials fundamentals, this approach is presumed to be more accurate compared to mere extrapolation approach in use today. We report on the measurement uncertainty improvement with this approach. Situations with highest prediction confidence involve CD-AFM scanning resulting in partial information. For example, using carbon nanotube probes or CDP where there is little flaring of the tip, the CD-AFM cannot detect significant undercutting of the structure. Achieving agreement with the calibrated patterning model for measurement metrics such as height, top and middle CD permits the prediction of the bottom CD to be used as an authentic reference measurement.

The scatterometry or OCD (Optical CD) metrology technique has in recent years moved from being a general purpose CD metrology technique to one that addresses the metrology needs of process monitoring and control, where its strengths can be fully utilized. With the significant advancements that have been made in both hardware and software design, the setup time required to build complex models and solutions has been significantly reduced. Whilst the application of scatterometry to process control has clearly shown its merits, the question still arises as to how accurately the process corrections to feed forward or feedback for process control can be extracted? In this work we critically examine the accuracy of scatterometry with respect to process control by comparing three hardware platforms, on a simple litho stack. The impact of hardware design is discussed as well as the 'setup' of the modeled parameters on the final measurement result. It will be shown that informations extracted based on scatterometry measurements must be true to process variation and independent of the hardware design. Our results will show that the ability to use scatterometry effectively for process control ultimately lies in the ability to accurately determine the changes that have occurred in the process and to be able to extract appropriate process corrections for feedback or feed forward control; allowing these changes to be accurately corrected. To do this the metrology validation extends beyond the typical metrology metrics such as precision and TMU; metrology validation with respect to process control must encompass accurate determination of process corrections to ensure a process tool and/or process stays at the set point.

With the introduction of double patterning, overlay capability below 5nm is required for optical lithography density scaling to the 22nm node and beyond. Commensurate overlay metrology must enable dense sampling of all patterned area to control single-nanometer systematic sources of error among an increasing number of device layers. This translates to the need for sub-second measurement of microscopic targets representing multiple layers within a metrology tool field of view, all while improving accuracy. Blossom (BLO) is the overlay metrology of record for the IBM 32nm technology. As we will describe here, the densely packed array of layers represented in a single BLO target has enabled us to conduct within-field in-line sampling on our most critical layers. We will also report the significant improvements to metrology performance that have resulted from our migration of BLO technology to a new measurement platform. In addition, as 22nm development proceeds, we are shrinking our overlay targets further. A target suitable for within-chip insertion, a 10μm square micro-Blossom (μBLO) target, can accommodate up to 8 layers. Correlation of μBLO to BLO measurements on a layer pair shows excellent agreement, and despite an approximately 10X area shrink relative to BLO, the μBLO measurement uncertainty remains comfortably below 0.5nm. Our paper presents details of our target layout, measurement, and analysis approach. In addition, we detail data representative of overlay variation in state-of-the-art lithographic processes, along with our outlook for overlay metrology implementation for future technologies.

We have developed high-resolution grazing incidence x-ray diffraction (HRGIXD) pitch calibration system with wavelength of 0.1540593 nm (Cu K α₁ line). In order to ensure accuracy of this calibration system, we measured average pitch of a 100-nm pitch grating reference, which is being used for magnification calibration of a current critical-dimension scanning electron microscope (CD-SEM), and compared with the results of deep ultra violet (DUV) laser diffraction pitch calibration system with wavelength of 193 nm. The average pitch determined by the HRGIXD system agrees with that determined by the DUV laser diffraction system within the range of uncertainty. We measured average pitch of a fine 25-nm pitch grating, which will be used for magnification reference. In the DUV laser diffraction, wavelength of 193 nm no longer satisfies diffraction condition for the 25-nm pitch grating, because wavelength must be shorter than twice of the pitch size. On the other hand, wavelength of x-ray is much shorter than the pitch size. We have successfully detected more than ten sharp diffraction peaks corresponding to the 25-nm period. The average pitch of the grating is measured in very high-accuracy with standard uncertainty of less than 10 pm.

We have developed a new x-ray metrology for measuring surface periodic grating of semiconductor device pattern. X-rays irradiate surface of the device area with a shallow glancing angle, which is close to the critical angle of total external reflection of the surface material. The measured x-ray diffraction pattern is reflected to the average cross-sectional profile of the grating. The pattern made from SiO₂ on Si with100 nm-pitch is analyzed by the present x-ray metrology. The obtained profile, for example, line width, height of the grating and so on are well agreed with that observed by cross-sectional transmission electron microscopy. The wavelength of x-ray that we use is 0.154093 nm and it is enough shorter than the critical length of the grating structure, even when the line width becomes 10 nm or less. Therefore, the resolution of the x-ray metrology will be maintained good enough for the analysis that will be required in the future. In addition, x-ray metrology can be measure the cross-sectional profile with nondestructively due to hightransmissivity of x-rays for the materials. Furthermore, the optical parameter of the materials for x-ray is well established, therefore, x-ray metrology is applicable for any materials of device patterns without uncertain empirical parameters.

Grazing incidence small-angle x-ray scattering (GISAXS) is proposed as one of the candidates for characterizing cross section of nanostructure line grating pattern. GISAXS is expected as useful nondestructive tool for characterizing cross section. We developed GISAXS and evaluated the capability using the 4X nm resist line patterns and the 3X nm silicon gate line patterns. The GISAXS results are compared with TEM images to evaluate the reconstruction ability in cross section contour profile. The correlation is investigated between GISAXS and the reference tools such as CD-SEM and TEM in the values of CD, height and bottom corner radius. The static repeatability is also evaluated by performing measurement ten times. We report the results of GISAXS capability as cross sectional metrology tool in actual device of 4X and 3X generation.

The recently introduced helium ion microscope (HIM) is capable of imaging and fabrication of nanostructures thanks to its sub-nanometer sized ion probe. The unique interaction of the helium ions with the sample material provides very localized secondary electron emission, thus providing a valuable signal for high-resolution imaging as well as a mechanism for very precise nanofabrication. The low proximity effects, due to the low yield of backscattered ions and the confinement of the forward scattered ions into a narrow cone, enable patterning of ultra-dense sub-10 nm structures. This paper presents various nanofabrication results obtained with direct-write, with scanning helium ion beam lithography, and with helium ion beam induced deposition.

Microscopy of 3D interconnect structures is challenged by the opaque nature of silicon. Infrared (IR) microscopy provides a way of "looking" through silicon where microscopes based on visible wavelengths fail. Perhaps the most prevalent application of IR microscopes in 3D manufacturing is imaging sub-surface features at the interface of a bonded wafer pair. The ability to see through silicon using IR microscopes enables a variety of metrology techniques, including the overlay of circuit layers (e.g., metal 2 to via). IR microscopy is a non-destructive technique and, as such, it is an ideal candidate for in-line metrology for the bonded wafer pairs required for 3D interconnects. This paper reviews overlay metrology capability for an IR microscope. The ability to measure the overlay of bonded wafer pairs according to the 2009 International Technology Roadmap for Semiconductors (ITRS) is demonstrated. Overlay tolerances for a variety of copper interconnect test structures is predicted based on electrical designs, and overlay results are compared to electrical test results. The use of IR microscopy as an early indicator of electrical yield is clearly demonstrated.

Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure involved scanning with three different recipe types: Standard Inspection: Nominal recipe with a low false alarm rate was used to scan the wafer and repeaters were extracted from the final defect map. Haze Monitoring Application: Recipe sensitivity was enhanced and run on a single field column from which on repeating defects were extracted. Enhanced Repeater Extractor: Defect processing included the two parallel routes: a nominal recipe for the random defects and the new high sensitive repeater extractor algorithm. The results showed that the new application (recipe #3) had the highest capture rate on haze defects and detected new repeater defects not found in the first two recipes. In addition, the recipe was much simpler to setup since repeaters are filtered separately from random defects. We expect that in the future, with the advent of mask-less lithography and EUV lithography, the monitoring of field and die repeating defects on the wafer will become a necessity for process control in the semiconductor fab.

A persistent industry problem impacting photomask yield and costs has been haze formation. The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Thus some capability will always be needed to remove haze on photomasks with their final pellicles mounted both at the manufacture and long term maintenance stages of a mask's lifetime. A novel technology is reviewed here which uses a dry (no chemical effluents) removal system to sweep the entire printable region of a pelliclized photomask to eliminate all removable haze regardless of the mask substrate materials or the presence of critical patterns. An operational process technique for this system and performance in removal is shown for haze located on the mask pattern surface. Finally, preliminary data from tool acceptance and preliminary use in a production environment will also be reviewed.

Defects on the backside of wafers can be either tool or process induced and can cause lithography-related issues such as focus deviation or chuck contamination. Tool induced scratches, process induced contamination, or residues on the back of wafers often have unique signatures, such as a repeatable scratch caused by wafer handling equipment or a chuck imprint on the backside of a wafer. Certain backside defect signatures such as large scratches or divots can contribute to wafer breakage or reliability issues. Spatial Pattern Recognition (SPR) is a method of comparing defect patterns at the wafer level with known defect signatures stored in a library that is created from process data. These defect signatures can represent systemic issues with process tools, handling equipment, or the process itself. This paper describes a backside inspection method for identifying wafers with both known and new spatial pattern signatures. By reporting the frequency of each signature category, process partitioning can efficiently trace the source of these problems. In addition, new defect signatures can be automatically learned and added to the library. The paper also includes examples of how this method was used to identify backside defect patterns caused by process and tool excursions in a 300mm fabricator.

Three years ago Entegris pioneered a novel method of controlling ammonium sulfate (AS) haze by maintaining 193 nm reticles in a low humidity environment. Since then, this approach has became an industry standard and is widely used in production fabs around the world. Based on analysis of practical applications in HVM fabs, this paper describes a successful approach to reticle haze control, outlines its critical elements and explains its limiting factors. In addition to actual fab data, the paper provides a large body of comparative experimental data on humidity dynamics in different reticle storage schemes and arrangements. With this data, the authors explain why some designs work much better than others and provide practical recommendations for lithography practitioners on haze control equipment selections and reticle management strategy development.

A new multipurpose instrument calibration standard has been released by NIST. This standard was developed to be used primarily for X and Y scale (or magnification) calibrations of scanning electron microscopes from less than 10 times magnification to more than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument field of view (FOV). This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration and testing of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be used for a number of other applications, some of which will be described in this publication.

The 2007 edition of ITRS has introduced a new metric for metrology quality assessment - measurement uncertainty (MU). The new metric has precision as one of many uncertainty components. Additional significant components are tool matching, sampling uncertainty and sample-to-sample bias variation. Sample dependent bias variation and, therefore, MU can be measured accurately only if a reference metrology (RM) is employed. RM is a must for achieving and verifying required today sub-nanometer MU of critical dimension (CD) metrology. To insure long-term performance of in-line metrology and reliable process control a simple but efficient way is suggested - employment of in-line RM system. SI-traceable CD AFM with sub-nanometer MU is a proper RM tool for the task.

We aim to develop and calibrate a set of step height standards to meet the range of steps useful for nanotechnology. Of particular interest to this community is the calibration of atomic force microscopes operating at their highest levels of magnification. In previous work we fabricated and calibrated step height standards consisting of the lattice steps on the (111) surface of single crystal Si and provided a recommended value of 312 pm ± 12 pm. In the current work we report traceable measurements of 1 nm step height specimens fabricated on the (0001) 4H-SiC surface. In this, we are seeking to fill in the range between the newly available 300 pm steps and 8 nm steps, which are the smallest available commercially. The step height measurements were performed using a calibrated atomic force microscope (C-AFM) calibrated with respect to the wavelength of light along all three axes of motion. Analysis of the measurements yields an average step height value of 0.981 nm with a combined standard uncertainty of ± 0.019 nm (k = 1), reasonably consistent with the expected value of 1.00851 nm derived from the parameters of the SiC crystal lattice.

Resist-on-silicon sub-50-nm critical dimension targets have been investigated using a 193 nm angle-resolved scatterfield microscope (ARSM). The illumination path of this microscope allows customization of the conjugate back focal plane (CBFP) while separate collection paths permit both high-magnification and Fourier-plane imaging. Aspects of the calibration of this microscope are presented. Full-field, Fourier-plane images are collected as individual targets are illuminated using a field-of-view smaller than the target size; the range of incident polar angles corresponds to the numerical aperture (NA) of the objective, NA = 0.08 to 0.74. Next, angle-resolved scatterfield high-magnification imaging of these same targets are acquired in a conical mounting configuration by scanning the 12 mm diameter CBFP with a 1 mm diameter aperture. The results of these measurements and the prospects for quantitative, simultaneous measurement of multiple targets are discussed.

We consider the effects of finite spectral bandwidth and numerical aperture in scatterometry measurements and discuss efficient integration methods based upon Gaussian quadrature in one dimension (for spectral bandwidth averaging) and two dimensions inside a circle (for numerical aperture averaging). Provided the wavelength is not near a Wood's anomaly for the grating, we find that the resulting methods converge very quickly to a level suitable for most measurement applications. In the vicinity of a Wood's anomaly, however, the methods provide rather poor behavior. We also describe a method that can be used to extract the effective spectral bandwidth and numerical aperture for a scatterometry tool. We find that accounting for spectral bandwidth and numerical aperture is necessary to obtain satisfactory results in scatterometry.

The ability to extract critical parameters using scatterometry depends on the parameter sensitivity and correlation at different wavelengths. These, in turn, determine the key metrics: accuracy, precision, and tool-to-tool matching. Parameter sensitivity and correlation can vary drastically, depending on whether the oblique incident light beam is parallel (azimuth angle = 90 degrees), perpendicular (azimuth angle = 0 degrees), or at an intermediate angle to the measured structures. In this paper, we explore the use of both variable- and multiple-azimuth (AZ) (or multi-AZ) angle spectroscopic ellipsometry (SE) to optimize the measurement performance for different applications. The first example compares the sensitivity and results using SE at 0 and 90 degree AZ angles for a BEOL post-litho metal trench application. We observe up to a sixfold improvement in key metrics for critical parameters using 90 degree over 0 degree AZ angle spectra. The second example illustrates the benefits of a multiple-AZ angle approach to extract critical parameters for a two-dimensional logic High-K Metal Gate (HKMG) structure. Typically, this approach simultaneously fits two sets of SE spectra collected from the same location on the wafer at different AZ angles with the same physical model. This helps both validate and decorrelate critical parameters, enabling robust measurements. Results show that, for this application, the measurement performance metrics for each critical parameter are improved in almost every case.

Optical properties (n&k) of the material films under measurement are commonly assumed invariant and fixed in scatterometry modeling. This assumption keeps the modeling simple by limiting the number of floating parameters in the model. Such scatterometry measurement has the potential to measure with high precision some of the profile parameters (CD, Sidewall angle). The question is: if the optical properties modeled as "fixed" are actually changing - would this modeling assumption impact the accuracy of reported geometrical parameters? Using the example of a resist profile measurement, we quantify the "bias" effect of un-modeled variation of optical properties on the accuracy of the reported geometry by utilizing a traditional fixed n&k model. With a second model we float an additional optical parameter and lower the bias of the reported values - at the expense of slightly increased "noise" of the measurement (more floating parameters - less precision). Finally, we extend our multi-stack approach (previously introduced as enabler to the product-driven materials characterization methodology) to augment the spectral information and increase both precision and accuracy through the simultaneous modeling of multiple targets

In this work we report the results of the optical characterization of a periodic grating carried out with a probe spot size larger than the sample grating "box". The measured depolarizing Mueller matrices resulting from incoherent superposition of the optical responses of the grating and substrate were filtered by using the eigenvalues decomposition method. The retrieved Mueller matrices of the grating alone were fitted using rigorous coupled-wave method and the standard trapezoidal model with three parameters: the middle line-width (CD), the grating depth and the side-wall angle. The results are shown for all measured azimuthal angles and compared with reference values taken on a similar grating on the same wafer, in the usual conditions (beam spot inside the grating). The observed stability of the parameters very closely coincides with the reference grating except for some azimuthal angles, where the grating contributed only 5% of the signal. The overall dispersion of the parameters is within the few nanometers from the statistical mean value, a performance comparable to that of standard grating characterizations with the probe beam illuminating only the grating.

DPT overlay errors result in CD distortions and CD non-uniformity leads to overlay errors demanding increased critical dimension uniformity (CDU) and improved overlay control. Scatterometry techniques are used to characterize the CD uniformity, focus and dose control. We will present CD distribution (CDU) and profile characterization for spacer double patterning structures by advanced scatterometry methods. Our result will include NISR, and spectroscopic ellipsometry (SE) characterization of CDU sensitivity in spacer double patterning stack. We will further show the results of spacer DP structures by NISR and SE measurements. Metrology comparison at various process steps including litho, etch and spacer and validation of CDU and profile; all benchmarked against traditional CDSEM measurements.

The novel calibration method of sub-nanometer accuracy for the line width measurement using STEM images is proposed to calibrate CD-SEM line width measurements. In accordance with the proposed method, the traceability and reference metrology of line width standards are established using Si lattice structures. First, we define the edge of a line as the end of Si lattice structure as the interface between Si lattice and oxide film. Second, an image magnification and inclination angles are calculated using 2D Fourier analysis of a STEM image. Third, the edge positions of the line are detected after the novel noise reduction method using averaging by Si lattice patterns. Then, the uncertainty of the line width measurement is evaluated with the uncertainty contributors of pixel size, edge detections and repeatability. Using the proposed method, the expanded uncertainty less than 0.5 nm for the line width of 45 nm is established.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require thinner layers of photoresists, such as under 100 nm. In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage behaves differently for different sized features. This work was extended in yet another paper in which we presented a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long as the photoresist was thick enough that the beam could not penetrate the entire layer of resist. In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes. With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage trend.

We present the Monte Carlo simulation program MCSEM, developed at the Physikalisch-Technische Bundesanstalt (PTB), Germany, for the simulation of Scanning Electron Microscopy (SEM) image formation at arbitrary specimen structures (e.g. layout structures of wafers or photomasks). The program simulates the different stages of the SEM image formation process: the probe forming, the probe-sample interaction and the detection process. A modular program structure is used for an easy adaptation of the program to new simulation tasks. Arbitrarily shaped 3D structured specimen models can be applied and different electron probe shapes are modeled. Various physical models for electron scattering in solid state material are included. Secondary electron (SE) detection modeling is based on SE raytracing, detectors for backscattered electrons (BSE) and transmitted electrons (TE) are also available. An electromagnetic field solver is used to simulate charging of the specimen and the transport of the SE within the electromagnetic field. Some examples of simulation results are presented together with comparisons with experimental results.

The extension of optical lithography to 22nm and beyond by Double Patterning Technology is often challenged by CDU and overlay control. With reduced overlay measurement error budgets in the sub-nm range, relying on traditional Total Measurement Uncertainty (TMU) estimates alone is no longer sufficient. In this paper we will report scatterometry overlay measurements data from a set of twelve test wafers, using four different target designs. The TMU of these measurements is under 0.4nm, within the process control requirements for the 22nm node. Comparing the measurement differences between DBO targets (using empirical and model based analysis) and with image-based overlay data indicates the presence of systematic and random measurement errors that exceeds the TMU estimate.

In 32nm/22nm advanced technology node, double patterning lithography is considered for semiconductor manufacturing. It necessitates tightened requirement of overlay measurement, i.e. to measure the position of a pattern with respect to that of a pattern in the underlying layer. The measurement target design plays a fundamental role in overlay precision and accuracy. Typical alignment target, such as bar-in-bar or box-in-box (BIB), has precision, accuracy, and size restrictions. This prompts us to look into better alignment targets. Recently, scatterometry-based metrology and profile model capability have been extended to measure multi-level grating structures. In addition, scatterometry has been shown to be the best choice for integrated metrology to perform wafer-to-wafer control. Therefore, it makes sense to consider using scatterometry for overlay measurement. In this research, the modeling analysis is performed on the spectra taken directly from a real pattern area with grating-ongrating structure. The critical dimension (CD) at the grating on top and the lateral shift between the top and the bottom gratings can be detected simultaneously. The lateral shift between the layers can be verified with the traditional overlay box. Unlike the traditional BIB target that has micrometer CD size, the CD size of the scatterometry overlay (S_OVL) target is much closer to that on the real device. So, it can much better reflect the overlay (OVL) shift on real devices. We also studied the non-model-based S_OVL measurement using a 673-nm semiconductor laser with a 10μm x 20μm target size, wafer-to-wafer control of CD and lateral shifts on some critical layers with grating-on-grating structure, as well as the CD and OVL variations within layer and from layer to layer for double patterning.

A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved algorithms for this automation; both of which are described here.

Current image based overlay metrology accuracy will not be suitable for the critical layers of near future memory production. At current nodes, measurement reproducibility of 0.6nm or better is required. The number of sampling points is also expected to increase due to the need for higher order process corrections on the exposure tool. To maintain or improve total measurement cost, these requirements should be met without negatively impacting throughput. In this paper we will study a novel, diffraction-based system especially designed to meet these challenging requirements for next generation memory devices. In addition to overlay metrology, the system is capable of measuring CD and side wall angle (SWA) within the same measurement cycle. The system can also be used to monitor exposure tool overlay and focus stability. In this paper we intend to examine the metrics used to evaluate the overlay metrology performance critical for a DRAM production environment. We also intend to spend much of the paper taking a deeper look at how we can combine the overlay and CD metrology functionalities to examine the asymmetric profile of target gratings. One of the critical applications for diffraction based overlay metrology is in understanding the asymmetric properties of target gratings across a wafer. Reconstructing asymmetric profiles quickly, effectively and with a suitable degree of sensitivity, will allow measurement accuracy to be further enhanced and will open the door to numerous applications within the memory fab environment including process monitoring and improvement. In this paper, we intend to investigate techniques for detecting asymmetric structures and also for the more complex issue of reconstructing the shape of these structures.

We have developed a new local overlay measurement technique on actual device patterns using critical dimension scanning electron microscope (CD-SEM), which can be applied to 2D device structures such as an SRAM contact hole array or more complex shapes. CD-SEM overlay measurement can provide additional local overlay information at the site of device patterns, complementary to the conventional optical overlay data. The methodology includes the use of symmetrically arranged patterns to cancel out many process effects and reduce measurement uncertainty. The developed methodology was applied to local overlay measurement of double patterning contact hole layers of leading edge devices. Local overlay distribution was successfully captured on device structures on different length scale, and the result shows the possibility of assessing process induced shift on device structures and collecting denser sampling for better intra-chip overlay control. The measurement uncertainty of CD-SEM overlay metrology was assessed by comparing with conventional optical overlay metrology for 1D and 2D structures. Very good correlation was confirmed between SEM and optical overlay metrology with net residual error of ~1.1nm. Measurement variation associated with pattern roughness was analyzed for 1D structure, and identified as one of major variation sources for CD-SEM overlay metrology.

Metrology is often used in designing and controlling manufacturing processes. A product sample is processed, some relevant property is measured, and the process adjusted to bring the next processed sample closer to its specification. This feedback loop can be remarkably effective for the complex processes used in semiconductor manufacturing, but there is some risk involved because measurements have uncertainty and product specifications have tolerances. There is finite risk that good product will fail testing or that faulty product will pass. Standard methods for quantifying measurement uncertainty have been presented, but the question arises: how much measurement uncertainty is tolerable in a specific case? Or, How does measurement uncertainty relate to manufacturing risk? This paper looks at some of the components inside this process control feedback loop and describes methods to answer these questions.

This work explores the applications of CD-SEM overlay metrology for double patterned one-dimensional (1D) pitch split features as well as double patterned ensembles of two-dimensional (2D) complex shapes. Overlay model analysis of both optical overlay and CD-SEM is compared and found to give nearly equivalent results. Spatial correlation of the overlay vectors is examined over a large range of spatial distances. The smallest spatial distances are shown to have the highest degree of correlation. Correlation studies of local overlay in a globally uniform environment, suggest that the smallest sampling of overlay vectors need to be ~10-15μm, within the spatial sampling of this experiment. The smallest spatial distances are also found to have to tightest mean distributions. The distribution width of the CD-SEM overlay is found to scale linearly with log of the spatial distances over 4-5 orders of magnitude of spatial length. Methodologies are introduced to examine both the overlay of double pattern contacts at the edge of an array and lithographic process-induced overlay shift of contacts. Finally, a hybrid optical- CD-SEM overlay metrology is introduced in order to capture a high order, device weighted overlay response.

Modern OPC modeling relies on substantial volumes of metrology data to meet pattern coverage and precision requirements. This data must be reviewed and cleaned prior to model calibration to prevent bad data from adversely affecting calibration. We propose implementing specific tools in the metrology flow to improve metrology engineering efficiency and resulting data quality. The metrology flow with and without these tools will be discussed, and the inherent tradeoffs will be identified. To demonstrate the benefit of the proposed flow, engineering efficiency and the impact of better data on model calibration will be quantified.

OPC-modeling is traditionally based on CD-measurements. As design rules shrink, and process window become smaller, there is an unavoidable increase in the complexity of OPC/RET schemes required to enable design printability. The number of measurement points for OPC-modeling has increased to several hundred points per layer, and metrology requirements are no longer limited to simple one-dimensional measurements. Contour-based OPC-modeling has recently arisen as an alternative to the conventional CD-based method. In this paper, the technology of contour alignment and averaging was extended to arbitrary 2D structures. Furthermore the quality of SEM-contours was significantly improved in cases where the image has both horizontal and vertical edges (as is the case for most 2D structures), by a new SEM image method, which we call 'Fine SEM Edge'. OPC model calibration was done using SEM-contours from 2D structures. Then, the effectiveness of Contour-based calibration was examined by doing OPC model verification. The experimental results of the model quality with innovative SEM-contours with Fine SEM Edge (FSE) and Advanced alignment and averaging that was developed by Hitachi High-Technologies are reported. This combination of advanced alignment and averaging and FSE technologies makes the best use of the advantage of the contour-based OPC-modeling, and should be of use for the next generation lithography.

Mask and metrology errors such as SEM (Scanning Electron Microscopy) measurement errors are currently not accounted for when calibrating OPC models. Nevertheless, they can lead to erroneous model parameters therefore causing inaccuracies in the model prediction if these errors are of the same order of magnitude than targeted modeling accuracy. In this study, we used a dedicated design of hundres of features exposed through a Focus Exposure Matrix for the metrology error, we compared the SEM measurements to AFM measurements for as much as 105 features exposed in various process conditions of does and defocus. These data have then been used in a OPC model calibration procedure. We show that the impact of the metrology error is not negligible and demonstrate the importance of taking into account these errors in order to improve the reliability of the OPC models.

The CD metrology requirements for advanced node developments and process control are becoming more and more restrictive with shrinkage of dimensions. Currently in R&D, and more particularly in the process development in lithography or etching step, we have to cope with sub-40nm trenches CD measurements for sub-28nm nodes development. For such requirements, we are using the 3D-AFM technology as a complementary technique to CD-SEM. Indeed, as CD-SEM is limited in giving accurate information about profiles, the 3D-AFM technology must be considered. To succeed in measuring on a repeatable way and accurately sub-40nm trenches and contact holes, the 3D-AFM tips diameter has to be manufactured within tight specifications and the relative accuracy tip to tip must remains constant and reliable. In this paper, we will present a large set of data related to the use of various 3D-AFM tip models (diameter, tip edge, tip material, stiffness...) from large model to tiny model with typical tip diameter of 28nm. We compare the performances of each model in term of accuracy and repeatability, and extrapolate the industrial requirements that are necessary for tip manufacturing in order to be compatible with advanced roadmap requirements. Finally, we will present as function of tip model the relative accuracy of CD measurements.

Defect review of advanced lithography processes is becoming more and more challenging as feature sizes decrease. Previous studies using a defect review SEM on immersion lithography generated wafers have resulted in a defect classification scheme which, among others, includes a category for micro-bridges. Micro-bridges are small connections between two adjacent lines in photo-resist and are considered device killing defects. Micro-bridge rates also tend to increase as feature sizes decrease, making them even more important for the next technology nodes. Especially because micro-bridge defects can originate from different root causes, the need to further refine and split up the classification of this type of defect into sub groups may become a necessity. This paper focuses on finding the correlation of the different types of micro-bridge defects to a particular root cause based on a full characterization and root cause analysis of this class of defects, by using advanced SEM review capabilities like high quality imaging in very low FOV, Multi Perspective SEM Imaging (MPSI), tilted column and rotated stage (Tilt&Rotation) imaging and Focused Ion Beam (FIB) cross sectioning. Immersion lithography material has been mainly used to generate the set of data presented in this work even though, in the last part of the results, some EUV lithography data will be presented as part of the continuing effort to extend the micro-bridge defect characterization to the EUV technology on 40 nm technology node and beyond.

Defectivity control continues to challenge advanced semiconductor manufacturing, especially immersion lithography processes. Immersion exposure tools are sensitive to incoming wafer defects, including top coat voids, surface defects, and other random or systematic anomalies. A single defective wafer could contaminate the exposure tool's immersion hood resulting in lengthy and costly repairs. To mitigate this problem, TEL developed an integrated and real-time macro inspection solution to identify defective wafers which could potentially damage immersion exposure tools. The Wafer Intelligent Scanner (WIS) module integrates within the CLEAN TRACK^TM LITHIUS Pro^TM platform without impacting footprint or throughput. By utilizing user defined inspection criteria, wafers can be inspected prior to and after exposure for macro defects. Wafers failing to meet inspection criteria prior to exposure are automatically re-routed to bypass the exposure tool and subsequent process modules.

Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification (ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and consistency in the classification data and eliminates variance induced by the manufacturing staff. This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing environment as a key driver in the reduction of defect limited yields.

Maintaining low-defect spin-applied films is paramount to the success of semiconductor manufacturing. While some spin-on films have a low number of defects as coated, defect levels can rise with the number of wafers processed. Thin organic films may outgas or sublime during the post-coat baking process, or even during subsequent exposures to deep or extreme ultraviolet radiation. If these outgassing components collect on the lid of the hot plate chamber, there is an increased risk of "fall-on" defects on subsequently processed wafers. To increase throughput, preventive maintenance and cleaning schedules are pushed to the limit to provide maximum output from the track. New materials must be designed to produce minimal outgassing to ensure maximum throughput without defects. Early tests for measuring outgassing provided qualitative results gained from collecting the condensed outgassing components on a quartz wafer and measuring the absorbance of the resulting film. A more advanced technique involves the use of a newly designed quartz crystal microbalance (QCM) to more carefully quantify the amount of outgassing.[1] As the industry continues to mature, more sensitive measurements are required to design new materials with even lower outgassing from sublimation. The inverted wafer test and the QCM techniques provide complementary information about outgassing and together provide a better overall prediction of the defectforming potential than either technique alone.

Measuring coating defects on two or more blanket film layers is difficult and can be misleading due to reflectivity changes from the bottom layer, and surface roughness not present when the substrate is only polished silicon. To improve signal-to-noise ratio and establish a lower limit for particle size detection, polystyrene latex (PSL) spheres are deposited on the film stack. Particles as small as 54 nm were detectable on a stack 330-nm thick using a Hitachi LS Series Surface Scanning Inspection System (SSIS) and RS5500 Defect Review Scanning Electron Microscope (DRSEM). These systems have advanced capabilities enabling automated detection, classification, and characterization of defects down to 30 nm or smaller on some substrates and films. Haze wafer maps are related to surface roughness and reflectivity and show unusual asymmetries possibly caused by dispense problems or exhaust flow patterns during baking. These maps can be helpful to find problems in the coating system, even if film thickness is on target. Preliminary testing results are presented for a typical trilayer pattern stack for high-resolution 193-nm patterning consisting of a silicon spinon hardmask (HM) layer on top of a spin-on carbon (SOC) layer. The majority of the defects were caused by bubble formation within the HM that was modulated by process conditions used for these tests. A higher spin speed for the HM coating produced lower defects, most likely due to a thinner film with less trapped solvent during baking, but this effect will require more study, as it could also be due to a faster evaporation rate caused by higher airflow. Pre-wet, spin time, and bake temperature did not produce significant effects within these tests, but showed trends requiring further study. These advanced spin-on HM materials can be applied as thin as 15 to 20 nm due to their high etch selectivity. With the use of such high-resolution defect metrology, very subtle chemical interactions and process effects can be examined to find the ideal process conditions for both the SOC and HM layers.

Assessing molecular contamination (MC) at part-per-billion (ppbV) or part-per-trillion volume (pptV) levels in cleanroom air and purge gas lines is essential to protect lithography and metrology tools optics and components. Current lithography and metrology tool manufacturer's specifications require testing of some contaminants down to single digit pptV levels. Ideally this analysis would be performed with an on-line analyzer (capable of providing almost instant results): the best analyzers currently available are only capable of providing 100 pptV detection. Liquid impinger sampling has been the dominant sample collection method for sub ppbV acidic and basic MC analysis. Impinger sampling suffers from some inherent problems that can dramatically reduce the collection efficiency such as analyte solubility and evaporative losses. An innovative solid-state trapping technology has been recently developed by SAES Pure Gas along with the CollectTorr sampling system. NIST traceable gas phase standards have been used to compare the collection efficiency of the traditional impinger technology to that of the solid state trapping method. Results varied greatly for the different acid gases with sulfur dioxide showing comparable collection efficiencies while hydrofluoric acid and hydrochloric acid showed much lower recoveries in the impingers than the solid-state traps. Ammonia collection efficiencies were slightly higher for the solid state traps and were improved in the impingers when an acidified solution was used as the collection media. The use of solid-state traps, besides being much simpler from both the handling and logistical stand point, eliminates the analyte solubility and evaporation problems frequently seen with the impinger sampling.

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

In semiconductor manufacturing, process errors are likely to depart from normal distributions. For data violating the assumption of normality, classical process capability indices (PCIs) may be misleading in terms of the process behavior. To avoid this, we propose new PCIs with information on the skewness and the kurtosis of a given distribution. Based on a Monte Carlo simulation with various distributions, the formulae of the proposed PCIs were optimized. Compared with Johnson transformation or other approaches, our proposed method is simple in calculation. Therefore, it would have greater applicability for data analysis in semiconductor manufacturing.

Current approaches to control critical dimensions (CD) uniformity during lithography is primarily based on run-to- run (R2R) methods where the CD is measured at the end of the process and correction is done on the next wafer (or batch of wafers) by adjusting the parameter set-points. In this work, we proposed a method to monitor the various photoresist parameters (e.g. photoresist thickness, photoactive compound) and CD in-situ and in real-time. Through modeling and real-time identification, we develop new in-situ measurement techniques for the various parameters of interest in the lithography sequence using existing available data in the manufacturing process.

Run-to-run (R2R) control is now a required component of microlithography processing. R2R control is a form of discrete process control in which the product recipe with respect to a particular process is modified between runs; a "run" can be a lot, wafer or even a die ("shot"). Deployment experience reveals that a cost and technology-effective R2R control solution must be part of a complete Advanced Process Control and equipment automation solution that includes Fault Detection. This complete solution must leverage event-driven technology to support flexibility and reconfigurability, be re-usable via model libraries, be deployed in a phased approach, utilize robust control algorithms, be easily integratable with other components in the manufacturing process, and be extensible to incorporate new technologies as they are developed. In microlithography applications, R2R control solutions are shown to improve process centering and reduce variability resulting in process capability improvements of up to 100%. In the near future, virtual metrology, which harnesses the power of microlithography fault detection along with a prediction engine, will better enable wafer-to-wafer and shot-to-shot feedback control by predicting metrology values for each wafer or die without incurring extra metrology cost or unnecessary waste.

This project is the continuation of work reported previously at this conference (Yu, et. al., SPIE 2009). A new software tool for developing a static scanner fleet matching (SFM) matrix is tested including fleet snapshot and scanner pair drilldown. In addition the latest scanner models can adjust the distortion performance dynamically, at run-time, improving effective overlay performance of the scanner fleet, and allowing more flexibility for mix-and match exposure. The goal is to improve overlay |mean|+3s significantly between scanners for critical layer pairs.

Diffraction Based Overlay (DBO) metrology has been shown to have significantly reduced Total Measurement Uncertainty (TMU) compared to Image Based Overlay (IBO), primarily due to having no measurable Tool Induced Shift (TIS). However, the advantages of having no measurable TIS can be outweighed by increased susceptibility to WIS (Wafer Induced Shift) caused by target damage, process non-uniformities and variations. The path to optimum DBO performance lies in having well characterized metrology targets, which are insensitive to process non-uniformities and variations, in combination with optimized recipes which take advantage of advanced DBO designs. In this work we examine the impact of different degrees of process non-uniformity and target damage on DBO measurement gratings and study their impact on overlay measurement accuracy and precision. Multiple wavelength and dual polarization scatterometry are used to characterize the DBO design performance over the range of process variation. In conclusion, we describe the robustness of DBO metrology to target damage and show how to exploit the measurement capability of a multiple wavelength, dual polarization scatterometry tool to ensure the required measurement accuracy for current and future technology nodes.

Diffraction based overlay (DBO) technologies have been developed to address the tighter overlay control challenges as the dimensions of integrated circuit continue to shrink. Several studies published recently have demonstrated that the performance of DBO technologies has the potential to meet the overlay metrology budget for 22nm technology node. However, several hurdles must be cleared before DBO can be used in production. One of the major hurdles is that most DBO technologies require specially designed targets that consist of multiple measurement pads, which consume too much space and increase measurement time. A more advanced spectroscopic ellipsometry (SE) technology-Mueller Matrix SE (MM-SE) is developed to address the challenge. We use a double patterning sample to demonstrate the potential of MM-SE as a DBO candidate. Sample matrix (the matrix that describes the effects of the sample on the incident optical beam) obtained from MM-SE contains up to 16 elements. We show that the Mueller elements from the off-diagonal 2x2 blocks respond to overlay linearly and are zero when overlay errors are absent. This superior property enables empirical DBO (eDBO) using two pads per direction. Furthermore, the rich information in Mueller matrix and its direct response to overlay make it feasible to extract overlay errors from only one pad per direction using modeling approach (mDBO). We here present the Mueller overlay results using both eDBO and mDBO and compare the results with image-based overlay (IBO) and CD-SEM results. We also report the tool induced shifts (TIS) and dynamic repeatability.

Wafer overlay is one of the key challenges for lithography in semiconductor device manufacturing, this becomes increasingly challenging following the shrinking of the device node. Some of Low k1 techniques, such as Double Exposure add additional burden to the overlay margin because on most critical layers the pattern is created based on exposures of 2 critical masks. Besides impact on overlay performance, any displacement between those two exposures leads to a significant impact on space CD uniformity performance as well. Mask registration is considered a major contributor to within-field wafer overlay. We investigated in-die registration performance on a critical poly-layer reticle in-depth, applying adaptive metrology rules, We used Thin-Plate-Splinefit (TPS) and Fourier analysis techniques for data analysis. Several systematic error components were observed, demonstrating the value of higher sampling to control mask registration performance.

The motivation of this work is to suggest a guide-line to define a practical overlay metrology requirement for a given design rule. Total measurement uncertainty, TMU, of an overlay metrology is defined as the square root of square sum of following items: tool induced shift (TIS)-mean, TIS-3 sigma, dynamic precision, and tool-to-tool match. It is important to remind that the TMU depends on process conditions, thus TMU is different layer by layer. In this study, the impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of the stability of high order overlay correction parameters. By defining the variation range of correctable parameters as a figure of merit, corresponding TMU is determined for a given design rule. By implementing this methodology, 2 nm of TMU value is obtained for 45 nm of DRAM half pitch, based upon simulation results. Similarly, 1.0 nm of TMU requirement is suggested for 36 nm of DRAM half pitch. Detailed methodology and simulation results are discussed.

Operating Characteristic (OC) curves, which are probabilities of lot acceptance as a function of fraction defective p, are powerful tools for visualizing risks of lot acceptance errors. The authors have used OC curves for the overlay sampling optimization, and found that there are some differences in probability of acceptance between theoretical calculation and empirical estimation. In this paper, we derive a theoretical formulation of the probability of acceptance for several simple cases by decomposing overlay errors, and show that the origin of the differences is the use of stratified sampling in overlay inspection.

In recent years, DRAM technology node has shrunk below to 40nm HP (Half Pitch) patterning with significant progresses of hyper NA (Numerical Aperture) immersion lithography system and process development. Especially, the development of DPT (Double Patterning Technology) and SPT (Spacer Patterning Technology) can extend the resolution limit of lithography to sub 30nm HP patterning. However it is also necessary to improve the tighter overlay control for developing the sub 40nm DRAM because of small device overlap margin. Since new process technologies such as complex structure of DPT and SPT, new hard mask material and extreme CMP (Chemical Mechanical Planarization) process have also applied as design rule is decreased, the improvement of process overlay control is very important. In this paper, we have studied that the characterization of overlay performance for sub 40nm DRAM with actual experimental data. First, we have investigated the influence on the intra field overlay and inter field overlay with comparison of HOWA and HOPC and the improvement of inter field overlay residual errors. Then we have studied the process effects such as hard mask material, thermal process and CMP process that affect to overlay control.

Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

The tight overlay budgets required for 45nm and beyond makes overlay control a very important topic. High order overlay control (HOC) is becoming an essential methodology to remove the immersion induced overlay signatures. However, to implement the high order control into dynamic APC system requires FA infrastructure modification and a stable mass production environment. How to achieve the overlay requirement before the APC-HOC system becomes available is important for RD environment and for product early ramp up phase. In this paper authors would like to demonstrate a field-by-field correction (FxFc) or correction per exposure (CPE) methodology to improve high order overlay signature without changing current APC-linear control system.

We have developed the effective method of mask and silicon 2-dimensional metrology. The aim of this method is evaluating the performance of the silicon corresponding to Hotspot on a mask. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. 2-dimensional Shape quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. On the other hand, there is roughness in the silicon shape made from a mass-production line. Moreover, there is variation in the silicon shape. For this reason, quantification of silicon shape is important, in order to estimate the performance of a pattern. In order to quantify, the same shape is equalized in two dimensions. And the method of evaluating based on the shape is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. It is possible to analyze variability of the edge of the same position with high precision. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. - Estimate of the correlativity of shape variability and a process margin. - Determination of two-dimensional variability of pattern. - Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the shape of the same location of Design, Mask, and Silicon in such a viewpoint.

SEM contours are used to complement CD measurements in OPC model calibration. This is done to capture 2D information about printed features into the model while CD measurement data is kept to maintain accuracy for 1D features. As the method progresses, there are emerging challenges that are normally not found in CD based calibration. One such challenge is the need to align SEM contours with calibration features. This is particularly important in determining model accuracy since contour calibration typically involves a cost function that compares the SEM contours to the simulated print images. This work explores a technique to include contour alignment errors into the calibration cost function. For each contour and its corresponding simulated print, the cost function returns an error value for a given set of model parameters. The error represents how well the model simulation compared to input contour. In addition, it also contains information on how far or how close the contour is aligned to simulation. Misalignment is to be eliminated on the fly during calibration and to be reported at the end of calibration. In this paper we describe the proposed technique and compare the results of calibration between aligned and misaligned contour data.

In this paper we demonstrate the process of creating a large-area, extreme field of view (XFOV) SEM image of a critical layer of an IC product, using an array of images captured with a typical, production CD-SEM. Individual CD-SEM images, taken side-by-side over a large area were processed to create a combined extreme field of view (XFOV) image. All feature edges were identified across this XFOV image and the edges extracted, creating feature contours. The feature contours were then compared to design and simulation data, and differences identified.

The model-based library (MBL) matching technique was applied to measurements of photoresist patterns exposed with a leading-edge ArF immersion lithography tool. This technique estimates the dimensions and shape of a target pattern by comparing a measured SEM image profile to a library of simulated line scans. In this study, a double trapezoid model was introduced into MBL library, which was suitable for precise approximation of a photoresist profile. To evaluate variously-shaped patterns, focus-exposure matrix wafers were exposed under three-illuminations. The geometric parameters such as bottom critical dimension (CD), top and bottom sidewall angles were estimated by MBL matching. Lithography simulation results were employed as a reference data in this evaluation. As a result, the trends of the estimated sidewall angles are consistent with the litho-simulation results. MBL bottom CD and threshold method 50% CD are also in a very good agreement. MBL detected wide-SWA variation in a focus series which were determined as in a process window by CD values. The trend of SWA variation, which is potentiality to undergo CD shift at later-etch step, agreed with litho-simulation results. These results suggest that MBL approach can achieve the efficient measurements for process development and control in advanced lithography.

With semiconductor technology moving to smaller patterns after the 45nm hp node, introduction of high-NA immersion lithography progresses, and with it, the challenge of decreasing process latitude. The decreasing lithography tool focus margin is mentioned as one of the key problems of a high-NA immersion lithography process. Tool focus fluctuation has an impact on resist pattern shape and not only does CD change, pattern height also decreases. As a result of previous studies [1][2], it is understood that the resist loss influences pattern formation after etch, and it was confirmed that resist loss is important for CD control. We observe correlation between the resist top roughness and the resist loss, and evaluate the resist loss measurement function by quantifying the resist top roughness. This principle of resist loss detection by measuring roughness is that a changing roughness of resist pattern top is detected as a fluctuation in image brightness on the CD-SEM. A measurement idea was proposed and performance evaluation has already been performed by using one kind of sample. In this study, we demonstrate the validity of resist loss detection by investigating various wafer conditions which contain the dependency by looking at two types of resist and different exposure tool illumination settings. Furthermore, we have confirmed the sensitivity limit of resist loss detection which is approximately above 10nm. Finally, we have discussed improving the resist loss detection sensitivity and considered the applicability of resist loss detection for the litho process monitor.

We present a comparison of different methods to extract area information from images. Two different physical-based algorithms were tested which determine the areas of arbitrarily shaped 3D nano-structures on wafers or photo-masks (e.g. contact holes) using secondary electron images of scanning electron microscopy (SEM). One of these algorithms, called NANOAREA, was developed by the PTB. The other one is the software package MaskEXPRESS, which was developed by Toppan Printing Co., Ltd. In addition to real SEM images we used Monte Carlo generated SEM images of contact holes of different shapes and sizes. For this, the Monte Carlo simulation program MCSEM, developed at PTB, was applied. MCSEM simulates the electron diffusion and secondary electron generation and transport in solid state material and provides simulated SEM images of arbitrary 3D specimen structures. NANOAREA uses basic image processing routines to estimate the edge position of a structure. Then, one-dimensional profiles which intersect the structure boundary perpendicularly are extracted. A one-dimensional edge detection algorithm determines the edge position on each profile. Finally these detected edge positions are used to calculate the polygon area using the triangle method. NANOAREA showed a very small underestimation of the area of about 0.3 % with regard to the Monte Carlo simulations (i.e. sub-pixel deviation). MaskEXPRESS has a similar approach, however employs a different edge detection algorithm. For quadratic contact holes a very high correlation coefficient r larger than 0.99 of the CDs was seen with an offset of about 0.3 nm for the two tested programs. Here the critical dimension (CD) is defined as the square root of the area. The deviations from the mean offset were smaller than 1 nm over the whole investigated range. For analysis of arbitrarily shaped features we used a double T-shaped structure. Also here almost perfect correlation was found (r = 0.98). The observed mean offset in this case was also about 0.3 nm. The offsets depend on the length of the edge and can vary with the shape of the structure, too. Here we report the excellent correlation of the investigated algorithms and programs to determine area parameters from SEM images. The results found are an important prerequisite for harmonized area measurement based on independent algorithms and pave the way to a standardized approach to area determination and reporting of photomask structures.

We have developed a 25-nm pitch multilayer grating pattern for CD-SEM magnification calibration instead of the conventional 100-nm pitch grating reference. The 25-nm pitch grating reference was fabricated by multilayer deposition of alternative alternating SiO₂ and Si layers and then the reference chip was fabricated by substrate bonding and polishing process. Finally the 25-nm pitch grating pattern was achieved using the material-selective chemical etching of the polished cross-sectional surface. We evaluated the 25-nm pitch grating reference chip using CD-SEM. A high-contrast secondary electron image of the grating pattern was obtained under 1-kV acceleration voltage. The uniformity of the 25-nm pitch size of the grating was less than 1 nm in 3σ. The line edge roughness of the grating pattern was also less than 1 nm. Such a fine and uniform grating pattern will fulfill the requirements of a magnification calibration reference for next-generation CD-SEM.

The Critical Dimension Scanning Electron Microscope (CD-SEM) performs automatic measurement according to the recipe conditions programmed in advance. Traditionally, recipe creation requires not only a knowledgeable engineer but also scheduled tool time with appropriate wafers from the production equipment. It will bring a negative impact significantly to overall productivity when CD-SEM is under heavy utilization for creating massive recipe. Besides, the errors from recipe caused could give an additional interruption for production running from assisting measurement and recipe optimization as well. In this paper, we introduce the new concept of a function, naming Average Template, toward improving offline based recipe correction. Average Template allows creating highly robust pattern recognition template against pattern variations as averaging the images which are saved during recipe running, and this new function has been evaluated to prove the benefit of its application in the mass production. DesignGauge (DG) has allowed reliable recipe creation. However, the functionality improvement for stable recipe optimization is effectuated without wafer through the Average Template. Both recipe creation and optimization in robustness are actualized as utilizing this new function in DG, so that tool can keep under production without any interruption.

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single application. All of the most critical device layers today, and even non-critical layers, now require optical proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM) tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding much value to CD-SEM metrology. In addition, as integrated circuit dimensions and pitches continue to shrink, double patterning (DP) has become more common. Thus automatic recipe setup has needed to incorporate capabilities to deal simultaneously with two layers. This has the benefit of allowing the user to measure the two different CD populations and the image shift in the lithography (i.e., the overlay). Thus automatic recipe creation can be used to characterize the DP pattern for both CD and overlay. DesignGauge, the automatic recipe utility for Hitachi CG series CD-SEMs, is not only capable of offline recipe creation, but also can also directly transfer design-based recipes into standard CD-SEM recipes for use with DP processes. These recipes can be used for OPC model-building and verification as with previous DesignGauge applications. The software also provides design template-based recipe setup for production layer recipes, which improves production tool utilization, as production recipes can thus be written offline for new products, improving first silicon cycle time, engineering time to generate recipes, and CD-SEM utilization. Another benefit of the application is that recipes are more robust than with conventional direct image-based pattern recognition. This paper explores the feasibility of matching a two-layer GDS pattern to features in an image, allowing for the more complex measurements involved in DP characterization. This work will evaluate DesignGauge with double litho double etch (DLDE DP), including rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of the recipe creation, recipe execution, and verification of proper measurements of the dual CD populations and overlay.

In this paper, we show Scatterometry simulation software which has the spectroscopy calculation and optimization algorithm systems. We analyze the spectral Scatterometry using the wavelength range of 400nm to around 800nm. The calculation is sped up by parallel computing using a multicore CPU. Threading Building Blocks (TBB) techniques are used in the parallel computing. We calculate the spectroscopy using the rigorous coupled wave analysis (RCWA) which provides a method for calculating the diffraction of electromagnetic waves by periodic grating. A conjugate gradient (CG) method is used to automatically search the data which resembles the given spectrum. In this simulation, we can check the sensitivity for profile measurements. And we provide the results using this simulator.

Due to immaturity of extreme ultra violet (EUV) lithography and resolution limitation of 193 nm immersion lithography for 32 nm node and beyond, various double patterning processes have been developed as an alternative process to shrink device size other than improving resolution of photo lithography. Double patterning has been accepted as a process bridging between 193 nm immersion and EUV lithographic process for 32 nm and 22 nm nodes. Recently, a sidewall-transferred double-patterning process has been introduced to reduce cost and keep enough process margins in device fabrication. For the development of the double patterning process and deployment of the double patterning process to fabrication lines, it is necessary to monitor and control the critical dimensions and profile shapes in the double patterning process. In this paper, we report monitoring of critical dimensions and profile shapes at several process steps of the double patterning process using spectroscopic ellipsometry based scatterometry.

State-of-the-art lithography is often severely influenced by defects that are smaller than the resolution limit of the mask inspection system. However, the mask inspection suffers from noises comparable to signal of the small defect, due to illumination nonuniformity, laser speckle, and fluctuation of the sensor signal. In order to overcome these issues, we propose a novel mask defect inspection method that uses detection optics for polarization variation. This inspection method uses the variation of polarization states which are caused by form birefringence in the mask feature. Thus the defect signals in the polarization-variation image can be obtained with sufficient intensity for much smaller defects than the wavelength. However since pattern edges are especially emphasized in the polarization-variation images, the images can not faithfully be acquired the mask pattern. To avoid these problems, we simultaneously use both conventional transmitted inspection images and the polarization variation images. By using numerical simulation, this paper discusses the validity of the mask inspection method that detects the polarization variation. The simulated results show that this new inspection method is quite effective for 20-nm-size defect and smaller ones.

Lithography potential expands for 45nm node to 32nm device production by the development of immersion technology and the introduction of phase shift mask. We have already developed the mask inspection system using 199nm wavelength with simultaneous transmitted illumination and reflected illumination optics, and is an effectual candidate for hp 32nm node mask inspection. Also, it has high defect sensitivity because of its high optical resolution, so as to be utilized for leading edge mask to next generation lithography. EUV lithography with 13.5nm exposure wavelength is dominant candidate for the next generation lithography because of its excellent resolution for 2x half pitch (hp) node device. But, applying 199nm optics to complicated lithography exposure tool option for hp2x nm node and beyond, further development such as image contrast enhancement will be needed. EUVL-mask has different configuration from transmitted type optical-mask. It is utilized for reflected illumination type exposure tool. Its membrane structure has reverse contrast compared with optical-mask. This nature leads image profile difference from optical-mask. A feasibility study was conducted for EUV mask pattern defect inspection using DUV illumination optics with two TDI (Time Delay Integration) sensors. To optimize the inspection system configuration, newly developed Nonlinear Image Contrast Enhancement method (NICE) is presented. This function capability greatly enhances inspectability of EUVL mask.

As the semiconductor industry moves to 3X technology nodes and below, holistic lithography source mask optimization (SMO) methodology targets an increase in the overall litho performance with improved process windows. The typical complexity of both mask and illumination source exceeds what the lithographic industry has been accustomed to, and presents a novel challenge to mask qualification and metrology. In this paper we demonstrate the latest in aerial imaging technologies of Applied Material's Aera2^TM mask inspection tool. The aerial imaging capability opens the door to a wide variety of metrological measurements analysis at aerial level and provides enabling solutions for mask and scanner qualifications. In particular, we demonstrate core and periphery DRAM pattern process window assessment and MEEF measurements, performed on an advanced test mask.

Trimethylsilanol (TMS) is a low molecular weight / low boiling point silicon-containing, airborne contaminant that has received increased interest over the past few years as an important cause for contamination of optical surfaces in lithography equipment. TMS is not captured well by carbon-based filters, and hexamethyldisiloxane (HMDSO), even though captured well, can be converted to TMS when using acidic filter media commonly used for ammonia removal. TMS and HMDSO co-exist in a chemical equilibrium, which is affected by the acidity and moisture of their environment. This publication shows that HMDSO is converted to TMS by acidic media at concentrations typically found in cleanroom environments. This is contrary to published results that show a re-combination of TMS to HMDSO on acid media. We also demonstrate that, based on its conversion to TMS, HMDSO is not a suitable test compound for hybrid chemical filter performance, as the apparent lifetime/capacity of the filter can be substantially skewed towards larger numbers when conversion to TMS is involved. We show lifetime test results with toluene and HMDSO on acidic and non-acidic filter media. Appropriately designed, asymmetric hybrid chemical filters significantly minimize or eliminate the conversion of HMDSO to TMS, thereby reducing the risk to scanner optical elements. Similarly, such filters can also prevent or reduce acid-sensitive reactions of other AMC when passing through filter systems.

With continued shrinkage of the semiconductor technology node, the inspection of mask with a single preset defect detection sensitivity level becomes impractical because of the increase occurrence of false capturing of defects. Inspection of leading-edge masks with conventional defect detection method, redundant detection of defects such as pseudo defects, or anomalies such as slightly deformed OPCs caused by assist features tend to increase the Turn Around Time (TAT) and cost of ownership (COO). This report describes a new method for the inspection of mask. It assigns defect detection sensitivity levels to local area inspections and is named as Regional Sensitivity Applied Inspection (RSAI). Then, the sensitivity information from each local area is converted into a format that can be fed into a Mask Data Rank (MDR) which is represented on the basis of pattern prioritization determined at the device design stage. Core technologies employing this concept resulted in the shortening of TAT where samples of actual device mask patterns were used. Printability verification functions (PVF) were applied to the advancement of technologies such as to Source Mask Optimization (SMO) technology. We report on the shortening of TAT that was achieved by the implementation of a new inspection technology that combines RSAI with MDR, and employs printability verification functions.

Highly homogeneous glasses and crystalline materials such as CaF₂ are used in high-end microlithographic applications. Residual stresses in the material lead to stress birefringence and thus to imaging errors, which is undesirable for semiconductor manufacture in view of the ever smaller structure sizes. In order to meet the increasing requirements regarding repeatability, lateral resolution and measuring speed, a new type of automated imaging polarimeter has been developed. The measuring apparatus determines the two-dimensional stress birefringence distribution within a large field of view at a high lateral resolution. The short measuring time enables a high sample throughput and makes it possible to analyze time- and temperature-dependent alterations.

Scanner introduction into the fab production environment is a challenging task. An efficient evaluation of scanner performance matrices during factory acceptance test (FAT) and later on during site acceptance test (SAT) is crucial for minimizing the cycle time for pre and post production-start activities. If done effectively, the matrices of base line performance established during the SAT are used as a reference for scanner performance and fleet matching monitoring and maintenance in the fab environment. Key elements which can influence the cycle time of the SAT, FAT and maintenance cycles are the imaging, process and mask characterizations involved with those cycles. Discrete mask measurement techniques are currently in use to create across-mask CDU maps. By subtracting these maps from their final wafer measurement CDU map counterparts, it is possible to assess the real scanner induced printed errors within certain limitations. The current discrete measurement methods are time consuming and some techniques also overlook mask based effects other than line width variations, such as transmission and phase variations, all of which influence the final printed CD variability. Applied Materials Aera2^TM mask inspection tool with IntenCD^TM technology can scan the mask at high speed, offer full mask coverage and accurate assessment of all masks induced source of errors simultaneously, making it beneficial for scanner qualifications and performance monitoring. In this paper we report on a study that was done to improve a scanner introduction and qualification process using the IntenCD application to map the mask induced CD non uniformity. We will present the results of six scanners in production and discuss the benefits of the new method.

Experimental results of tool-to-tool polarization comparison at hyper numerical aperture with POLARIS^TM PSM Polarimetry (Polarization Affected Resist Image Sensor) are presented. Measurements of tool-to-tool variation of the Intensity in the Preferred Polarization State (IPS) are shown with two modes of operation: 1) measurement of relative IPS difference between tools, which does not require calibration with on-board metrology and 2) estimate of actual IPS measurement, which requires calibration with on-board technique. Relative tool-to-tool variation is generally more important, as it, rather than actual IPS values, determines any induced tool-to-tool CD variation. Monitoring single tool stability has been shown in previous work to remain stable to within a fraction of 1%. Tool-to-tool monitoring has additional sources of variation. The example shown illustrates matching with on-board metrology generally within 2%, but up to 4% at a maximum. Some causes of these potential variations are discussed as well as strategies to improve accuracy. The impact of metrology-induced resist burning is assessed and believed to cause uncertainty in the measurement less than 1%. Finally, a set of measurements comparing azimuthal and horizontal-vertical polarization states are shown, illustrating the capability of POLARIS^TM to report the polarization behavior at arbitrary locations within the pupil. Although pupil-averaged IPS values match to the on-board technique within 1.2%, the angular resolved measurements do not necessarily match theoretical values and vary by up to 10%.

Production of objects with 5 to 25 nm width or pitch requires metrology with picometer-scale accuracy. We imaged a new 70-nm pitch standard by AFM and made it traceable to the international (SI) meter. We describe data capture and analysis procedures that produce metrology-quality results from general purpose AFMs and SEMs. We suggest that traceable pitch standards are most useful when the expanded uncertainty (k=2, 95% confidence) is less than ±1.33% for single pitch values and ±0.5% for mean pitch. We show a projected chain of comparisons (roadmap) leading to a 5-nm pitch standard with expanded uncertainty of 52 pm (1.04%) for single values and 16 pm (0.32%) for the mean value, significantly better than the target.

In this communication, we report on our experimental results from the research focused on the application of the electron beam direct writing in the nanometer range. Special care is taken to analyze the forward scattering spread and its influence on the pattering fidelity for patterns with the dimensions in the sub-10nm region. We model, simulate and discuss several different cases of the strategy used in the pattern writing. The sub-pixel address grid is used and the energy beam distribution is analyzed with 1Å resolution. The pre-compensated energy distribution is analyzed from its slope cross-sectional point of view. Additionally, the field factor correction (FFC) dose compensation, the correctness of the built-in FFC compensation for the sub-10nm regime, and its influence on the writing speed is discussed. We map the pre-compensated energy distribution used for the pattern exposure to the developed resist profile modeled by the spline approximation of the experimentally acquired resist contrast curve. The newly established development process for the hydrogen silsesquioxane (HSQ) resist has been tested and applied in its optimal way. Successful sub-10nm patterning with the dimension controllability better than 5% of the critical dimension (CD) was achieved. The experimental setup use JBX-9300FS (used @ 100keV) as the exposure tool, and the HSQ (XR-1541) as the resist. The energy intensity distribution (EID) function used for the proximity effects compensation is calculated by CHARIOT simulation engine.

The ASML extreme ultraviolet lithography (EUV) alpha demo tool is a 0.25NA fully functional lithography tool with a field size of 26×33 mm², enabling process development for sub-40-nm technology. Two exposure tools are installed in two research centers. The main topic of this paper is the examination of the measured pattern roughness LER contributed by measurement (SEM), exposure (EUV exposure tool) and the resists itself. The authors also examined suspected metrology SEM challenges on different EUV resist types exposed by one of the EUV demo tools. Standard CD SEM tests, such as precision and shrinkage were performed in order to get best working conditions. As part of the research, special attention was given to expected electron - material interactions, such as resist's slimming, low contrast and contamination build up on both lines. LER was analyzed in order to determine separately the contribution effect of the exposure tool and the different resists. Additional comparison was performed on different CDs with different orientations and densities.

Recently most of modern absolute measurement rotation the flats or spheres in the interferometer. We review traditional absolute testing of flats methods and emphasize the method of even and odd functions. The rotation of the lens can lead to some errors such as angle rotation error, center excursion error and other coordinate system motion error. We analyze the errors by using Zernike polynomial. The flat or sphere can be expressed as Zernike polynomial which can also be divided into even-odd, odd-even, even-even and odd-odd functions. We can use 36 Zernike polynomials to generate 3 plats A, B, C. Then the six measurements can be generated from the three plats. For the angle rotation error, we can simulate the angle error distribution and substitute in the systems. According the error distribution we can change the arithmetic to improve the measurement accuracy. The results of errors analyzed by means of Matlab are shown that we can change the arithmetic according the coordinate direction motion errors which can be detected to improve the accuracy. The analysis results can also be used in other interferometer systems which have the motion of the coordinate system.

Detection of resist residue and organic contamination after photo resist strip and wafer clean early in the high K/metal gate (HK/MG) manufacturing process flow is critical as it has been known to significantly impact yield. This residue, when exposed to subsequent thermal process steps, transforms into solid hard spot(s), and can then be detected by a wafer inspection tool, but unfortunately it is too late to take corrective action. A unique process control solution to detect the presence of residues was developed using advanced analysis of an optical scattering inspection of a litho checkerboard pattern. The presence of residue was then validated with film thickness measurements.

The focus of airborne molecular contamination (AMC) control within the semiconductor industry, specifically photolithography, has changed significantly over the past decade. As the focal point of concern has shifted from ammonia (or base gases), to acid gases, and recently to organic contaminants, the filtration industry has adeptly grown to provide the necessary filtration solutions. This paper attempts to provide an overview of these changes while reviewing the primary contaminants, how they are removed, the control technologies in use, and how they are applied.

The purpose of this study is to reduce the critical-dimension (CD) bias (i.e., the difference between actual and measured CD values) for very small line patterns with line widths smaller than 15 nm. The model-based library (MBL) matching technique, which estimates the dimensions and shape of a target pattern by comparing a measured SEM image waveform with a library of simulated waveforms, was modified in two ways to enable it to accurately measure very small patterns. The first modification was the introduction of line-width variation into the library to overcome problems caused by significant changes in waveform due to changes in both sidewall shape and line width. This modification improved the measurement accuracy. The second modification was the fixation of MBL tool parameters that relate to signal-intensity conversion to overcome problems caused by the reduction in pattern shape information due to merging of right and left white bands. This modification reduced the solution space and improved the measurement stability. We confirmed the effectiveness of the modification by using simulated images. We then verified the effectiveness of the modified MBL matching by applying it to actual SEM images. Silicon line patterns with line widths in the range 10-30 nm were used in this experiment, and the CD bias was evaluated by one-to-one comparison with atomic force microscopy (AFM) measurements. The CD bias measured by MBL matching for three heights (20, 50, and 80%) was consistent with the AFM results. The CD biases at all heights were smaller than 0.5 nm and the slopes of the CD biases with respect to the CD were smaller than 3%.

Although Scanning Electron Microscopes (SEM) have improved greatly over the last decade the techniques usually employed to measure their performance have not changed significantly in half a century. In particular, describing the imaging performance of an SEM by a single number - its 'resolution' - provides no useful information about its real world imaging capabilities nor about any of the factors that might limit that usefulness of the SEM for tasks such as metrology. The Contrast Transfer Function (CTF) discussed here analyses the way in which the SEM processes signal components of different spatial frequencies. The resultant plot provides information on the noise limited spatial resolution limit, predicts how this will vary with noise level, and provides a powerful general diagnostic capability. This type of measurement, which has become standard practice for transmission electron microscopes, can be performed using the public domain software package IMAGE-J, is rapid, and requires only a specimen offering a broad and flat Fourier spectrum. The capabilities of this approach are demonstrated by a number of examples.

One of the key parameters necessary to assure a good and reliable functionality of any integrated circuit is the Critical Dimension Uniformity (CDU). There are different contributors which impact the total CDU: mask CD uniformity, scanner and lens fingerprint, resist process, wafer topography, mask error enhancement factor (MEEF) etc. In this work we focus on improvement of intra-field CDU at wafer level by improving the mask CD signature using a CDC200^TM tool from Carl Zeiss SMS. The mask layout used is a line and space dark level of a 45nm node Non Volatile Memory (NVM). A prerequisite to improve intra-field CDU at wafer level is to characterize the mask CD signature precisely. For CD measurement on mask the newly developed wafer level CD metrology tool WLCD32 of Carl Zeiss SMS was used. The WLCD32 measures CD based on aerial imaging technology. The WLCD32 measurement data show an excellent correlation to wafer CD data. For CDU correction the CDC200^TM tool is used. By utilizing an ultrafast femto-second laser the CDC200^TM writes intra-volume shading elements (Shade-In Elements^TM) inside the bulk of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. In the present work we will demonstrate a closed loop process of WLCD32 and CDC200^TM to improve mask CD signature as one of the main contributors to intra-field wafer CDU.

In the last years a flourishing number of techniques such as High Order Control or mappers have been proposed to improve overlay control. However a sustainable improvement requires sometimes understanding the underlying causes of the overlay limiting factors in order to remove them when possible or at least to keep them under control. Root cause finding for overlay error is a tough task due the very high number of influencing parameters and the interaction of the usage conditions. This paper presents a breakdown methodology to deal with this complexity and to find the contributors of overlay error variation. We use a Partial Least Squares (PLS) algorithm to isolate the key contributors for correctable terms and a field-to-field linear regression technique to highlight the main causes of residuals. We present a study carried out on 45nm CMOS contact-gate overlay over 687 production wafers exposed in an ASML TWINSCAN XT:1700i Immersion scanner. We present the results of the correlations with the 180 process and equipment variables used for this study. For each isolated contributor we propose an explanation of the underlying physical phenomenon and solutions.

Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates that we use smaller and smaller grid sizes to produce the fine patterns required. These small grids lead to significant overhead in data handling and, more importantly, for the tools that will write and inspect the mask, together making the mask extremely expensive. For two dimensional structures, such as corners, we have very complex structures using either additive or subtractive OPC features to produce the desired shape. However, it is unclear whether these structures need to be so perfect for the electrical task they are intended to perform. In previous work we have created a number of corner type electrical test structures and applied varying degrees of OPC to both the outer and inner corners of the structures, then printed these on doped polysilicon and the electrical effect of the OPC was investigated. This work showed that the electrical effect of OPC on the outer corner was minimal, whereas the inner corner shape had a marked influence upon the electrical resistance of the circuit feature. However, technology continues to move forward and polysilicon gates are being replaced by metal gates for 32nm node. Therefore, in this work we replace the polysilicon with a metal and investigate the size and position of OPC applied to both the outer and inner corners of the structures. The data obtained using the metal structures suggests that as was the case when using polysilicon, OPC on the outside corner has little impact upon a simple circuit's performance, while care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC serifs used.

BEAMETR (BEAm METRology) technique is demonstrated as an attractive solution for automatic measurement of electron beam sizes in two coordinates. The method associates one software and one specially designed pattern chip. The fabrication of new BEAMETR design is performed by electron beam lithography and metal lift-off. A specific bi-layer resist system and proximity correction is used for achieving the requirements for the "pound-key" shape of BEAMETR pattern. Beam sizes in two coordinates (x,y) of Scanning Electron Microscope are measured for various operating conditions. This method allows measuring electron beam sizes down to 2 nanometers.

SEM metrology involves uncertainty of the linewidth measurement because the SEM signal formation is an extremely complex process. In this work, we used an analytical SEM for CD metrology applications on quartz nanoimprint template. The SEM was tuned first to find the best reasonable condition for consistent operation. Beam characterization was done using BEAMETR beam measurement technique. SEM images of templates were taken at optimum conditions. The measurements were done using a) regular imaging processing software and b) using physical model based processing tool myCD. The quartz template was then measured using TEM crossections at selected sites to reveal profile information as metrology comparison reference. The metrology capability and fundamental limitation of analytical SEM operation with regular imaging processing was identified. Information about SEM setup and materials was used. The considerable improvement using the physical modeling imaging process was found.

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput). Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications. Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.

Low-cost effective characterization methodology was developed that allows indirect evaluation of mechanical, geometrical and optical parameters of periodical microstructures in the cases when traditional measurement techniques are not suitable. Proposed methods are applicable for optimization and control of technological processes. Laser diffractometer is used in the experimental works for measurement of optical parameters of periodical microstructure and estimation of geometrical parameters with an error of less than 5% by comparing theoretical and experimental values of diffraction efficiencies of periodical microstructures. This method is suitable for geometry control of periodical microstructures during all technological process. Also an efficient method was developed that is capable to estimate with an error of 5% the depth of periodical microstructures, which have characteristic depths that are larger than the wavelength of coherent light used in the experiment. Quality of periodical microstructures is sensitive to thermal conditions during replication process. Therefore an experimental setup based on Michelson interferometer was developed for the investigation of induced thermal deformation. The radius and stress kinetics could be analyzed for different thickness of coated polymer. These are the problems that are considered in this paper.

In general, it is defined "Chrome-Film Haze", as an invisible film reside on the chrome surface. This type of Haze defect can poise as a "silent killer" because it cannot be seen by naked eyes, nor can be easily detected by our inline Inspection tool. We hypothesize that this kind of haze will block its transmission at chromeside, thus causing its dosage trending on one direction & intrafield corners/centre CD drifting. This type of "haze", if not properly managed, especially on a "Dark-field Low-Transmission" Mask (i.e..Contact)... can cause "Contact Bridging" as a matter of time, resulting catastrophe yield loss on thousands of wafers, in a mass production FAB environment. So far, "Chrome-Film Haze" phenomenon is evident only on our Binary 193nm Reticles, with increased ArF exposures. Somehow, it does not occur on our 193nm PSM Mask yet. This could be attributed to the differences in the PSM & Binary Mask Cleaning material;- 193nm PSM Reticle utilise 100% sulphate-free cleaning while 193nm Binary Mask is not. Thus, we can presumely expect that the sulphate "seeds" left on Chrome side, could have grown over increased ArF exposition, in a matter of time. Current FAB plant managed this kind of "Chrome-Film" Haze, by inserting a "APC Dosage control limit" & "Intrafield Corners/Centre CD" control so that it's dosage will not be allowed to trend unknowingly, causing corners-CD to drift away from its target. From our historical dosage trends, it became so apparent that we can almost predict when it'll hit its next APC dosage limit. Thus, we can draw a conservative wafer exposure count limit before it trigger its APC Dosage limit. In this way, we can be better prepared to plan and manage our production wafer input, in order to minimise the impact of reticle being sent for cleaning.

The semiconductor industry recently concluded that EUV lithography is the most promising candidate to replace ArF for the 22nm half-pitch node and beyond. Significant progress was made in EUV scanner and source technology and EUV resists have achieved acceptable performance levels as well. But issues related to EUV mask inspection and defectivity remain for the most part unanswered. This gap positions EUV masks as the leading risk to the entire technology, and requires a robust solution during the introduction phase of EUVL. In this paper we present results from a EUV mask inspection system. We demonstrate optimal pattern image formation by using illumination shaping, and consider detection of various defect types that represent realistic mask defectivity scenarios. These results demonstrate that DUV-based patterned mask inspection tool can meet the requirements of the pre-production EUV phase, at 32nm half-pitch, and has adequate room to extend to production at the 22nm node.

The progress of optical lithography towards EUV wavelength has placed mask defectivity among major EUV program risks. Traditional mask inspection was carried in the DUV domain at 19x nm wavelength, similar to ArF lithography. As EUV mask patterns approach the 20nm half-pitch level, the resolution of DUV systems approaches its practical limits. At this limit, the lesson learned from ArF lithography is that contrast may be improved significantly by utilizing resolution enhancement techniques such as off-axis illumination shapes. Here we present an experimental study of the effects of illumination and polarization on contrast and detection. We measured a EUV patterned mask with programmed defects using Aera2 mask inspection tool at 193nm wavelength, equipped with a high NA objective. We compared the contrasts of the patterns and the defect detection signals obtained by employing 4 different illumination shapes and three polarization states: linear along x, linear along y, circular polarization. We learned that in order to achieve the best results both in terms of contrast and in terms of detection, it is most important to choose a suitable exposure conditions. In addition, a proper choice of the polarization state of the illumination can also result in some improvement.

SI-traceable critical dimension 3DAFM was used to characterize 25 nm NanoCD linewidth standard. The standard has a uniquely low linewidth roughness (LWR) and can be used as a benchmark during development of advanced patterning technologies. The following results were obtained: (a) Mean LWR for two 25 nm standards with uncertainty ±0.02 nm (0.95 CL). The LWR is below 0.7 nm (1s). (b) Distribution of LWR and linewidth (LW) at 3 line heights (20, 50 and 80% from the line top) along 3 mm segment of the standards. Variations are below 0.25 nm and 0.07 nm (1s) for LW and LWR, respectively. (c) Spatial power spectra of LWR of the standards. The NanoCD spectrum resembles reported earlier spectra of polycrystalline Si.