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- Front Matter: Volume 7488
- Invited Session
- Defect Inspection and Disposition
- Defect Inspection and Repair
- Mask Films, Process Control, and Equipment
- Nano-Imprint and Patterned Media Technology II
- Source-Mask Optimization
- RET and OPC/ORC
- EUV Mask Substrates and Processing
- Patterning Technology and Tools
- Metrology I
- Metrology II
- Mask Cleaning and Maintenance
- Nano-Imprint and Patterned Media Technology III
- Nano-Imprint and Patterned Media Technology IV
- Mask Business
- Mask Data Preparation
- Simulation and Modeling
- EUV Mask Contamination and Cleaning
- EUV Mask Data Preparation and Inspection
- DPL Implementation and RET Manufacturability
- Poster Session: Cleaning/Contamination/Haze
- Poster Session: EUV Mask
- Poster Session: Inspection and Repair
- Poster Session: Mask Data Preparation
- Poster Session: Mask Process Control/Equipment
- Poster Session: Mask Substrate/Blank/Films
- Poster Session: Metrology
- Poster Session: OPC
- Poster Session: Pattern Generation/Equipment
- Poster Session: Simulation and Modeling
- Additional Papers
Front Matter: Volume 7488
Front Matter: Volume 7488
Show abstract
This PDF file contains the front matter associated with SPIE
Proceedings Volume 7488, including the Title Page, Copyright
information, Table of Contents, and the Conference Committee listing.
Invited Session
Mask industry assessment: 2009
Show abstract
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's
assessment is the eighth in the current series of annual reports. With ongoing industry support, the report can be used
as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries.
The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask
industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is
basically the same as the 2005 through 2008 surveys. Questions are grouped into categories: General Business
Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services.
Within each category is a multitude of questions that create a detailed profile of both the business and technical
status of the critical mask industry. This in combination with the past surveys represents a comprehensive view of
changes in the industry.
PMJ panel discussion overview: mask manufacturing with massive or multi-parallel method
Show abstract
Computational lithography appeared with people's expectation expanding to reduce total lithography cost and to
push the resolution limit for launching novel LSI fabrication processes and masks toward advanced LSI devices of
22 nm and beyond. Recently computational lithography grows up into an integration step to achieve the optimum
solution between an illumination source and a mask for creating the resist image on a wafer. This integration
scheme enables us not only to achieve ultimate single exposure but also to attain higher resolution beyond the
physical limitation by means of double patterning technique. The advanced computational lithography requires
massive data volume that urges us to construct further effective multi parallel methods. Photomask Japan
highlighted the computational lithography in a panel discussion titled "Mask Manufacturing with Massive or
Multi-parallel Method" and sub-titled "Massive or Multi-parallel" drives 22 nm (half pitch 32 nm) litho-mask
solution?" We reached a conclusion of "Enhancing computation power and more sophisticated computation
methods could solve the difficulties about further complicated computation".
Defect Inspection and Disposition
SMO photomask inspection in the lithographic plane
Show abstract
Source Mask Optimization (SMO) describes the co-optimization of the illumination source and mask pattern in the
frequency domain. While some restrictions for manufacturable sources and masks are included in the process, the
resulting photomasks do not resemble the initial designs. Some common features of SMO masks are that the line edges
are heavily fragmented, the minimum design features are small and there is no one-to-one correspondence between
design and mask features. When it is not possible to link a single mask feature directly to its resist counterpart,
traditional concepts of mask defects no longer apply and photomask inspection emerges as a significant challenge. Aerial
Plane Inspection (API) is a lithographic inspection mode that moves the detection of defects to the lithographic plane.
They can be deployed to study the lithographic impact of SMO mask defects. This paper briefly reviews SMO and the
lithography inspection technologies and explores their applicability to 22nm designs by presenting SMO mask
inspection results. These results are compared to simulated wafer print expectations.
Aerial image based die-to-model inspections of advanced technology masks
Show abstract
Die-to-Model (D2M) inspection is an innovative approach to running inspection based on a mask design layout data. The
D2M concept takes inspection from the traditional domain of mask pattern to the preferred domain of the wafer aerial
image. To achieve this, D2M transforms the mask layout database into a resist plane aerial image, which in turn is
compared to the aerial image of the mask, captured by the inspection optics.
D2M detection algorithms work similarly to an Aerial D2D (die-to-die) inspection, but instead of comparing a die to
another die it is compared to the aerial image model. D2M is used whenever D2D inspection is not practical (e.g., single
die) or when a validation of mask conformity to design is needed, i.e., for printed pattern fidelity. D2M is of particular
importance for inspection of logic single die masks, where no simplifying assumption of pattern periodicity may be
done. The application can tailor the sensitivity to meet the needs at different locations, such as device area, scribe lines
and periphery.
In this paper we present first test results of the D2M mask inspection application at a mask shop. We describe the
methodology of using D2M, and review the practical aspects of the D2M mask inspection.
Mask pattern recovery by level set method based inverse inspection technology (IIT) and its application on defect auto disposition
Show abstract
At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features
(SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect
disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the
inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then
followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect
disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance.
The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby
enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects
collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and
aerial/wafer image based automated mask disposition.
Defect printability analysis by lithographic simulation from high resolution mask images
Show abstract
We report the development of Mask-LMC for defect printability evaluation from sub-200nm wavelength mask
inspection images. Both transmitted and reflected images are utilized, and both die-to-die and die-to-database inspection
modes are supported. The first step of the process is to recover the patterns on the mask from high resolution T and R
images by de-convolving inspection optical effects. This step uses a mask reconstruction model, which is based on
rigorous Hopkins-modeling of the inspection optics, and is pre-determined before the full mask inspection. After mask
reconstruction, wafer scanner optics and wafer resist simulations are performed on the reconstructed mask, with a wafer
lithography model. This step leverages Brion's industry-proven, hardware-accelerated LMC (Lithography
Manufacturability Check) technology1. Existing litho process models that are in use for Brion's OPC+ and verification
products may be used for this simulation. In the final step, special detectors are used to compare simulation results on the
reference and defect dice. We have developed detectors for contact CD, contact area, line and space CD, and edge
placement errors. The detection results on test and production reticles have been validated with AIMSTM.
Printability verification function of mask inspection system
Show abstract
In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute
size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo
defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of
parameters such as LER and defects of SRAF.
NFT and Brion are jointly developing a mask-image based printability verification system with functions combining
their respective technologies with the results from ASET's research. This report describes such defect detection results
and introduces the development of a mask inspection system with printability verification function.
Defect Inspection and Repair
Using metrology capabilities of mask inspection equipment for optimizing total lithography performance
Show abstract
The demand for aggressive image placement accuracy and CD uniformity for each generation is being increasingly
accelerated by DPT deployment. The method of the correction with the scanner is in effect devised by obtaining the CD
and IP maps of each mask after the mask pattern is drawn. We are developing a technology that generates CD and IP
maps for each mask from the image data of inspection equipment with the ultimate goal of "in-die overlay improvement"
optimizing scanner as well as writer performances. We evaluated the positional measurement function by using NPI
inspection system with the evaluation mask.
High MEEF reticle inspection strategy
Show abstract
Reticle defectivity has been a widely discussed topic in the last few years primarily due to
ongoing haze issues but also because of the increasing number of the qualification methods
available in the fab. Mask shops are taking a closer look at the alternatives to the direct reticle
inspection [1], making a step towards wafer inspection as a valid option for reticle qualification.
High MEEF patterns represent the most interesting and challenging case study due to potentially
comparable sensitivity performance of the wafer inspection and reticle inspection tools as
reported in [2]. A reticle with programmed defects in different environments was used to define
detection limits, capture rates and noise levels for both direct reticle inspection and the inspection
of the wafer print. Reticle inspection was performed using KLA587 tool. For the inspection of
the wafer prints two most advanced DUV inspection tools were used. Defect sizes were defined
on the reticle and on the wafer using SEM CD tools.
The focus of this study was to identify gaps and opportunities existing in the reticle qualification
chain starting with the outgoing qualification at the mask shop and continuing during the reticle
lifetime in the fab. Results and conclusions of this investigation will be presented and discussed
in conjunction with the prospects and possible modifications of pursued approach for 45nm and
the future nodes.
New tools to enable photomask repair to the 32nm node
Show abstract
The AFM-technology based technique of nanomachining has been well-proven in the area photomask repair since
its introduction a decade ago. However, the problems and challenges facing the mask repair operator have
changed significantly in this period, and ongoing engineering platform development has reflected these shifts, as
well as refinements based on specialized experience with nanomachining repair technology. Improvements from
this technical development include improved monitoring and control of the internal tool environment (to minimize
AFM scan noise and thermal drift), and automation to easily and reliably clean and characterize the 3-dimensional
shape of the NanoBitTM apex. For repair applications, improvements will be shown for the automated and
operator-intuitive reconstruction of 3-dimensional nanometer-scale patterns on the photomask with referenced
z-depth and xy alignment regardless of pattern orthogonality. Multiple pattern repair capability is also reviewed
due to a greater diversity of available process options and multi-repair box capability with a common quartz-level
z-reference point. Finally, it will be shown how all of these individual improvements work together to provide
extended repair capability down to the 32 nm technology node.
Simulation based mask defect repair verification and disposition
Show abstract
As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity
and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect
counts pose great challenges in the post inspection defect classification and disposition: which defect is real
defect, and among the real defects, which defect should be repaired and how to verify the post-repair
defects.
In this paper, we address the challenges in mask defect verification and disposition, in particular, in post
repair defect verification by an efficient methodology, using SEM mask defect images, and optical
inspection mask defects images (only for verification of phase and transmission related defects).
We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In
total 20 types of defects were designed including defects found in typical real circuit environments with 30
different sizes designed for each type. The SEM image was taken for each programmed defect after the test
mask was made. Selected defects were repaired and SEM images from the test mask were taken again.
Wafers were printed with the test mask before and after repair as defect printability references.
A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The
software is used to extract edges from the mask SEM images and convert them into polygons to save in
GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to
form mask patterns and were merged back into the original GDSII design file. This merge is for the
purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and
accurate simulation requires including larger area of optical proximity effect. With lithography process
model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If
such complicated model is not available, a simple optical model can be used to get simulated aerial image
intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the
contour (or intensity) differences between defect pattern and normal pattern. With user provided judging
criteria, this software can be easily disposition the defect based on contour comparison. In addition, process
sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model,
which will make mask defect disposition criteria more intelligent.
Challenging defect repair techniques for maximizing mask repair yield
Show abstract
In today's economic climate it is critical to improve mask yield as materials, processes and tools are more time and cost
involved than ever. One way to directly improve mask yield is by reducing the number of masks scrapped due to defects
which is one of the major mask yield reducing factors. The MeRiTTM MG 45, with the ability to repair both clear and
opaque defects on a variety of masks, is the most comprehensive and versatile repair tool in production today. The cost
of owning multiple repair tools can be reduced and time is saved when fast turnaround is required, especially when more
than one defect type is present on a single mask. This paper demonstrates the ability to correct repair errors due to
human mistakes and presents techniques to repair challenging production line defects with the goal of maximizing mask
repair yield and cycle time reduction.
Expanding the lithography process window (PW) with CDC technology
Sz-Huei Wang,
Yu-Wan Chen,
Chung Ming Kuo,
et al.
Show abstract
The continuous shrinking of the semiconductor device nodes requires tough specifications of CD uniformity which
result in narrowing of the lithography process window. Finding methods for expanding the process window will
enable to continue manufacturing at least one more generation using the existing litho equipment.
The CDC technology has been described in detail in past studies beginning in 2006; however it has typically been
studied from a mask shop perspective.
In this paper we will demonstrate a way to improve the CD Uniformity (CDU) on a new mask, which has a CD
uniformity problem that leads to shrinking of the lithography process window, by using the Carl Zeiss CD Control
(CDC) Technology. The methodology used and the process window improvement verification we show are based
purely on fab available techniques and do not require any input from the mask shop.
A production memory product in PSC fab P1/2 showed reduced yield due to reduced process window in one
line/space (L/S) layer. A close investigation in the fab showed wafer CD non-uniformity of 6.5nm Range and
3.95nm 3S in this layer due to a mask CDU problem.
A CDC process to improve the CDU was applied by the Carl Zeiss CDC200 tool based on wafer CD data only.
Post CDC treatment results show that CD Range was reduced to 3.8nm (42% improvement) and 3S was reduced to
1.94nm (51% improvement).
Further assessment of the litho process window of this layer showed an increase of CD-DOF from 0.15um before
(Pre) CDC to 0.30um after (Post) CDC and an exposure latitude increase from 14.1% Pre to 26.7% Post CDC.
To summarize our findings, applying the CDC process to the problematic layers allowed to increase the PW in
Mask Films, Process Control, and Equipment
Post exposure bake tuning for 32nm photomasks
Show abstract
In optimizing e-beam resist process conditions for photomask lithography, the primary
performance measurements for optimization are resolution, critical dimension uniformity
(CDU), line edge roughness (LER), and linearity. Through technology nodes, one
parameter that has consistently shown a critical impact on these factors is the post
exposure bake (PEB) condition. With 32nm e-beam resist technologies having reduced
temperature sensitivity, this paper investigates the current impact of PEB conditions. The
PEB assessment will summarize the influence of PEB temperature, duration and
environment flow on 32 nm positive tone resists by reporting and analyzing two of the
primary performance measurements: CDU and LER.
Reduction of local CD-linewidth variations in resist develop through acoustic streaming
Show abstract
According to the ITRS roadmap for lithography (2008 edition), the CD uniformity requirement of optical masks beyond
32nm HP is less than 1.5nm (3σ). Especially for double patterning lithography, not only the global uniformity but also
the local uniformity is of very high concern. Therefore it is imperative that the develop process will yield CD-linewidth
control independent of pattern sizes or pattern loading, following precisely those pattern size image correction strategies
applied during mask writing (e.g. proximity and fogging correction). Conventional methods of resist develop cannot
meet such requirement without negative side effects (e.g. increased dark loss, pattern collapse, global CD-uniformity
degradation and/or defect issues). The ASonic® nozzle developed by HamaTech APE combines the very favorable dark
loss, defect and global CD-linewidth control benefits of a fast and uniform low impact initial develop dispense (surface
wetting), with an enhanced developer agitation through acoustic streaming, which provides improved local CD-control
independent of pattern size and loading.
The principle functionality of the ASonic® nozzle is described. Developing loading effect is examined with various
conditions and CD linearity, proximity and CD uniformity are also verified.
Plasma characterization of Tetra III chrome etch system
Show abstract
Both Langmuir probe and spatial optical emission spectroscopy (OES) measurements have
been used to characterize the TetraTM chrome etch chamber. Langmuir data was measured over a
range of process pressures between 1.5mT and 10mT and source powers between 150W and 500W.
At 350W, the data show electron and ion densities near 1 x 109 cm-3 for Ar and for Cl2/O2 etch
plasmas. Ion density trends with pressure were observed to be opposite for the two plasmas.
The effect of the third electrode designed in the chamber was demonstrated to reduce ion
density by more than an order of magnitude for Ar plasma and still lower for Cl2/O2 plasma.
Electron temperature and plasma potential are also reduced.
Radial OES measurements are reported with a new apparatus that yields direct spatial
emission data. Spatial scans of infrared emission from atomic Cl were measured under a range of
several chamber conditions already measured with the Langmuir probe. The scans showed that the
emission uniformity above the mask can be adjusted to a flat profile by selection of the process
condition.
Behavior of the molybdenum silicide thin film by 193nm exposure
Show abstract
In order to embody high resolution at 32 nm and below, molybdenum silicide (MoSi) phase shift mask (PSM) is
essential material in the ArF lithography process, generally. But some problems reported from for the variation of PSM
characteristics like transmittance variation and chemical durability. This change in characteristics is an issue for the yield
drop in the semiconductor device manufacturing. So we study the behavior of MoSi PSM thin film in the view point of
the ArF laser exposure in this paper.
Firstly, the problems of MoSi thin film by the 193 nm exposure are observed. From the result, 0.36 % of the
transmittance was changed by 193 nm irradiation with 10 kJ of energy. Accordingly, MoSi thin film characteristics were
degraded by the ArF laser irradiation. The reason for the transmittance degradation by irradiation for MoSi thin film was
analyzed. Also, we found that the oxygen was activated by the ArF laser and this activated oxygen penetrated to MoSi
thin film. Consequently, the transmittance increased by the penetrated oxygen. Then we investigated the improvement
scheme for MoSi thin film's irradiation characteristic. First, the transmittance of the thin film was changed by the
reactive gas ratio change. Also, the Si ratio in the MoSi thin film was changed. Lastly, densification process was applied.
Consequently, the densification process for the MoSi thin film improved the irradiation characteristics.
Mask performance improvement with mapping
Show abstract
Current high end chips require an extremely precise fabrication of lithographic masks. Some of the most critical
parameters are the placement of structures on the masks as well as their dimensional tolerances. Improving these two key
parameters has always been one of the central objectives of the Advanced Mask Technology Center (AMTC). To this
end, the AMTC has complemented its process development by a set of enhancement schemes which are used to
compensate residual process signatures. In this paper, improvements achieved in the area of CD uniformity (CDU) and
pattern placement are shown. The correction schemes take first principle considerations as well as empirical findings into
account. Based on this, a set of design and process parameters is used to determine the spatial corrections which will
optimize mask quality parameters. This enables the AMTC to tailor the writing parameters to the needs of each mask
design. Latest results for the 32nm technology show that values as low as 5nm image placement error and 3nm CDU can
be reached at the same time.
Enhanced laser-writing techniques for bimetallic grayscale photomasks
Show abstract
Under laser exposure, bimetallic thin films of Bi/In and Sn/In oxidize becoming transparent. By controlling the
power, direct-write binary and grayscale photomasks have been produced with the mask's transparency (optical density,
OD), ranging between ~3.0 (unexposed) to <0.22 (fully exposed). Precise 3D micro-optics require both high vertical
accuracy, gray levels over large OD changes, and precise lateral pattern creation. To achieve this result, an OD
measurement system has been developed that provides real-time measurements while the masks are being written.
Using stationary exposures of Bi/In and Sn/In films with varying laser powers, the reduction in OD of the films is
measured with respect to time. Using 1-minute exposures, the films reach a 'saturated' level within a second at 180 mW
while at 50 mW their OD gradually reduces. The influence of film's thickness is examined with thicker films requiring a
longer exposure time in order to reach a similar OD level. For mask-writing, the optimal line spacing is dependent upon
the laser beam's power distribution profile. Using a line-spacing 3-5 times smaller than the effective spot-size,
variations in the patterned mask caused by a Gaussian-distributed beam can be minimized at the cost of increasing the
writing time of the mask by the same factor. The Gaussian-distributed beam at different laser powers is also found to
create shifts in the OD measurements that are problematic for a closed-loop mask-writing system. The influence of the
beam's power distribution is discussed along with solutions to eliminate the problems.
Nano-Imprint and Patterned Media Technology II
Study of program defects of 22nm nanoimprint template with an advanced e-beam inspection system
Show abstract
Nanoimprint lithography (NIL) is a candidate of alternative, low cost of ownership lithography solution for
deep nano-meter device manufacturing12. For the NIL template pattern making, we have been developing the processes
with 100keV SB EB writer and 50keV VSB EB writer to achieve the fine resolution of near 20nm1-7. However,
inspection of nanoimprint template posed a big challenge to inspection system due to the small geometry, 1x comparing
to 4x of Optical mask and EUV mask. Previous studies of nanoimprint template inspection were performed indirectly on
a stamped wafer and/or on a round quartz wafer13. Electron beam inspection (EBI) systems have been widely used in
semiconductor fabs in nanometer technology nodes. Most commonly EBI applications are electrical defects, or voltage
contrast (VC) defects detection and monitoring8-11.
In this study, we used a mask EBI system developed by Hermes Microvision, Inc. (HMI) to directly inspect a
NIL template with line/space and hole patterns half pitched from 22nm to 90nm and with program defects sized from
4nm to 92nm. Capability of inspection with 10nm pixel size has been demonstrated and capability of capturing program
defects sized 12nm and smaller has been shown. This study proved the feasibility of EBI as inspection solution of
nanoimprint template for 22nmHP and beyond.
A cost of ownership model for imprint lithography templates for HDD applications
Show abstract
Cost of ownership projections have often been used to determine the potential costs
associated with the introduction of novel lithography applications. While they are often
controversial and their accuracy or usefulness are a function of the validity of the
assumptions used to build the model; they provide insight to the real technical issues, as
well as, the critical areas that required the most financial and technical resources for
success and profitability. This paper will provide a first look at the key technical and
financial challenges of using nano-imprint technology for the fabrication of hard disk
drives (HDD). The focus will be on the master template/stamp cost of ownership, pattern
generation time, inspection and repair and yield. This paper will not address the costs
associated with replication of the master template because many of the assumptions for
replication robustness have yet to be realized in a production environment.
High-resolution e-beam repair for nanoimprint templates
Show abstract
UV nanoimprint lithography (UV-NIL) is a high-throughput and cost-effective patterning technique for complex nanoscale
features and is considered a candidate for CMOS manufacturing at the 22nm node and beyond. To achieve this
target a complete template fabrication infrastructure including inspection and repair is needed. Due to the 1X
magnification factor of imprint lithography the requirements for these steps are more challenging compared to those for
4X photomasks. E-beam repair is a very promising repair technology for high-resolution imprint templates. It combines
the advantages of precise beam placement using fine resolution images and damage free repair by electron beam induced
chemical reactions. In this work we performed template repair using a new test stand with improved beam and stage
stability. Repeatability of 3D pattern reconstruction with main focus on shrunk lateral repair dimensions and height
control was investigated. The evaluation was done on various features in a 40nm half pitch design. Additionally, the
resolution capability of the new hardware was examined on selected programmed defects in a 32nm half pitch design. A
first qualitative examination of the repaired template was done using top-view SEM images taken from the test stand
before and after repair. The repaired template was then imprinted on 300mm silicon wafers, and the imprinted repaired
defects were analyzed using a SEM Zeiss Ultra 60.
Duplicated quartz template for 2.5 inch discrete track media
Show abstract
The Nano Imprint Lithography (NIL) process has been proposed as a method of making Discrete Track Media (DTM)
for the next generation hard disc. The UV-NIL process is especially practical because of its minimal thermal expansion
and high manufacturing throughput. Quartz template fabrication is a key issue in UV-NIL. Duplication from a Si master
using NIL was studied as a method of such quartz template fabrication. In this method, the UV light radiated through
the quartz substrate to reach the resist. This method avoids typically used Cr (and other hard masks) on the quartz
substrate, eliminating the problem of low throughput caused by low transmission efficiency of the hard mask. The
success of this method therefore depends crucially on the etching selectivity of quartz to NIL resist used as the resist
mask. Using a newly developed NIL resist with high etching selectivity and duplicating by a "hard mask-less" method, a
125nm track pitch (TP), 2.5 inch full-surface quartz template with uniform pattern height was fabricated. A 75nm TP
quartz template of 60nm pattern height was also fabricated using this method.
Source-Mask Optimization
Source-mask co-optimization (SMO) using level set methods
Show abstract
Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes
for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of
photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach
[3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the
contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set
technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization
of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost
function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well.
This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also
utilizes running on a distributed computing environment.
In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended
to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect
of using different emphasis in defining the cost function will also be studied.
Aerial imaging for source mask optimization: mask and illumination qualification
Show abstract
As the semiconductor industry moved to 4X technology nodes and below, low-k1 ArF lithography approached the
theoretical limits of single patterning resolution, a regime typically plagued by marginally small process windows. In
order to widen the process window bottleneck, projection lithography must fully and synergistically employ all available
degrees of freedom. The holistic lithography source mask optimization (SMO) methodology aims to increase the overall
litho performance and achieve a robust process window for the most challenging patterns by balancing between the mask
and illumination source design influences.
The typical complexity of both mask and illumination source that results from a generic SMO process exceeds the
current norm in the lithographic industry. In particular, the SMO literature reports on masks that fully operate as
diffractive optical elements, with features that have little resemblance to the final wafer-level pattern. Additionally, SMO
illumination sources are characterized by parametric or pixelated shapes and a wide range of transmission values.
As a consequence of the new mask and source designs, qualifying the mask for printing and non-printing defects and
accurate assessment of critical dimensions becomes one of the main mask inspection challenges.
The aerial imaging technologies of Applied Material's Aera2TM mask inspection tool provide enabling solutions by
separating out only the defects that matter and accurately measures aerial imaging critical dimensions. This paper
presents the latest numerical and experimental SMO mask qualifications research results performed at Applied Materials
with a mask containing two-dimensional DRAM production structures.
RET and OPC/ORC
Sub-resolution assist features placement using cost-function-reduction method
Show abstract
We proposed a new method of generating and optimizing sub-resolution assist features (SRAFs). This method is based
on a newly proposed ILT algorithm-Cost-function-Reduction method (CFRM). CFRM is proved to be much effective
and efficient than gradient-based algorithm and traditional simulated annealing method. We improve CFRM to be an
initial condition independent algorithm (ICIA) by tuning some running parameters. The robustness of ICIA is verified
numerically by six mask patterns and two mask technologies in partial-coherence image model using 100 randomly
generated mask patterns. Results showed that all are converged to similar final mask patterns with less than 3%
differences of the final image edge placement error (EPE). The skeleton of the final mask pattern can be decided by first
tens of iterations. Based on the above properties, an efficient and effective algorithm is proposed to handle SRAFs
placement. This effectiveness method is demonstrated by different patterns using different mask technologies.
Inverse lithography (ILT) mask manufacturability for full-chip device
Show abstract
Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks
provide significantly better litho performance and need to be enabled for production as one of the leading candidates for
low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in
production. In a prior publication [1], it has been shown at clip level that the Inverse Synthesizer (ISTM) product has the
capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of
nearly ideal ILT mask. The production readiness of ILT needs to be studied at full chip level with various aspects
including mask data fracturing, MRC constraints, writing time, and inspection.
The computation of ILT mask usually starts with the calculation of an optimized contoured mask then followed by
manhattanization step to convert contour into horizontal-vertical segments. By varying the segmentation length during
manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of
segmentation length impact on writing time and lithography performance at full-chip is presented. MRC is another
important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and
inspectability at various selected MRC rules are also presented in the paper.
SRAF enhancement using inverse lithography for 32nm hole patterning and beyond
Show abstract
At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF)
that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF
at a sufficient level through pitch.
SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or
conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random
holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for
certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size
and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of
technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important
mask writing time due to the shotcount 4.
In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse
Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited.
Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of
DOF and Runtime performance for hole patterning
Model-based assist feature placement for 32nm and 22nm technology nodes using inverse mask technology
Show abstract
Inverse imaging has been long known to provide a true mathematical solution to the mask
design problem. However, it is often times marred by problems like high run-time, mask
manufacturability costs, and non-invertible models. In this paper, we propose a mask synthesis
flow for advanced lithography nodes, which capitalizes on the inverse mask solution while still
overcoming all the above problems. Our technique uses inverse mask technology (IMT) to
calculate an inverse mask field containing all the useful information about the AF solution. This
field is fed to a polygon placement algorithm to obtain initial AF placements, which are then cooptimized
with the main features during an OPC/AF print-fix routine to obtain the final mask
solution. The proposed flow enables process window maximization via IMT while guaranteeing
fully MRC compliant masks. We present several results demonstrating the superiority of this
approach. We also compare our IMT-AFs with the best AF solution obtained using extensive
brute-force search (via a first principles simulator, S-litho), and prove that our solution is
optimum.
Model-based assist features
Show abstract
In a recent paper15, we presented a novel method for fully automated model-based generation and optimization
of sub-resolution assist features which, when placed on a contact layer photomask, minimize the variations in the printed
pattern with respect to focus change. Here we extend that methodology to improve the contrast of the light intensity in
addition to minimizing variations caused by focus change.
EUV Mask Substrates and Processing
Correlation of overlay performance and reticle substrate non-flatness effects in EUV lithography
Show abstract
Image placement (IP) and overlay error specifications in the International Technology Roadmap for
Semiconductors (ITRS) continue to get tighter with each successive technology node. One of the
significant contributors to IP error is the non-flatness of the reticle substrate. In this paper, we will discuss
in detail the effect of reticle substrate shape on the overlay performance in extreme ultraviolet (EUV) tools.
Substrate shape-induced overlay effects are important when multiple device levels are printed using EUV
lithography. We present an analysis of 20 blanks with different flatness specifications for overlay
signatures when used for printing multiple device levels. A comprehensive analysis of scanner correctable
and non-correctable errors for different substrate shapes will also be presented. Non-flatness specifications
for EUV blanks will be reviewed based on these reticle-matching results. We will discuss results from
flatness measurements and the effect on overlay budget due to mismatched substrates using several
substrates with different flatness specifications.
Thin absorber EUVL mask with light-shield border for full-field scanner: flatness and image placement change through mask process
Show abstract
When thinner absorber mask is practically applied to the EUVL for the ULSI chip production, it is inevitable to
introduce EUV light shield area in order to suppress leakage of the EUV light from adjacent exposure shots. We believe
that light-shield border of multilayer etching type is promising structure in terms of mask process flexibility for higher
mask CD accuracy
In this paper, we evaluate etching impact of absorber and multilayer on mask flatness and image placement change
through mask process of thin absorber mask with light-shield border of multilayer etching type structure. And then, we
clarify the relation between mask flatness and mask image placement shift.
EUVL ML mask blank fiducial mark application for ML defect mitigation
Show abstract
Fabricating defect-free extreme ultraviolet lithography (EUVL) multi-layer (ML) mask blanks presents a big challenge in
EUVL technology. ML defect sources primarily come from substrate defects and ML deposition adders. Defect
reduction, therefore, needs to address many development aspects, such as substrate material, substrate polishing,
substrate cleaning, blank handling, and ML deposition. High investment cost and potential low blank yield can quickly
drive up EUVL cost of ownership. However, allowing a few defects on the ML blank can improve the blank yield
drastically. Utilizing such defect-blanks through defect mitigation schemes has been proposed. It includes directly
repairing small ML phase and amplitude defects, mask absorber pattern proximity repair, and using absorber pattern to
cover the ML defects. It includes directly repairing small ML phase and amplitude defects,1-2 repairing mask absorber
pattern to compensate the effect of an adjacent ML defect,3 and using absorber pattern to cover the ML defects.4 In each
case, the ML defects will first need to be identified and located during the ML blank defect inspection. To precisely
locate the ML defects on the blank, fiducial marks on the ML blank are needed for mask alignment and defect location
identification.
In this paper, we will present the details of the ML defect mitigation process flow, i.e., using absorber pattern to cover
the ML defects, and the corresponding experimental validation of this mitigation flow. We will also discuss the fiducial
marking scheme, its application in the defect mitigation flow, the error budget of ML defect mitigation, such as defect
position measurement error, fiducial mask position error, e-beam alignment errors, etc.
Actinic EUVL mask blank inspection capability with time delay integration mode
Show abstract
We have been developing an actinic full-field mask blank inspection system to detect multilayer phase defects with dark
field imaging. Using the current system, we have analyzed the probability of defect detection and occurrence of false
defects with variations in defect signal intensity and in background intensity. The result indicates that the size of the
smallest defect for 100 % detection with no false defect at full-field inspection is 2.0 nm in height and 78 nm in width. A
100 % detection of smaller defects, 1.5 nm high and 60 nm wide, with no false defect at full-field inspection requires
46 % reduction of the detection threshold. This means that for further improvement of defect sensitivity, a 46 %
reduction of CCD noise level, or improvement of the defect detection algorithm, will be required.
Patterning Technology and Tools
Development of multiple pass exposure in electron beam direct write lithography for sub-32nm nodes
Show abstract
Electron beam direct write lithography is used in the ASIC manufacturing industry to sustain optical lithography for
prototyping applications, low volume production and for the development of the next technological nodes. However the
standard proximity effects corrections based on dose modulation are not sufficient to provide the patterning accuracy
required for the sub-32nm nodes. New methods are needed to push the resolution capabilities of electron beam
lithography. In a previous paper, a new writing strategy based on multiple pass exposure has been introduced. It consists
in adding small electron Resolution Improvement Features (eRIF) atop the nominal features. Thanks to this new method,
critical lines have been patterned with enlarged energy latitude. In this paper, multiple pass exposure is applied to the
sub-32nm nodes. The influence of the design of the eRIF is analysed in detail. The best conditions in terms of dose, size
and placement of the eRIF are used to establish a methodology to optimize this new strategy. Using multiple pass
exposure, the energy latitude was increased up to about 20% which is three times the energy latitude of the standard
exposure. Then the impact of multiple pass exposure on the writing time of the electron beam tool is studied. It appears
that a compromise has to be found between the writing time and the improvement of the energy latitude. Finally it is
shown that the resolution capabilities of the electron beam lithography can be increased using the multiple pass exposure
strategy.
Charged particle multi-beam lithography evaluations for sub-16nm hp mask node fabrication and wafer direct write
Show abstract
A detailed evaluation study has been performed with respect to the suitability of projection electron and ion multi-beam
lithography for the fabrication of leading-edge complex masks. The study includes recent results as obtained with
electron and ion multi-beam proof-of-concept systems with 200x reduction projection optics where patterns are
generated on substrates using a programmable aperture plate system (APS) with integrated CMOS electronics,
generating several thousands of well defined beams in parallel. A comparison of electron and ion projection multi-beam
writing is provided, in particular with respect to the suitability to expose non-chemically amplified resist (non-CAR)
materials. The extendibility of projection multi-beam technologies for 16nm hp, 11nm hp and 8nm hp mask nodes is
discussed as well as for wafer direct write for 22nm hp and below.
Electron beam mask writer EBM-7000 for hp 32nm generation
Show abstract
Optical lithography is facing resolution limit. To overcome this issue, highly complicated patterns with high data volume
are being adopted for optical mask fabrications. With this background, new electron beam mask writing system, EBM-
7000 is developed to satisfy requirements of hp 32nm generation. Electron optical system with low aberrations is
developed to resolve finer patterns like 30nm L/S. In addition, high current density of 200 A/cm2 is realized to avoid
writing time increase. In data path, distributed processing system is newly built to handle large amounts of data
efficiently. The data processing speed of 500MB/s, fast enough to process all the necessary data within exposure time in
parallel for hp32nm generation, is achieved. And this also makes it possible to handle such large volume dense data as
2G shots/mm2 local pattern density.
In this paper, system configuration of EBM-7000 with accuracy data obtained are presented.
Exposure results with four column cells in multicolumn EB exposure system
Show abstract
In the Mask D2I project at ASET, the authors assembled an electron beam exposure system to prove the concept ofmulti
column cell with character projection technology. They performed beam calibrations in individual column cells to
evaluate the resolution capabilities and stitching accuracies of the deflection fields of the system. Isolated 35nm line
pattern and 60nm 1:1 line-and-space pattern were exposed in each column cell. Present stitching errors among the
deflection fields were less than 15nm. We also evaluated stitching errors of patterns exposed by the different column
cells. The stitching errors among the column cells were estimated to be less than 20nm. We are now investigating the
origins of these errors to improve the exposure accuracies of the multi column cell system.
Metrology I
Results of an international photomask linewidth comparison of NIST and PTB
Show abstract
In preparation for the international Nano1 linewidth comparison on photomasks between nine national metrology institutes,
the National Institute of Standards and Technology (NIST) and the Physikalisch-Technische Bundesanstalt (PTB),
initiated a bilateral linewidth comparison in 2008, independent of and prior to the Nano1 comparison in order to test the
suitability of the mask standards and the general approach to be used for the Nano1 comparison. This paper reports on
the current status of the bilateral comparison. In particular the methods for linewidth metrology applied at NIST and
PTB and its major uncertainty contributions will be discussed based on actual measurements results for both of the mask
standards chosen for the bilateral comparison.
Measurement sampling frequency impact on determining magnitude of pattern placement errors on photomasks
Show abstract
Current methodologies for determining pattern placement errors on production masks are based primarily on limited
sample sizes and Gaussian statistics. These methodologies and accepted practices may not be indicative of the true
nature of pattern placement errors actually occurring on the photomasks. Pattern placement errors can originate from a
variety of sources on e-beam generated photomasks. Random shot placement errors, localized charging and heating,
proximity effects, global charging, and writing strategies may all have an impact on overall pattern placement errors. It
is suspected therefore that pattern placement errors on photomasks are not all well approximated as Gaussian, but
include a number of significant errors with unique spatial signatures that need to be addressed differently. This paper
investigates different measurement sampling strategies on a single leading edge poly layer to determine what level or
amount of measurements might be necessary to more accurately determine the probabilities of the true placement errors
on the photomask, and what spatially dependent components may or may not be accurately represented in the
measurements.
A 193nm optical CD metrology tool for the 32nm node
Show abstract
A novel optical critical dimension (CD) metrology tool equipped with a 193 nm laser source and a high numerical
aperture objective (NA=0.9) is under development at the Physikalisch-Technische Bundesanstalt (PTB), the National
Metrology Institute of Germany. The CD tool is designed for characterization of photomasks up to 6-inch and offers "atwavelength"
measurements for current and future 193 nm lithography. Design, construction and realisation of the CD
metrology tool is presented in this paper. The illumination system, which employs a multi-mode DUV fiber to reduce the
lateral coherence of the laser beam, is detailed with numerical simulation and experimental investigation. Combined with
precision optical modelling, this optical CD tool will be applicable for quantitative determination of the microstructures
on 32 nm node photomasks with uncertainty less than 10 nm.
How much is enough? An analysis of CD measurement amount for mask characterization
Show abstract
The demands on CD (critical dimension) metrology amount in terms of both reproducibility and measurement uncertainty
steadily increase from node to node. Different mask characterization requirements have to be addressed like very small
features, unevenly distributed features, contacts, semi-dense structures to name only a few. Usually this enhanced need is met
by an increasing number of CD measurements, where the new CD requirements are added to the well established CD
characterization recipe. This leads straight forwardly to prolonged cycle times and highly complex evaluation routines. At the
same time mask processes are continuously improved to become more stable. The enhanced stability offers potential to
actually reduce the number of measurements. Thus, in this work we will start to address the fundamental question of how
many CD measurements are needed for mask characterization for a given confidence level.
We used analysis of variances (ANOVA) to distinguish various contributors like mask making process, measurement tool
stability and measurement methodology. These contributions have been investigated for classical photomask CD
specifications e.g. mean to target, CD uniformity, target offset tolerance and x-y bias. We found depending on specification
that the importance of the contributors interchanges. Interestingly, not only short and long-term metrology contributions are
dominant. Also the number of measurements and their spatial distribution on the mask layout (sampling methodology) can be
the most important part of the variance. The knowledge of contributions can be used to optimize the sampling plan.
As a major finding, we conclude that there is potential to reduce a significant amount of measurements without loosing
confidence at all. Here, full sampling in x and y as well as full sampling for different features can be shortened substantially
almost up to 50%.
Metrology II
Photomask metrology using a 193nm scatterfield microscope
Show abstract
The current photomask linewidth Standard Reference Material (SRM) supplied by the National Institute of
Standards and Technology (NIST), SRM 2059, is the fifth generation of such standards for mask metrology.
The calibration of this mask has been usually done using an in house NIST ultra-violet transmission microscope
and an Atomic Force Microscope (AFM). Recently, a new optical reflection scatterfield microscope has been
developed at NIST for wafer inspection, Critical Dimension (CD) and overlay metrology purposes.
Scatterfield microscopy relies on illumination engineering at a sufficiently large Conjugate Back Focal Plane
(CBFP) of the microscope.1 Our new scatterfield reflection microscope uses 193 nm excimer laser light as well as
sophisticated configurations to allow measurement of both the image plane and the Fourier plane using full-field
and angle-resolved illumination. By reducing the wavelength compared to many current metrology tools that
work in the visible light and near ultra-violet range, we have made substantial improvements in image resolution2
and commensurate gains in sensitivity to geometrical parameters.
We present a preliminary study on the use of this new microscope to calibrate and measure features of this SRM
photomask. The 193 nm scatterfield microscope is used in full-field mode with a NA range from 0.12 to 0.74
using our scatterfield imaging method. Experimental results obtained on isolated lines for different polarization
states of the illumination are presented and discussed. Pitch measurements are compared to the measurements
done on our NIST Ultra-Violet (UV) transmission microscope.
Experimental test results of pattern placement metrology on photomasks with laser illumination source designed to address double patterning lithography challenges
Show abstract
Double Patterning Lithography techniques place significantly greater demand on the requirements for pattern placement
accuracy on photomasks. The influence of the pellicle on plate bending is also a factor especially when the pellicle
distortions are not repeatable from substrate to substrate. The combination of increased demand for greater accuracy and
the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements
on actual device features. The above requirements triggered development of a new generation registration metrology tool
based on in-depth experience with the LMS IPRO4. This paper reports on the initial experimental results of DUV laser
illumination on features of various sizes using unique measurement algorithms developed specifically for pattern
placement measurements.
In-die metrology on photomasks for low k1 lithography
Show abstract
New lithography techniques like Double Patterning, Computational Lithography and Source Mask Optimization will be
used to drive immersion lithography to its limits. This results in several challenges for the mask maker. The extremely
high MEEF values amplify small process variations on the mask features on the wafer. Complex mask features using
sophisticated OPC and assist features as well as double patterning tightens the registration and CDU specification at the
same time. Especially, overlay becomes more and more critical and must be ensured on every die. In-die registration and
CD metrology on arbitrary features is required to measure mask performance precisely.
In this paper an overview about several in-die metrology techniques will be given. Application of in-die CD
measurements using the Zeiss WLCD32 tool as well as in-die registration measurements using the Zeiss Prove tool will
be shown and discussed.
Critical dimension uniformity using reticle inspection tool
Show abstract
The Critical Dimension Uniformity (CDU) specification on photomasks continues to decrease with each successive node.
The ITRS roadmap for optical masks indicates that the CDU (3 sigma) for dense lines on binary or attenuated phase shift
mask is 3.4nm for the 45nm half-pitch (45HP) node and will decrease to 2.4nm for the 32HP node. The current
capability of leading-edge mask shop patterning processes results in CDU variation across the photomask of a similar
magnitude.
Hence, we are entering a phase where the mask CDU specification is approaching the limit of the capability of the
current Process of Record (POR). Mask shops have started exploring more active mechanisms to improve the CDU
capability of the mask process. A typical application is feeding back the CDU data to adjust the mask writer dose to
compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Mask makers are
currently using the CD-SEM tool for this application. While the resolution of SEM data ensures its position as the
industry standard and continued requirement to establish the photomask CD Mean to Target value, a dense measurement
of CDs across the reticle with minimal cycle time impact would have value.
In this paper, we describe the basic theory and application of a new, reticle inspection intensity-based CDU approach
that has the advantage of dense sampling over larger areas on the mask. The TeraScanHR high NA reticle inspection
system is used in this study; it can scan the entire reticle at relatively high throughput, and is ideally suited for collecting
dense CDU data. We describe results obtained on advanced memory masks and discuss applications of CDU maps for
optimizing the mask manufacturing process. A reticle inspection map of CDU is complementary to CD-SEM data. The
dense data set has value for various applications, including feedback to mask writer and engineering analysis within the
mask shop.
IntenCD technology for fast and accurate scanner performance determination
Show abstract
Scanner performance is influenced by the quality of its illumination, mechanical and optical elements and the impact of
these factors on the printed wafer. Isolation of the aggregated scanner errors from other sources of error on the printed wafer
is a challenging task since the total error budget of the lithography process consists of many dynamic sources, such as wafer
planarity and film stack properties.
The mask is conceptually part of the scanner optics and integral to the imaging process. Therefore the mask error
contribution to the overall error becomes relevant for any advanced lithography process.
Discrete mask measurement techniques are currently used to create across mask CDU maps. By subtracting these maps from
their final wafer measurement CDU map counterparts, it is possible to assess within certain limitations the real scanner
induced printed errors. The current discrete measurement methods are time consuming and some overlook errors other than
linewidth variations, such as transmission and phase variations, all of which influence the final printed CD variability.
In this paper we present a methodology, which leverages Applied Materials Aera2tmmask inspection tool, based on a socalled
IntenCDtm technology.
IntenCD aerial imaging produces maps by scanning the mask at high speed, offer full mask coverage and accurate
assessment of all mask induced errors simultaneously, making it ideal for mask CDU characterization and scanner
qualification.
Mask Cleaning and Maintenance
Advances in CO2 cryogenic aerosol technology for photomask post AFM repair
Show abstract
As the mask technology moves towards production of 36 nm and 22 nm DRAM half
pitch nodes, printing features and sub-resolution assist features (SRAF) shrink below 80
nm. These narrow features become more fragile and place new demands on cleaning
processes for a physically non damaging solution. These challenges include compatibility
with new materials, oxidation, chemical contamination sensitivity, proportionally
decreasing printable defect size, and a requirement for a damage-free clean. CO2
cryogenic aerosol cleaning has, for many years, shown potential to offer a wide process
window for meeting some of these new challenges. CO2 cryogenic aerosol cleaning for
post AFM repair debris cleaning has been used for many years on masks greater than 90
nm DRAM half pitch nodes. Until recently, CO2 purity and delivery hardware issues
resulted in foreign material adder (FMACO2) contamination and SRAF damage below 150
nm critical feature size. Some key desirable properties of CO2 cryogenic aerosol cleaning are the non-oxidizing
and non-etching properties when compared to current chemical wet clean processes. In
this paper, recent advancements of CO2 cryogenic aerosol cleaning technology are
presented, highlighting improvements in the areas of FMACO2 reduction, lowering the
critical feature size without damage, and electrostatic discharge (ESD) mitigation. Key
aspects of successful CO2 cryogenic aerosol cleaning include the spray nozzle design,
CO2 liquid purity, and integrated system design. The design of the nozzle directly
controls the size, flux, and velocity of the CO2 snow particles. Methodology and
measurements of the solid CO2 particle size and velocity distributions will be presented,
and their responses to various control parameters will be discussed. FMACO2 mitigation
can be achieved only through use of highly purified CO2 and careful materials selection
of the delivery hardware. Recent advances in CO2 purity will be discussed and data
shown. The mask cleaning efficiency by CO2 cryogenic aerosol and damage control is essentially
an optimization of the momentum of the solid CO2 particles and elimination FMACO2.
Data on CO2 tribocharge mitigation, the main cause of ESD, will be presented and
application to current technology nodes discussed. The previous damage threshold of 150
nm SRAF structures have been reduced below 60 nm and data will be shown indicating
sub-50 nm is possible. The tool capability has been improved from previously doing
local cleaning of AFM repair sites to a full mask clean with prospects of replacing certain
wet clean steps where phase and transmission are degraded.
Nano-Imprint and Patterned Media Technology III
6-inch circle template fabrication for patterned media using a conventional resist and new chemically amplified resists
Show abstract
Nanoimprint lithography (NIL) is one promising candidate for fabricating a patterned media to be used in the next
generation of hard disk drives. It is expected that the pitch, characterizing the feature size of the media will become as
small as about 50 nm for discrete-track recording (DTR) in 2010 or 2011. There are two major issues, one is fine groove
formation and the other is long e-beam writing time. Writing time is estimated more than one week if we use
ZEP520A-resist. To solve these problems, master template fabrication processes using combination of silicon substrate
and new CAR were evaluated. As a result, the capability of 1:2 groove and land ratio 50 nm pitch LS pattern formation
with new CAR which sensitivity is approximately 2.5 times higher than ZEP520A was shown.
A new x-ray metrology for profiling nanostructures of patterned media
Show abstract
We have developed a new x-ay metrology for profiling surface periodic structure of discrete track patterned
media. X-rays irradiate surface of the discrete track media with a shallow glancing angle, which is close to the critical
angle of total external reflection of the surface material. The measured x-ray scattering pattern is reflected to the average
cross-sectional profile of the grating. Resist pattern of circular discrete track with120 nm-pitch on 65 mmφ magnetic disc
is analyzed by the present x-ray metrology. The obtained profile, for example, line width, height of the track and so on
are well agreed with that observed by cross-sectional scanning electron microscopy. The wavelength of x-ray that we use
is 0.154093 nm and it is enough shorter than the critical length of the grating structure, even when the track width
becomes 10 nm or less. Therefore, the resolution of the x-ray metrology will be maintained well that of required in
future. In addition, x-ray metrology is able to profiling the cross-sectional structure with nondestructively due to hightransmissivity
of x-rays for the materials. Furthermore, the optical parameter of the materials is well established in x-ray
region, therefore, it is applicable not only resist patterns, but also real device patterns only with certain physical/optical
parameters.
Inspection of 32nm imprinted patterns with an advanced e-beam inspection system
Show abstract
We used electron beam (e-beam) inspection (EBI) systems to inspect nano imprint lithography (NIL)
resist wafers with programmed defects. EBI with 10nm pixel sizes has been demonstrated and
capability of capturing program defects sized as small as 4nm has been proven. Repeating defects
have been captured by the EBI in multiple die inspections to identify the possible mask defects. This
study demonstrated the feasibility of EBI as the NIL defect inspection solution of 32nm and beyond.
SEM CD metrology on nanoimprint template: an analytical SEM approach
Show abstract
Critical dimension metrology is the most needed feedback in nanofabrication and automatic CDSEM-based methods
are by far the industrial standard for its well-established methodology and ease of programming and flexibility in
measurement setup and operation. The dimensional measurements from SEMs consist of two steps, the first being the
pixel based electron emission signal intensity profile generation and the second being the algorithm treatment on the
generated intensity profile for the dimension determination. However, SEM metrology involves uncertainty of the
measurement in the signal processing step, because the SEM signal formation is an extremely complex process
depending on the pattern geometry, materials, detector setup, and beam voltage. Analytical SEMs are even less
optimized for the task of quantitative metrology, especially at the CD ranging below 100 nm.
In this work, we used an analytical SEM for CD metrology applications on quartz nanoimprint template from the
perspective that only analytical SEM is accessible. The machine was tuned and beam characterization was done first to
find the best reasonable condition for consistent manual operation using BEAMETR beam measurement pattern and
software. The optimized beam condition set was then used for image collection on pitch pattern quartz template and
the measurements were done using regular imaging processing and physical model based processing tool myCD. In
order to discuss the spot size on the scan signal and the resulting influence on CD measurements, we used CHARIOT
simulation software for simulated intensity profile as demonstration. The quartz template was then measured through a
mask CDSEM for final data comparison. Selected sites were cross sectioned to reveal profile information as metrology
comparison reference. Through our exercise, the metrology capability and fundamental limitation of analytical SEM
operation with regular imaging processing was identified and the improvement using the physical modeling imaging
process was verified.
Nano-Imprint and Patterned Media Technology IV
Optical metrology for template and disk patterned imprints
Show abstract
Driven by the ever-growing storage density needs, the hard-disk drive (HDD) industry is transitioning to patterned
magnetic media. For the first time, magnetic media disk production will require advanced lithography and critical
dimension (CD) process control. The CDs of patterned media features will have to be smaller than the most advanced
semiconductor design rules, and nano-imprint lithography (NIL) is the only candidate to yield such small dimensions at
the low cost the industry demands. After an introduction to the industry's drivers for the transition, we give a summary
of the NIL process for HDD media production, and an estimate of the CD metrology requirements for future process
control. We then present some arguments and results to illustrate how a spectroscopic ellipsometry based scatterometry
technique could be a good candidate to meet the CD control requirements of the patterned media roadmap. Simulations
and experimental results on several DTM structures, for both template and disk imprints are discussed.
A non-destructive metrology solution for detailed measurements of imprint templates and media
Show abstract
This study investigates a non-destructive optical metrology technique, that furnishes measurement solutions for hard
drive discrete track recording (DTR) and bit patterned media (BPM) templates and imprints. From the measurement and
analysis of polarized reflectance and transmittance, feature height and profile of DTR and BPM templates and imprints,
as well as residual layer thickness of imprints, are accurately determined, and uniformity maps of these parameters are
produced in a fraction of a minute. Simulations of theoretical polarized reflectance and transmittance, relating to next
generation structures, demonstrate that the optical metrology solution has capability for future products.
Jet and flash imprint lithography for the fabrication of patterned media drives
Show abstract
The ever-growing demand for hard drives with greater storage density has motivated a technology shift from
continuous magnetic media to patterned media hard disks, which are expected to be implemented in future
generations of hard disk drives to provide data storage at densities exceeding 1012 bits per square inch. Jet and
Flash Imprint Lithography (J-FILTM) technology has been employed to pattern the hard disk substrates. This paper
discusses the infrastructure required to enable J-FIL in high-volume manufacturing; namely, fabrication of master
templates, template replication, high-volume imprinting with precisely controlled residual layers, dual-sided
imprinting and defect inspection. Imprinting of disks is demonstrated with substrate throughput currently as high as
180 disks/hour (dual-sided). These processes are applied to patterning hard disk substrates with both discrete tracks
and bit-patterned designs.
Mask Business
Fabless company mask technology approach: fabless but not fab-careless
Show abstract
There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask
facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of
situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely
with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both
technology development and benefited from corporations. Our involvement in manufacturing is driven by the following
three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable
design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been
involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The
second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to
market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough
visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been
observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To
achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity
has to be monitored.
Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial
development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges
for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time
(TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that
assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a
need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design
criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask
manufacturing has contributed significantly to our success in past many nodes and will continue.
A universal mask management relational database
Show abstract
With the emergence of submicron technologies new product development costs have soared to reach an average of
$15M. This includes all direct and indirect costs from specification to the start of volume production. At 65nm a single
mask set costs more than $1M. As statistically final silicon needs at least one rework on metal layers, we can roughly
estimate that mask budget is at least 10% of the chip development.
It is then obvious that IDM companies as well as fabless design centers must take special care for mask management.
Improving data exchange between mask data preparation teams and mask shops by using the SEMI-P10 standard has
been a great step, but building an internal mask data preparation database to warrant a safe traceability of all masks still
remains a challenge.
This paper describes a relational database, which manages all the data related to mask data preparation during the entire
life of the project. This database is not only dedicated to mask ordering, it also includes feedbacks on mask
manufacturing from the mask shop and on silicon manufacturing from the production line making mask traceability
possible.
Mask Data Preparation
Deployment of OASIS.MASK (P44) as direct input for mask inspection of advanced photomasks
Show abstract
With each new process technology node, chip designs increase in complexity and size, leading to a steady
increase in data volumes. As a result, mask data prep flows require more computing resources to maintain
the desired turn-around time (TAT) at a low cost. The effect is aggravated by the fact that a mask house
operates a variety of equipment for mask writing, inspection and metrology - all of which, until now,
require specific data formatting. An industry initiative sponsored by SEMI® has established new public
formats - OASIS® (P39) for general layouts and OASIS.MASK (P44) for mask manufacturing equipment -
that allow for the smallest possible representation of data for various applications. This paper will review a
mask data preparation process for mask inspection based on the OASIS formats that also reads
OASIS.MASK files directly in real time into the inspection tool. An implementation based on standard
parallelized computer hardware will be described and characterized as demonstrating throughputs required
for the 45nm and 32nm technology nodes. An inspection test case will also be reviewed.
Mask data prioritization based on design intent - II
Show abstract
Mask D2I/ASET has been working to reduce TAT for mask writing and inspection. As a part of this program we have
developed a data flow process for mask manufacturing in which we refer to design intent information in order to reduce
TAT of mask manufacturing processes. We convert design level information "Design Intent (DI)" into priority
information of mask manufacturing data known as "Mask Data Rank (MDR)" so that we can identify and sort out the
importance of reticle patterns from the view point of the design side. As a result, we can reduce mask writing time and
mask inspection time significantly. Our objective is to build efficient data flow conversion system from DI to MDR.
Automatic DI creation flow from EDA tools, and an automatic MDR creation flow from the created DI have already
been established. We extracted design intents (Litho hotspot area, Shield net, Gate channel area, Timing critical net,
Dummy metal fill, Power ground net, etc.) from the database in EDA tools automatically, and converted them into MDR.
In an earlier paper, we had shown that by using this flow, we could achieve TAT reduction in mask writing and mask
inspection for a limited number of design data. In this presentation, we will show TAT reduction results for actual device
design data; we will then discuss related issues and their solutions.
Favorable hierarchy detection through Lempel-Ziv coding based algorithm to aid hierarchical fracturing in mask data preparation
Show abstract
Runtime of the Mask Data Preparation (MDP) tool is largely dependent on the hierarchy of the input layout data. In this
paper, we present a technique where a hierarchical or flat input design layout or almost flat mask data can be converted
into a favorable hierarchical data which can be directly used by MDP tools for fracturing. A favorable hierarchy is a
hierarchy of cells where polygons within cells do not overlap with each other even if bounding boxes of cells might
overlap with each other. This is an important characteristic which can be intelligently made use of by intra-polygonal
operations like fracturing. Otherwise, a mask data preparation (MDP) tool has to take the responsibility for resolving
overlaps among polygons, which slows down the processing and increases the data size. MDP on a favorable hierarchy
will thus speed up the fracturing or re-fracturing steps and also minimize the output fractured data size, as shown through
the experimental results in the paper.
In the proposed technique, the favorable hierarchy is generated using a modified version of the Lempel-Ziv (LZ) coding
algorithm, which was originally devised for compressing character strings. A hierarchical fracturing algorithm can be
employed to work on the favorable hierarchy generated, which will utilize the property of a favorable hierarchy that
polygons do not overlap with each other. Apart from the obvious runtime benefits, such a favorable hierarchy allows
considerable reduction in fractured data size as most mask data formats allow representation of a hierarchy containing
two levels.
Latest results and computing performance of the ePLACE data preparation tool
Show abstract
At the EMLC 2009 in Dresden the data preparation package ePLACE was already presented. This package has been
used for quite different applications covering mask write, direct write and special applications. In this paper we will
disclose results achieved when using the ePLACE package for processing of layout data of immediate interest. During
the evaluation phase of the new solution we could benefit from broad experience we collected over many years with the
fracture performance of the MGS software, which is one core element of today's ePLACE package.
A key interest of this paper is the investigation of the scalability of computing solutions as a cost-effective approach
when processing huge data volumes with the new solution. This is reflected against current state-of-the-art data processing
tasks being part of both mask write and direct write applications.
Furthermore, we evaluated visualization and simulation possibilities of the ePLACE package with respect to its use with
latest layouts in various applications.
The improved performance of the data preparation package including its adaptation to new e-beam lithography options,
as, for instance, the incorporation of the cell projection capability or the newly developed Multi Shaped Beam (MSB)
technology, will be also discussed.
As an example the matching of the data path with a Vistec SB3055 will be outlined. Processing of Design For E-Beam
(DFEB) data (including cell contents) and their conversion to real exposure data is reported. The advantages of the
parallel use of standard shaped beam und cell projection technologies are highlighted focussing on latest writing time
yields achieved when applying the CP feature.
Simulation and Modeling
Impact of mask roughness on wafer line-edge roughness
Show abstract
The influence of line-edge roughness (LER) of an optical photomask on
the resulting printed wafer LER is investigated. The LER Transfer function
(LTF) proposed by Naulleau and Gallatin, and later corrected by Tanabe, is
shown to be a very useful tool for evaluating the low-pass filtering behavior of
the imaging tool and its impact on the transfer of mask LER to the wafer. Highfrequency
mask LER can also impact wafer LER by lowering the normalized
image log-slope (NILS) of the image, though it would take a large amount of
mask LER before this affect would be noticeable. Low-frequency mask LER,
most likely due to mask writer errors such as shot placement or rotation errors,
will produce wafer LER that may be significant in magnitude. Further work
characterizing the magnitude and frequency content of mask LER over many
different masks and processes is needed.
Challenges for the 28nm half node: Is the optical shrink dead?
Show abstract
A half-node process has been routinely used to deliver incremental improvements in process control and hardware
availability in order to continue Moore's Law. Traditionally, due to the imaging requirements, parameters such as
numerical aperture and partial coherence were not set to their maximum resolution settings, thus leaving room in
hardware and RET recipes to accommodate incremental imaging requirements. However, as hardware availability and
computational lithography methods are stressed to the maximum of their capabilities to deliver the next technology
nodes, it is worth asking the question if such optical shrinks continue to be viable moving forward. Already 28nm
layouts scaled down from the original 32nm layouts are starting to show signs of configuration limitations dictated by
the available imaging hardware.
In this paper we show that two-dimensional features determine the feasibility of migrating successfully to the next halfnode
even when one-dimensional metrics suggest that such migration should be possible. While it has been proposed
that methodologies that are based on fabrics can guarantee composability and are intrinsically easier to migrate to
smaller nodes, such approaches are mostly valid for processes in which the frequency distribution of the object to be
imaged remains compatible with the hardware and RET of choice. This paper suggests that the distribution and extent
of the layout fabric discontinuities present one of the major hurdles to composability. In other words, it is not only
necessary to determine the best pitch and width of the underlying fabric it becomes crucial to determine the distribution
of the discontinuities present in the layout to build discrete devices.
Given that the feasibility of a half-node process is determined mostly by its ability to achieve denser patterns without
non-trivial layout modifications, in this paper we show that it is important to start looking at the explicit layout
configuration aspects that determine layout printability. We have selected a pair of prototypical layout configurations
common across all technology nodes of interest and have determined their intrinsic failure conditions for a given
process.
The results indicate that for a well padded 32nm process it may still be possible to perform an optical 28nm shrink with
only a minimum of manual intervention, assuming that certain layout configurations are removed or carefully
monitored during production. However, the nature of the analysis suggest that moving forward to 22nm and in the
absence of higher-resolution hardware (i.e. EUV) optical shrinks that require little or no layout modifications to the
desired patterns to be printed may no longer be possible.
Reduced basis method for computational lithography
Show abstract
A bottleneck for computational lithography and optical metrology are long computational times for near field
simulations. For design, optimization, and inverse scatterometry usually the same basic layout has to be simulated
multiple times for different values of geometrical parameters.
The reduced basis method allows to split up the solution process of a parameterized model into an expensive
offline and a cheap online part. After constructing the reduced basis offline, the reduced model can be solved
online very fast in the order of seconds or below. Error estimators assure the reliability of the reduced basis
solution and are used for self adaptive construction of the reduced system.
We explain the idea of reduced basis and use the finite element solver JCMsuite constructing the reduced
basis system. We present a 3D optimization application from optical proximity correction (OPC).
Efficient analysis of three dimensional EUV mask induced imaging artifacts using the waveguide decomposition method
Show abstract
This paper employs the Waveguide decomposition method as an efficient rigorous electromagnetic field (EMF) solver
to investigate three dimensional mask-induced imaging artifacts in EUV lithography. The major mask diffraction induced
imaging artifacts are first identified by applying the Zernike analysis of the mask nearfield spectrum of 2D
lines/spaces. Three dimensional mask features like 22nm semidense/dense contacts/posts, isolated elbows and line-ends
are then investigated in terms of lithographic results. After that, the 3D mask-induced imaging artifacts such as feature
orientation dependent best focus shift, process window asymmetries, and other aberration-like phenomena are explored
for the studied mask features. The simulation results can help lithographers to understand the reasons of EUV-specific
imaging artifacts and to devise illumination and feature dependent strategies for their compensation in the optical proximity
correction (OPC) for EUV masks. At last, an efficient approach using the Zernike analysis together with the
Waveguide decomposition technique is proposed to characterize the impact of mask properties for the future OPC process.
Isotropic treatment of EMF effects in advanced photomasks
Show abstract
Classical methods for modeling electromagnetic scattering from the topography of lithographic reticles must place
a high premium on fast computation, and toward that end they apply pre-stored perturbations (e.g. the so-called
boundary layers) to feature edges in order to approximate the impact of finite-thickness mask films. Though
approximate, these methods involve E&M calculations with vector fields, and so employ edge-field corrections
that are different for edges oriented parallel or perpendicular to the vector field. As a result these methods entail a
requirement for two separate aerial image simulations using orthogonal source polarizations in order to represent
unpolarized illumination. This imposes a minimum 2X runtime penalty relative to baseline thin-mask (TMA)
simulations, since the known method for combining the effect of both polarizations into one single set of imaging
TCCs applies only to thin-mask calculations. More severe performance penalties are common in so-called sparse
imaging methodologies when topographic effects are included, since the separated treatment of feature edges and
the internal area of the features can increase the number of memory lookups required.
In this paper an isotropic field perturbation approach is evaluated, in which an isotropic edge field correction,
common to all edge orientations, mimics the effect of the true parallel and perpendicular edge field perturbations
when the mask is illuminated with unpolarized light, as well as in certain cases of polarized illumination. The
isofield is not an ad hoc empirical correction but rather an accurate approximation in the limit of modest departures
from scalar TMA. More specifically, we show that the isofield model accounts for vector imaging effects with full
accuracy in the TMA terms, and in an approximate way in the electromagnetic edge-field terms that becomes
accurate when the polarization dependence of the TMA terms is small. We will show with comparison to more
rigorous electromagnetic models and simulations, as well as against wafer measurements that the accuracy loss
relative to classic polarized EMF correction approach is within a small percentage on mask blanks where the
electromagnetic edge field perturbation terms are small relative to the TMA term. Methodology to extend these
models into the subwavelength diffraction regime will be discussed.
EUV Mask Contamination and Cleaning
50nm particle removal from EUV mask blank using standard wet clean
Show abstract
Readiness of defect free mask supply is one of the critical challenges for the insertion of extreme ultra violet
lithography (EUVL) into high volume semiconductor manufacturing for 32 nm half pitch (HP) and beyond. According to
ITRS updated in 2008, the defect size which is needed to remove is 25 nm for 32 nm HP [1]. On the other hand, in the
presentation published in 2008, critical defect size for absorber defect on EUV mask was described around 24 nm for 32
nm HP line and space patterns, meaning that the particles having the equivalent size are necessary to be removed [2]. In
such a stringent defect requirement, cleaning process must play critical role to remove such tiny particulate defects.
However, EUV mask cleaning faces unique challenges related to the reflective mask structure, new material such as
ruthenium (Ru) capping layer and more frequent cleaning due to the lack of pellicle protection. Consequently, it must be
gentle enough not to damage fragile patterns and surfaces on EUV mask, particularly the very thin Ru capping layer. The
competing demand makes the EUV mask cleaning more challenging.
We have reported comprehensive evaluation of cleaning related issues using the blank inspection tool M1350 with
80 nm sensitivity [3, 4]. In this paper we extend our effort to much smaller defects using the new blank inspection tool
M7360 with 50 nm sensitivity.
EUV Mask Data Preparation and Inspection
Accurate models for EUV lithography
Show abstract
Accurate modeling of EUV Lithography is a mandatory step in driving the technology towards its foreseen insertion
point for 22-16nm node patterning. The models are needed to correct EUV designs for imaging effects, and to
understand and improve the CD fingerprint of the exposure tools. With a full-field EUV ADT from ASML now
available in the IMEC cleanroom, wafer data can be collected to calibrate accurate models and check if the existing
modeling infrastructure can be extended to EUV lithography. As a first topic, we have measured the CD on wafer of a
typical OPC dataset at different flare levels and modeled the evolution of wafer CD through flare, reticle CD, and pitch
using Brion's Tachyon OPC engine. The modeling first requires the generation of a flare map using long-range kernels
to model the EUV specific long-range flare. The accuracy of the flare map can be established independently from the CD
measurements, by using the traditional disappearing pad test for flare determination (Kirk test). The flare map is then
used as background intensity in the calibration of the traditional optical models with short-range kernels. For a structure
set of 600 features and over a flare range of 4-6%, an rms fit value of 0.9nm was obtained.
As a second aspect of the modeling, we have calibrated a full resist model to process window data. The full resist model
is then used in a combination with experimental measurements of reticle CD, slit intensity uniformity, focal plane
behavior, and EUV thick mask effects to model the evolution of wafer CD across the exposure field. The modeled
evolution of CD across the exposure field was found to be a good match to the experimentally seen evolution of CD
across the field, and confirms that the 4 factors mentioned above are main contributions to the CD uniformity across the
field. As such the modeling work enables a better understanding of the errors contributing to CD variation across the
field for EUV technology.
Investigation of buried EUV mask defect printability using actinic inspection and fast simulation
Show abstract
The fast simulator RADICAL and the Actinic Inspection Tool (AIT) are used in advance of availability of high
volume manufacturing quality exposure tools, resists, and masks to assess the expected defect printability levels in
production conditions. AIT images are analyzed to qualitatively demonstrate general trends in defect printability: defects
smaller than 0.5nm tall on the multilayer surface can cause an unacceptable critical dimension (CD) change, CD change
increases for taller defects, and defect printability varies asymmetrically through focus. RADICAL is used to derive
quantitative limits for defect size and demonstrate the effects of focus and illumination for 22nm and 16nm dense lines.
For 22nm dense lines at best focus a 0.8nm tall defect causes a 10% CD change. For 16nm lines a 0.4nm tall defect
causes a 10% CD change. The CD is shown to be more sensitive to buried defects out of focus, but less sensitive to
defects in focus if annular or dipole illumination is used.
Study of EUVL mask defect inspection using 199-nm inspection tool with super-resolution method
Show abstract
In this paper, we will report on our experimental results on the impact of inspection system optics on mask defect
detection sensitivity. We evaluated the capability of detecting defects on the EUVL masks by using a new inspection
tool (NPI6000EUVα) made by NuFlare Technology, Inc. (NFT) and Advanced Mask Inspection Technology, Inc.
(AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect inspection system using 199nm
wavelength inspection optics. The programmed defect mask with LR-TaBN absorber was used which had various sized
opaque and clear extension defects on hp-180nm, hp-128nm, and hp-108nm line and space patterns. According to the
analysis, to obtain optimum sensitivity for various types of defects, using both C- and P-polarized illumination
conditions were found to be effective. At present, sufficient defect-detection sensitivity is achieved for opaque and clear
extension defects in hp128nm (hp32nm at wafer). For hp108nm (hp27nm at wafer), using both C- and P- polarized
illumination is effective. However, further developments in defect-detection sensitivity are necessary.
DPL Implementation and RET Manufacturability
Single-mask double-patterning lithography
Show abstract
This paper proposes shift-trim double patterning lithography (ST-DPL), a cost-effective method for achieving 2× pitchrelaxation
with a single photomask (especially at polysilicon layer). The mask is re-used for the second exposure by
applying a translational mask-shift. Extra printed features are then removed using a non-critical trim exposure. The
viability of ST-DPL is demonstrated. The proposed method has many advantages with virtually no area overhead (< 0.3%
standard-cell area): (1) cuts mask-cost to nearly half that of standard-DPL, (2) reduces overlay errors between the two
patterns and can virtually eliminate it in some process implementations, (3) alleviates the bimodal problem in doublepatterning,
and (4) enhances throughput of first-rate scanners. We implement a small 45nm standard-cell library and small
benchmark designs with ST-DPL to illustrate its viability.
Resolving contact conflict for double patterning split
Show abstract
Double patterning (DP) is one of the main options to print devices with half pitch less than 45nm. The basis of DP is to
decompose a design into two masks. In this work we focus on the decomposition of the contact pattern layer. Contacts
with pitch less than a split pitch are assigned to opposite masks corresponding to different exposures. However, there
exist contact pattern configurations for which features can not be assigned to opposite masks. Such contacts are flagged
as color conflicts. With the help of design of manufacturing (DFM), the contact conflicts can be reduced through
redesign. However, even the state of the art DFM redesign solution will be limited by area constraints and will introduce
delays to the design flow. In this paper, we propose an optical method for contact conflicts treatment. We study the
impact of the split on imaging by comparing inverse lithography technology (ILT), optical proximity correction (OPC)
and source mask co-optimization (SMO) techniques. The ability of these methods to solve some split contacts conflicts
in double patterning are presented.
Parallel processing for pitch splitting decomposition
Show abstract
Decomposition of an input pattern in preparation for a double patterning process is an inherently global
problem in which the influence of a local decomposition decision can be felt across an entire pattern. In
spite of this, a large portion of the work can be massively distributed. Here, we discuss the advantages
of geometric distribution for polygon operations with limited range of influence. Further, we have found
that even the naturally global "coloring" step can, in large part, be handled in a geometrically local
manner. In some practical cases, up to 70% of the work can be distributed geometrically. We also
describe the methods for partitioning the problem into local pieces and present scaling data up to 100
CPUs. These techniques reduce DPT decomposition runtime by orders of magnitude.
Poster Session: Cleaning/Contamination/Haze
Back-glass cleaning: reducing repelliclization costs by focused action
Show abstract
With the optimization of sulfate-free cleaning the issue of haze under pellicle was almost eliminated. In consequence,
current reasons for mask repelliclization needs are moving from pattern issues to more gross problems on back glass.
Moreover, the longer life of photomasks allows a new problem to appear as growing defects on back glass, commonly
ascribed to environmental conditions at user's site. The commonality of these problems is being independent on mask
complexity and substrate. In order to avoid the criticalities of pellicle removal and cleaning treatment as well as the cost
of necessary inspection after new pellicle application, the best solution is cleaning only the backside of the mask,
provided that integrity of pellicle and pattern on front side are preserved
In this article we present the results obtained by the use of the Mask cleaner DE050019TM on several cases.
The efficiency of the treatment was assessed in terms if removal capability on different kinds of contaminations, either
from use or mask aging. Pattern inspections were conducted in order to assess ESD robustness. Ionic residues were
checked by IC aimed to compare with standard cleanings.
This methodology demonstrated to be capable of maintaining a Particle Removal Efficiency>97% on all kinds of
contaminations, without any damage to pellicle or harm to patterns, still maintaining residual ions at the same level as
after cleaning by standard tools.
Poster Session: EUV Mask
Feasibility study of the approach to flare, shadowing, optical and process corrections for EUVL OPC
Show abstract
The switch from 193i to EUV Photolithography will bring some fundamental changes in exposure. The flare levels of an
EUV machine are significantly higher compared with standard 193i machines. Moreover shadow effects on the reticle
are not equivalent to 193i. It is inevitable that these fundamentals require modifications in the Optical Proximity
Correction (OPC) flow.
In this paper in collaboration with ASML BRION the critical enabling steps of the Mask Data Preparation (MDP) for
EUVL, Flare, Shadowing and Optical and Process Corrections (OPC), are investigated.
We measured the needs of the EUV MDP flow against the capabilities of a state-of-the art OPC flow built for 193i.
Adaptations are being made to implement features which are currently not available in a 193i based flow.
We present a feasibility study of the Model Based approach to the EUV OPC on a wide selection of features. Also we
demonstrate simulations and verification of the EUV modeling capabilities of the TachyonTM with various levels and
ranges of flare and prove the applicability of the reviewed approach to the process development for the 27nm EUV
node..
We also evaluated the accuracy of the EUV OPC modeling and expected OPC corrections on the reviewed selection of
clips as a substantial part of the overall CDU budget.
Finally an overall EUV OPC flow as a manufacturable solution based on the Tachyon's predictions and ASML's
knowledge of Photolithography was discussed.
Novel EUV mask inspection tool with 199-nm laser source and high-resolution optics
Show abstract
A novel EUV mask inspection tool with 199nm laser source and super-resolution technique has been developed.
This tool is based on NPI-5000PLUS, which is a photo-mask inspection tool for hp2X nm node and beyond. In order to
implement EUV mask inspection with only a short time for mask set-up, reflected illumination type alignment optics to
guide alignment mark and adjust mask coordinate with visible illumination light are equipped. Moreover, to inspect EUV
masks for hp2X nm and beyond, the image detection optics with the novel polarized illumination technique is
incorporated in this tool. Image contrast enhancement was confirmed by experiments and simulations.
Poster Session: Inspection and Repair
Aerial plane inspection for advanced photomask defect detection
Show abstract
A new methodology - Aerial Plane Inspection (API) - has been developed to inspect advanced photomasks
used for the 45 nm node and beyond. Utilizing images from a high resolution mask inspection system, a
mask image is recovered by combining the transmitted and reflected images. A software transformation is
then performed to replicate the aerial image planes produced in a photolithography exposure system. These
aerial images are used to compare adjacent die in a Die-Die inspection mode in order to find critical defects
on the photomask. The mask recovery process and modeling of the aerial plane image allows flexibility to
simulate a wide range of lithographic exposure systems, including immersion lithography. Any source
shape, Sigma, and numerical aperture (NA) can be used at all common lithographic wavelengths.
Sensitivity of the inspection can be fully adjusted to match photomask specifications for CD control, lineend
shortening, OPC features, and for small and large defective areas. An additional adaptive sensitivity
option can be utilized to automatically adjust sensitivity as a function of MEEF.
Using the Aerial Plane Inspection to compare pattern images has the benefit of filtering out non-printing
defects, while detecting very small printing defects. In addition, defects that are not printing at ideal
exposure condition, but may be reducing the lithographic process window, can also be detected.
Performing defect detection at the aerial image plane is more tolerant to small Optical Proximity Correction
(OPC) sub-resolution assist features (SRAFs) that are difficult to inspect at the reticle image plane.
AIMS mask qualification for 32nm node
Show abstract
Moving forward to 32nm node and below optical lithography using 193nm is faced with complex requirements to be
solved. Mask makers are forced to address both Double Patterning Techniques and Computational Lithography
approaches such as Source Mask Optimizations and Inverse Lithography. Additionally, lithography at low k1 values
increases the challenges for mask repair as well as for repair verification and review by AIMSTM. Higher CD
repeatability, more flexibility in the illumination settings as well as significantly improved image performance must be
added when developing the next generation mask qualification equipment. This paper reports latest measurement results
verifying the appropriateness of the latest member of AIMSTM measurement tools - the AIMSTM 32-193i.
We analyze CD repeatability measurements on lines and spaces pattern. The influence of the improved optical
performance and newly introduced interferometer stage will be verified. This paper highlights both the new Double
Patterning functionality emulating double patterning processes and the influence of its critical parameters such as overlay
errors and resist impact. Beneficial advanced illumination schemes emulating scanner illumination document the
AIMSTM 32-193i to meet mask maker community's requirements for the 32nm node.
Inspection of complex OPC patterns for 4x node and beyond
Show abstract
OPC (Optical Proximity Correction) technique is inevitable and getting more complex to resolve finer features on
wafer with existing optical lithography technology. Some SRAFs generated with special model-based OPC engines
are so sophisticated that we can hardly imagine final patterns on wafer simply by seeing patterns on reticle. These
model-based OPCs consist of many kinds of assist features since they are designed differently according to various
target features on wafer and lithographic conditions. Not only small main features but also even smaller and
aggressive SRAFs (Sub Resolution Assist Features) may cause too many false counts and/or nuisance defects during the
reticle inspection, which makes inspection TAT (Turn Around Time) longer and inspection process more laborconsuming.
To improve the inspectability of this sort of complex OPC patterns, appropriate MRC (Mask Rule Check)
rules should be considered.[1][2] As far as the inspection methods are concerned, several approaches have been
developed, such as TLD (Thin Line Desense), LPI (Lithographic Plane Inspection)[3][4], and Aerial Image Based
Inspection[5][6] to relax MRC rules. In this paper, we've compared and analyzed the functionalities of enhanced
inspection methods for complex OPC features of 4x nodes and beyond.
Theoretical foundations of die-to-model inspection
Show abstract
Advanced immersion lithography is enabled by a combination of optimized off-axis illumination,
highly complex design patterns, and photo-mask technologies with several transmission and phase
levels. The pattern on the mask, for 45nm half pitch and below, shows little resemblance to the target
printed pattern, which is revealed only when illuminated with the correct aerial exposure conditions.
The main pattern is modified or surrounded by OPC and SRAF features which are comparatively
much smaller. The small size and irregularity of these features present a challenge to mask inspection
process, both due to their size and the mask manufacturing process sensitivity. While most masks are
inspected using a die-to-die scheme, single-die masks use an alternative detection scheme based on
comparing the mask image to mask design data. In high-resolution inspection tools, the resolution
must be sufficient to resolve the sub-resolution features, and compare them to the mask design. In
aerial inspection tools, which have optics that mimic the illumination and collection exposure
conditions over the mask as in a scanner, the inspection image depicts the mask at the scanner
resolution. As a consequence, in the aerial image, as in the scanner, sub-resolution features are not
resolved and do not develop. Therefore, a conventional comparison to a database is not possible.
Here, we present a single die detection scheme that takes a new approach - an optical model is
calculated from the mask design information, based on an optical modeling of the inspection optics
response. The result is an aerial model image, which predicts the aerial image created by the
inspection tool, and may be directly compared to the real image captured by the inspection machine.
We describe herein the theoretical foundation of the Die-to-Model scheme, and the practical
computational implementation. As a consequence of the high quality modeling, the detection scheme
employed for single die inspection performance is identical to the die-to-die scheme,. This new die to
model scheme, implemented on the Aera2 aerial mask inspection tool is successfully implemented in
4x memory and 32nm generation logic mask production at leading mask shops.
New analysis tools and processes for mask repair verification and defect disposition based on AIMS images
Show abstract
Using AIMSTM to qualify repairs of defects on photomasks is an industry standard. AIMSTM images match the
lithographic imaging performance without the need for wafer prints. Utilization of this capability by photomask
manufacturers has risen due to the increased complexity of layouts incorporating RET and phase shift technologies.
Tighter specifications by end-users have pushed AIMSTM analysis to now include CD performance results in addition to
the traditional intensity performance results.
Discussed is a new Repair Verification system for automated analysis of AIMSTM images. Newly designed user
interfaces and algorithms guide users through predefined analysis routines as to minimize errors. There are two main
routines discussed, one allowing multiple reference sites along with a test/defect site within a single image of repeating
features. The second routine compares a test/defect measurement image with a reference measurement image. Three
evaluation methods possible with the compared images are discussed in the context of providing thorough analysis
capability.
This paper highlights new functionality for AIMSTM analysis. Using structured analysis processes and innovative
analysis tools leads to a highly efficient and more reliable result reporting of repair verification analysis.
Poster Session: Mask Data Preparation
Reducing the shot counts of mask writing with OPC by extracting repeating patterns
Show abstract
In May 2006, the Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) at the
Association of Super-Advanced Electronics Technologies (ASET) launched 4-year program for reducing mask
manufacturing cost and TAT by concurrent optimization of MDP, mask writing, and mask inspection [1]. One area of
the project focuses on clever utilization of repeating patterns where the repeating patterns are extracted from the mask
data after the layout has been run through its OPC process. The data thus obtained is then used as Character Projection
(CP) for reducing the shot counts during the subsequent electron beam writing step. We have developed a software that
can extract repeated pattern from mask data. This software has been verified by using actual device production data
obtained from the member companies of MaskD2I. In this paper, we will address the effect of reducing the shot counts
on TAT in mask writing. In order to evaluate the usefulness of extraction repeating patterns, we will also show the result
of extraction common repeating patterns from multiple masks and the investigation result of EB proximity effect on CP
drawing.
Improving the quality of fractured mask data through in-place optimization of the fracturing solution
Show abstract
In this paper, we present the idea of (in-place) substitution of the fracture solution for some of the badly or nonuniformly
fractured instances of polygons, by a better fracture solution. Polygons could be categorized as badly or nonuniformly
fractured based on the values of various quality metrics - such as number of generated trapezoids, number of
slivers, uniformity in fracturing etc. The inferior quality of fracture solution may be due to sub-optimal fracturing. This
In-Place Optimization (IPO) strategy proposes a solution wherein rather than carrying out a complete re-fracturing of the
mask data, the QoR of fractured data can be improved "in-place" through applying patches to the hotspots of badly or
non-uniformly fractured polygons.
The proposed IPO scheme is flexible enough to classify the QoR of a fractured solution of a polygon using externally
defined parameters or formulae. In a way, the users responsible for mask MDP can categorize the quality of a fractured
solution as good or bad through defining some criteria externally to the tool. The IPO scheme allows internal
substitution, where a better fracture solution for any given polygon is found within the same fracture data at some other
instance of the polygon, or external substitution where a better fracturing solution is generated using a third party
fracturing tool or by using the same fracturing tool with different inputs. Since this IPO technique modifies the fractured
mask data, it is mandatory to have a built-in validation scheme which is discussed in detail.
Economic assessment of lithography strategies for the 22nm technology node
Show abstract
The unavailability of extreme ultra violet lithography (EUVL) for mass production of the 22nm technology
node has created a significant void for mainstream lithography solutions. To fill this void, alternate
lithography solutions that were earlier deemed to be technically and economically infeasible, such as
double patterning technologies (DPT), source mask optimization (SMO), massively parallel direct write ebeam
(MEBM) and Interference assisted lithography (Intf), are being proposed, developed and adopted to
ensure the timely deployment of the 22nm technology node. While several studies have been undertaken to
estimate the lithography process costs for volume production with the aforementioned technologies, these
studies have provided only a partial analysis since they have not taken into account the impact on design
density and product yield.
In this paper we use the cost-per-good-die metric in order to capture process costs as well as yield and
design density. We have developed a framework that estimates the lithography cost-per-good-die for
SRAM arrays and have applied it to evaluate the economical feasibility of the various lithography strategies
under consideration for the 22nm technology node. Specifically, we compare the cost-per-good-die for
different 32MB SRAM arrays, each optimized for a different lithography solution. Our analysis shows that
the selection of the best lithography strategy is both layer and volume specific. The use of DPT solutions is
recommended for Active and Contact layers. The use of Intf is recommended for layers such as Poly,
Metals and Vias in the case of low volume products. For medium to high volume products the use of SMO
is recommended for Poly, Metals and Vias. This paper provides quantifies of economic benefit of the
proposed lithography strategy.
Poster Session: Mask Process Control/Equipment
Improved particle control by adopting advanced ceramic materials in dry etcher for defect reduction
Show abstract
As integration of circuits increases, required feature size becomes smaller and smaller. Defect control becomes tighter
due to decrease in defect size that affects the images printed on the wafer and increase in possibility to be killer defect
like 2-face bridge defect. Therefore, particle sources from all processes should be controlled extremely.
Especially for dry etching process, Alumina ceramic has been widely used for plasma resistance material such as
electrode covering plate and insulator. However, they can be etched under 'F' series plasma condition as well, even in
small amounts. It has been reported that non-volatile by-products from etch ceramic can be particle sources to be killer
defect. Therefore, selection of ceramic materials must be important for particle control in dry etch process.
This paper pertains to testing etch resistance differences in Alumina (Al2O3) and Yttria (Y2O3) ceramic materials
depending on various density and surface roughness. Ceramic surface microstructures change after plasma treatment was
observed with scanning electron microscope (SEM) and ceramic erosion rate after plasma treatment was measured with
surface profiler.
Poster Session: Mask Substrate/Blank/Films
The study of the birefringence as MoSi based materials for immersion lithography
Show abstract
According to the semiconductor technology roadmap, immersion lithography is emerging for 32 nm and below
technology. Therefore, immersion lithography requires new process parameters such as high refractive index fluid,
stepper, resist, and birefringence. A lot of research for those items has been done, and the components and materials of
thin film used blankmask have become more important. The birefringence of thin film is an especially essential issue
for the development of advanced technology. Accordingly, we studied birefringence with thin film characteristics.
Having a transmittance of 6% at 193 nm, six different kinds of molybdenum silicon-based thin films were prepared
by DC magnetron sputter. The thin films were deposited on 6.3 mm thick quartz using O2, N2, CH4 and CO2 reactive
gasses. We studied the effects of thin film composition, substrate, heat treatment, and dopant in this paper. First, we
measured the birefringence as thin film composition and substrate by the 250AT Exicor system. We studied the effect
of reactive gas flow rate and types on birefringence, and we selected thin film material adaptable to reduce the
birefringence from the above results. Next, we doped the transition metal to the selected materials to decrease the
birefringence. Then we did heat treatment to the thin films by using rapid thermal process (RTP) to further reduce the
birefringence. According to the results, we confirmed that the birefringence was influenced by thin film composition
and it was controlled by the tuning of thin film composition, dopants, and heat treatment. Next, we analyzed the
intensity of crystal state and density of thin films by using x-ray diffractometer (XRD) and x-ray refractometer (XRR).
Finally, we analyzed the thin film characteristics by using various analytic tools.
Poster Session: Metrology
A study of contour image comparison measurement for photomask patterns of 32 nm and beyond
Show abstract
In order to analyze small reticle defects quantitatively, we have developed a function to measure differences in two
patterns using contour data extracted from SEM images. This function employs sub-pixel contour data extracted with high
accuracy to quantify a slight difference by ΔCD and ΔArea. We assessed the measurement uncertainty of the function with a
test mask and compared the sizes of programmed defects by each of conventional and proposed methods. We have also
investigated a correlation between measured minute defects in high MEEF (Mask Error Enhancement Factor) regions and
aerial images obtained by AIMS (Aerial Image Measurement System) tool. In this paper, we will explain the Contour
Comparison Measurement function jointly developed by Toppan and Advantest and will show its effectiveness for photomask
defect analyses.
Noble approach for mask-wafer measurement by design-based metrology integration system
Show abstract
OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate
OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the
manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask
technique need be considered in addition to lithography technique.
Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is
very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to
be reported that there are cases that size cannot be matched between a mask pattern and the corresponding
printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask
and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the
device size is so small that low k1 lithography had been developed and widely used in a production.
Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using
contour that was extracted from mask SEM image in addition to mask model.
This paper describes a newly developed integration system in order to solve issues above, and the applications.
This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using
DesignGauge; OPC evaluation system by Hitachi High-Technologies.
It was investigated that a measurement accuracy improvement by executing a mask-wafer same point
measurement with same measurement algorithm utilizing the new system. At first, we measured patterns
described on a mask and verified the validity based on a measurement value, picture, measurement parameter
and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same
patterns that were exposed using the mask. In addition, average CD measurement was tried in order to
improve the correlation. Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the
result and the design data was used in a litho simulation. This realizes verification including mask error.
It is thought that it is beneficial for both mask maker and device maker to use this system.
Poster Session: OPC
Adaptive OPC approach based on image simulation
Show abstract
With the design rule shrinks rapidly, full chip robust Optical Proximity Correction (OPC) will definitely need longer
time due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more
difficult. For, the critical dimension of the design features is deeply sub exposure wavelength, and there is only
limited room for the OPC correction. Usually very complicated fragment commands need to be developed to handle
the shrinking designs, which can be infinitely complicated. So when you finished debug a sophisticated fragment
scripts, you still cannot promise that the script is universal for all kinds of design. And when you find some hot spot
after you apply OPC correction for certain design, the only thing you can do is to modify your fragmentation script
and try to re-apply OPC on this design. But considering the increasing time that is needed for applying full chip OPC
nowadays, re-apply OPC will definitely prolong the tape-out time. We here demonstrate an approach of adaptive
OPC, with which automatic fragmentation adjustment can be realized. And this will be helpful to reduce the difficulty
for OPC recipe development.
Introducing process variability score for process window OPC optimization
Show abstract
As the IC Industry moves towards 32nm technology node and below, it becomes important to study the impact of
process window variations on yield. PVBands is a technique to express process parameter variations such as dose, focus,
mask size, etc. However, PVBands width and area ratio alone are insufficient as a quantitative measure for judging the
PVBand performance, as it does not take into consideration how far away the contours are from the target.
In this paper, a novel mathematical formulation is developed to better judge the PVBands performance. It expresses the
PVBand width and symmetry with respect to the target through a single score. This score can be used in OPC (Optical
Proximity Correction) iterations instead of working with the nominal EPE (Edge Placement Error). Not only does this
approach provide a better measure of the PVBands performance through the value of the score, but it also presents a
straightforward method for PWOPC optimization by using the PV Score directly in the iterations.
Patterning of 90nm node flash contact hole with assist feature using KrF
Show abstract
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm
technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI)
such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus
(DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an
important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image
contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated
features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a
contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are
derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of
assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly
impossible task.
To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The
impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also
shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a
methodology for optimizing SRAF rules using inverse lithography technology is described.
On comparing conventional and electrically driven OPC techniques
Show abstract
This paper compares the range of accepted layouts produced by conventional Shape Driven Proximity Correction (SDOPC)
and Electrically Driven Optical Proximity Correction (EDOPC). For SDOPC, correction is made until a target geometry
matches a layout. In EDOPC, current matching is the primary objective.1-6 Using electrical objectives results in a smaller
fragmentation requirement for an equivalent current accuracy as SDOPC. Number of candidate OPC solutions accepted
by EDOPC is orders of magnitude higher than SDOPC leading to potentially much faster convergence. Moreover, due to
additional flexibility in EDOPC, it is able to correct several layouts which are not correctable by SDOPC with the same
fragmentation.
OPC model space approach to in-line process monitoring structures
Show abstract
With shrinking technology nodes and increasing geometries criticity, it has become more and more difficult to
conceive fast and accurate in-line check to insure process quality for each lithography level. Time and costs limit
metrology options.
A commonly accepted solution consists in some CD measurement on high contrast structure for each critical
level. However, the RET complexity of current layouts makes this solution no longer fully reliable and allows
non-conform materials to pass through the check. The idea behind this article (patent pending) is to add a second
verification by creating a set of small structures layouted to cover specific coordinates in the model parameters
space. Extrapolated model parameters allow to layout geometries encircling the OPC space region occupied by
the production device. Those structures shall bridge or pinch for litho or process deviations before any detectable
impact on the most sensitive shapes present in the product. Total size of few square microns is required to stay
within a single SEM picture. The use of image processing based on pattern recognition on SEM pictures to
assess their sensitivity to process variations permits a fast analysis. As a matter of fact, this approach will allow
getting reliability by watching the whole model space and economic compatibility as the procedure is fast and
cost-effective.
Practical application of OPC in electrical circuits
Show abstract
Today's Optical Proximity Correction (OPC) is becoming increasingly complex and necessitates using smaller and
smaller grid sizes to produce the fine patterns required. These small grids lead to very high overhead in data handling, as
well as for the tools that will write and inspect the mask; which together make masks extremely expensive. For two
dimensional structures such as corners, we use complex structures incorporating either additive or subtractive OPC
features to produce the desired shape. It is unclear though, how precisely the final structures must match the original
design to perform their intended electrical functions. In this work we have created a number of corner type electrical test
structures and applied different degrees of OPC to both the outer and inner corners of the structures. These features were
then printed on doped polysilicon wafers, and the wafers were etched and electrically tested. The electrical effect of OPC
on the outer corner was found to be minimal, whereas the inner corner shape had a significant effect upon the electrical
resistance of the circuit feature. The data suggests that OPC on the outside corner has little impact upon a simple circuit's
performance, but care should be taken with OPC on the inner corners, particularly with regard to the size of the OPC
serifs used.
Poster Session: Pattern Generation/Equipment
3D Si aperture-plates combined with programmable blanking-plates for multi-beam mask writing
Show abstract
Multi-beam lithography is considered a promising fabrication technology for future node mask making. Due to rising
design complexity and therefore increasing pattern writing times the multi-beam approach has distinguished throughput
advantages compared to state of the art variable shaped beam pattern generators.
A key component of a projection multi-beam writing tool is the programmable blanking-plate for generating the desired
pattern geometry on the mask substrate.
In our case a highly parallel charged particle beam illuminates a Si aperture-plate which shapes and generates many
thousand individual spot beams. These beams pass through a blanking-plate with integrated CMOS electronics for demultiplexing
the writing data. The blanking-plate is equipped with blanking and ground electrodes placed around the
apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x
reduction optics and the exposure of the mask substrate is done in stripes by a continuous moving stage [1,2].
Cross talk between adjacent beams in the blanking-plate has to be avoided to ensure adequate pattern fidelity and line
edge roughness on the mask substrate. One solution is the insertion of a 3D Si aperture-plate in proximity to the
blanking- plate shielding the blanking electrodes from each other during operation.
We developed and characterized a new process flow for the fabrication of these 3D Si aperture-plates for the case of 43
thousand beams in parallel and will present and discuss the cross talk results for blanking-plates combined with standard
2D and new 3D Si aperture-plates.
Poster Session: Simulation and Modeling
Revisit to aberration: a simulation study of lens aberration induced overlay misalignment and its experimental validation
Show abstract
Overlay (O/L) misalignment (M/A) is induced from numerous sources including metrology error and stage control error,
and aberration in projection optics. However, as design rule become smaller, aberration induced O/L M/A is evaluated to
take considerable portion in the overlay budget. This paper focuses on O/L M/A issues from projection optics. We
presents a simulation analysis of M/A between contact hole (C/H) pattern and line & space (L/S) pattern at 65nm node
based on the aberration data from actual lithography tool to single out the main source of O/L M/A.. The study shows
that the aberration in projection optics can induce considerable M/A and the conventional overlay keys do not represent
this M/A properly. Among the Zernike fringe polynomials, the third-order behavior (D3) in Z2 (tilt) is found to be the
critical source of misalignment. This portion of the aberration is resulted from the lens heating (LH) and can be corrected.
However, this correction method needs improvements because its controllability over LH is not enough for the complete
correction of LH induced M/A. Besides D3, Z10 (3-Foil) are found to be the major sources for pattern shift in C/H
patterns, and Z7 and Z14 (Coma x) are found for L/S patterns.
Wafer topography proximity effect modeling and correction for implant layer patterning
Show abstract
Photolithography on reflective surfaces with topography can cause overexposure in some areas in the photoresist,
resulting in undesired critical dimension (CD) variations in the printed patterns. Using bottom anti-reflective coatings
(BARCs) will reduce the severity of the problem. However it is not a preferred solution in some situations due to added
process complexity, such as the case of implant blocking layer patterning. This topography proximity effect (TPE) has
been ignored in the mask synthesis flow for the 45nm and larger nodes due to its relatively small impact to the CDs.
When the device critical length reaches 32nm and lower, the variations on the implant layer caused by underlying
topography becomes more and more an issue and need to be addressed properly. In order to do that, simulation with nonplanar
stack is required. The available tools for photolithography simulation with wafer topography, such as Synopsys'
Sentaurus Lithography (S-Litho), usually adopt a rigorous approach based on the solution of the Maxwell equations and
unsuitable for full chip optical proximity correction (OPC) due to their prohibitively long runtimes. A fast method for
TPE modeling is needed to make full chip TPE correction feasible.
In this paper, we propose a computationally fast approximate method that captures TPE well. It enables fast model
calibration and full chip implant layer mask correction, and fits in the current OPC flows easily. We validate the
method's effectiveness by comparing its simulation results with those produced by Sentaurus Lithography. We also
show how it helps implant layer mask synthesis that takes TPE from previous layers into consideration.
Fast and accurate computation of partially coherent imaging by stacked pupil shift operator
Show abstract
In this paper, the stacked pupil shift operator approach to partially coherent imaging as first introduced by
Yamazoe1 has been further pursued and investigated with a focus on its practical performances in lithographic
simulations.. The stacked pupil shift operator P is a singular matrix obtained by stacking pupil functions that
are shifted according to the illumination condition. The transmission cross coefficient (TCC) matrix can then
be constructed in an elegant fashion as TCC = PP. The new development presented in this paper utilizes
a matrix multiplication technique to speed up the computation of TCC matrix by tenfolds on average. This
enables fast and accurate generation of TCC kernels for complicated illumination source shapes where a large
number of source points are required to obtain good accuracy. The eigenvalue decomposition is applied to the
TCC matrix instead of the stacked pupil shift operator P so that mask and resist proximity effects can easily be
included in the effective TCC kernels.
Extensions of boundary layer modeling of photomask topography effects to fast-CAD using pattern matching
Show abstract
In lithography for the 45nm node and beyond, phase errors introduced through electromagnetic field (EMF)
effects at photomask openings are significant sources of error in calculating on-wafer images. These edge effects
create distortion in both real and imaginary field transmission, which leads to a tilt in the process window, and
must be addressed in mask design to avoid loss of process latitude. This study presents a new formulation for
pattern matching, which allows EMF effects to be included via boundary layer modeling to facilitate extremely
fast assessment of EMF impact on imaging. Boundary layers are first used to model these edge effects, by
adding additional transmission features to a layout to represent the error transmissions caused by edges. Pattern
matching is then used to determine susceptibly to various pre-existing perturbations, in the presence of defocus.
This process can be extremely fast and hotspot detection can be run on an entire chip in hours, compared to
days for aerial imaging. Correlation between pattern matching and full aerial imaging can be as high as 0.97
for coherent imaging, and ≈ 0.75 for off-axis dipole illumination. This pattern matching framework is extremely
flexible and can be used for fast assessment of any series of effects which can be described as a path difference
in the pupil or as a transmission on the mask.
Calibration of e-beam and etch models using SEM images
Show abstract
Mask Process Compensation (MPC) corrects proximity effects arising from e-beam lithography and plasma etch
processes that are used in the photomask manufacturing. Accurate compensation of the mask process requires accurate,
predictive models of the manufacturing processes. Accuracy of the model in turn requires accurate calibration of the
model. We present a calibration method that uses either SEM images of 2-dimensional patterns, or a combination of
SEM images and 1D CD-SEM measurements. We describe how SEM images are processed to extract the contours, and
how metrology and process variability and SEM alignment errors are handled. Extracted develop inspection (DI) and
final inspection (FI) contours are used to calibrate e-beam and etch models. Advantages of the integrated 2D+1D model
calibration are discussed in the context of contact and metal layers.
Predictive modeling for EBPC in EBDW
Show abstract
We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing
processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual)
measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results.
We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with
experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools.
As an example, we apply and compare dose correction and geometric correction for low and high electron energies on
1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the
optical case, but enhanced for the particularities of e-beam technology.
The results are used to discuss PEC strategies, with respect to short and long range effects.
Effective methodology to make DFM guide line
Show abstract
Design For Manufacturing (DFM) has become an important focusing part in the semiconductor
industry as the feature size on the chip goes down below the 0.13um technology. Lots of DFM related ideas
have been come up, tried, and adopted for wider process window and higher device performance. As the
minimum features are getting shrunk, the design rules also become more complicated, but still not good
enough to describe the certain pattern that imposes narrow process window or even failure of device. Thus,
these process hot spot patterns become to identify, correct, or remove at the design step. One of the efforts is
to support a DFM guide line to the designer or add to conventional DRC rules. However it is very difficult to
make DFM guideline because we detect the hot spot pattern and confirm if these patterns is real hot spot or
not.
In this study, we developed effective methodology how to make DFM guide line. Firstly we use the s
oftware, called nanoscope to detect hot spots on post OPC layouts and then make this detected hot spot patter
n to test patterns that it can check electrical performance and then we compared with electrical performance a
ccording to split condition. It is confirmed this method is very effective to make DFM guide line below the 0.
13um technology.
pRSM: models for model-based litho-hotspot repairs
Show abstract
Computing repair hints for litho hotspots is made more effective with a model of how Process Window contour bands
changes as a function of design layout changes. We have developed a modeling methodology called pRSM (Partition
Response Surface Model). In our approach, we create a family of models along with error bound estimate models. We
first classify design layout configurations into a small number of partition categories and then build a RSM model and
error bound model for each partition category. In this paper we describe our pRSM methodology and present results
illustrating the advantages of our methodology over that of traditional RSM approaches.
Effect of SRAF placement on process window for technology nodes that uses variable etch bias
Show abstract
As technology advances to 45 nm node and below, the induced effects of etch process have an increasing contribution to
the device critical dimension error budget. Traditionally, original design target shapes are drawn based on the etch target.
During mask correction, etch modeling is essential to predict the new resist target that will print on the wafer. This step
is known as "Model Based Retargeting" (MBR). During the initial phase of process characterization, the sub-resolution
assist features (SRAF) are optimized whether based on the original design target shapes or based on a biased version of
the design target (resist target). The goal of the work is to study the different possibilities of SRAF placement to
maximize the accuracy and process window immunity of the final resist contour image. We will, statistically, analyze
and compare process window simulation results due to various SRAFs placements by changing the reference layer used
during placement.
FPGA as the programmable tool for yield improvement
Show abstract
FPGA programmability is utilized to profile the intra-field process variation through mapping of Tilo
propagation delay within a reticle field. ASML DoseMapper patented technology is used to optimize poly
photo exposure based on the FPGA intra-field process variation profile. As a result, significant yield and
performance improvement is achieved.
Model-based hints for litho-hotspots repair
Show abstract
A litho hotspot repair hints requires the specifications of how layout edges should be modified. Identifying how layout
edges not directly touching the hotspot region is challenging to encode in a rule set. We propose an approach using
models called Partition Response Surface Models (pRSM) to estimate the contours changes due to design layout
modifications. In this paper we present details of litho hotspot repair hint engine which uses the pRSM models to
compute the shape changes amount to resolve a litho hotspot and which can accept constraints from both design
considerations or design rule considerations.
What is a good empirical model?
Show abstract
An accurately predictive process model is of utmost importance to the traditional Optical Proximity Correction (OPC),
the leading-edge Inverse Lithography Technology (ILT), or other simulation software for IC manufacturing. There are
many parameters and methods in constructing and calibrating a model. But it is difficult to obtain a good empirical
model, partly because the assessment of the final result is lacking in terms of quantitative and objective metrics. We set
out to define certain practical guidelines, e.g. Model Effectiveness Standard Index (MESI), for analyzing parameter
uncertainty and estimating simulation uncertainty of an empirical model, so that we know what to choose among many
similar candidates. The discussion is framed in the estimation theory of statistics.
Additional Papers
Mask inspection placement maps for improving overlay
Show abstract
With each successive technology node the overlay specifications of the immersion lithography scanner have become
increasingly more stringent. One of the challenges is high order distortions introduced by the mask. These distortions may
contribute significantly to the product overlay budget raising it above the specification requirements and are not easy to
correct.
The higher order distortions, originating from pellicle and mask process imperfections, have been shown to result in errors
in the range of several nanometers to the overall overlay budget [1],[2]. Correction markers and the actual product features
cannot occupy the same space on the mask. As a result they might be exposed to differing local distortions which could
result in non-optimal systematic distortion corrections [3]. Therefore high precision placement measurements of features
across the mask are required for placement control and correction.
The Applied Materials Aera2TM aerial imaging mask inspection system is capable of generating high precision global and
local feature placement maps with a high measurement density. These maps can be used to monitor feature placement.
Furthermore, the maps can be used in a feed forward APC system such as ASML's GridMapper IntrafieldTM[4]. This feed
forward system helps to reduce the overall overlay error of feature processes and to meet the stringent overlay budget
requirements.
In this paper we present for the first time (?) mask registration results obtained with the Aera2 and show that this tool is able
to meet the 1 [nm], 3δ ITRS requirement [5] for the 22nm node.
Key words: Inspection, Mask, Reticle, Placement, Registration, Overlay,