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Design for Manufacturability through Design-Process Integration II
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Volume Details

Volume Number: 6925
Date Published: 9 April 2008

Table of Contents
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Front Matter: Volume 6925
Author(s): Proceedings of SPIE
DfM, the teenage years
Author(s): Lars Liebmann
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Intel design for manufacturing and evolution of design rules
Author(s): Clair Webb
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Automatic hotspot classification using pattern-based clustering
Author(s): Ning Ma; Justin Ghan; Sandipan Mishra; Costas Spanos; Kameshwar Poolla; Norma Rodriguez; Luigi Capodieci
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Effective learning and feedback to designers through design and wafer inspection integration
Author(s): Crockett Huang; Hermes Liu; S. F. Tzou; Allen Park; Chris Young; Ellis Chang
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Rigorous CMP and electroplating simulations for DFM applications
Author(s): Yuri Granik; Norbert Strecker
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Global and local factors of on-chip variation of gate length
Author(s): Morimi Osawa; Koji Hosono; Satoru Asai
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Layout verification in the era of process uncertainty: target process variability bands vs actual process variability bands
Author(s): J. Andres Torres
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Context analysis and validation of lithography induced systematic variations in 65nm designs
Author(s): Arjun Rajagopal; Anand Rajaram; Raguram Damodaran; Frank Cano; Srinivas Swaminathan; Clive Bittlestone; Mark Terry; Mark Mason; Yajun Ran; Haizhou Chen; Robert Ritchie; Bala Kasthuri; Jac Condella; Philippe Hurat; Nishath Verghese
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Low-k1 logic design using gridded design rules
Author(s): Michael C. Smayling; Hua-yu Liu; Lynn Cai
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DfM lessons learned from altPSM design
Author(s): Lars Liebmann; Zak Baum; Ioana Graur; Don Samuels
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Yield aware design of gate layer for 45 nm CMOS-ASIC using a high-NA dry KrF systems
Author(s): Ewoud Vreugdenhil; Harold Benten; Liesbeth Reijnen; Gerald Dicker; Jan-Willem Gemmink; Frank Bornebroek
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Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection
Author(s): Steve Prins; James Blatchford; Simon Chang; Lewis Flanagin; Scott Jessen; Sean O'Brien; Guangming Xiao; Timothy Lin; Thuc Dam; Bob Gleason
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Layout optimization based on a generalized process variability model
Author(s): Qian Ying Tang; Costas J. Spanos
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Manufacturing for design: a novel interconnect optimization method
Author(s): Hongbo Zhang; Liang Deng; Kai-Yuan Chao; Martin D. F. Wong
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Shaping gate channels for improved devices
Author(s): Puneet Gupta; Andrew B. Kahng; Youngmin Kim; Saumil Shah; Dennis Sylvester
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A routing clean-up methodology for improvement of defect and lithography related yield
Author(s): Jacques Herry; Reinhard März; Hanno Melzner; Kai Peter; Olivier Rizzo
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Analysis of systematic variation and impact on circuit performance
Author(s): Shayak Banerjee; Praveen Elakkumanan; Dureseti Chidambarrao; James Culp; Michael Orshansky
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VARAN: variability analysis for memory cell robustness
Author(s): Gideon Reisfeld; Dmitry Messerman; Nir Bone; Adi Lazar
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Implementation of silicon-validated variability analysis and optimization for standard cell libraries
Author(s): Raphael Bingert; Alain Aurand; Jean-Claude Marin; Eric Balossier; Thierry Devoivre; Yorick Trouiller; Florent Vautrin; Nishath Verghese; Richard Rouse; Michel Cote; Philippe Hurat
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Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours
Author(s): Toshiaki Yanagihara; Takeshi Hamamoto; Koya Sato; Atsushi Okamura; Toshiyuki Matsunaga; Naohiro Kobayashi; Tatsuya Maekawa; Nishath Verghese; Jac Condella; Philippe Hurat
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Hypersensitive parameter-identifying ring oscillators for lithography process monitoring
Author(s): Lynn Tao-Ning Wang; Wojtek J. Poppe; Liang-Teck Pang; Andrew R. Neureuther; Elad Alon; Borivoje Nikolic
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Systematic yield estimation method applying lithography simulation
Author(s): Suigen Kyoh; Soichi Inoue
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Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell
Author(s): Staf Verhaegen; Stefan Cosemans; Mircea Dusa; Pol Marchal; Axel Nackaerts; Geert Vandenberghe; Wim Dehaene
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Predicting yield using model based OPC verification: calibrated with electrical test data
Author(s): James A. Bruce; Tso-Hui Ting
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Exposure tool specific post-OPC verification
Author(s): John Sturtevant; Srividya Jayaram; Le Hong
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A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist
Author(s): Jonathan Ho; Yan Wang; Xin Wu; Jane Soward; Ping Zhang; Joanne Wu
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Predicting conversion time of circuit design file by artificial neural networks
Author(s): Sung-Hoon Jang; Jee-Hyong Lee; Byoung-Sup Ahn; Won-Tai Ki; Ji-Hyeon Choi; Sang-Gyun Woo; Han-Ku Cho
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System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator
Author(s): Mark C. Simmons; Jean-Marie Brunet; Seung-Weon Paek; Y. K. Kim
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An extraction of repeating patterns from OPCed layout data
Author(s): Yoshihiro Fujimoto; Masahiro Shoji; Kokoro Kato; Tadao Inoue; Masaki Yamabe
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Accurate model base verification scheme to eliminate hotspots and manage warmspots
Author(s): Shigeki Nojima; Suigen Kyoh; Shimon Maeda; Soichi Inoue
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ACLV- and process-window-aware extraction of transistor parameters using litho-friendly design (LfD) methodologies
Author(s): Reinhard März; Kai Peter; Monika Gschöderer; Eduard Ratai; Alexander Nielsen; Sascha Siegler; Rosi Deppe; Anton Huber
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Device performance-based OPC for optimal circuit performance and mask cost reduction
Author(s): Siew-Hong Teh; Chun-Huat Heng; Arthur Tay
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Concurrent development methodology from design rule to OPC in 45-nm node logic device
Author(s): Kenji Konomi; Shigeki Nojima; Shimon Maeda; Takeshi Fujimaki; Hirofumi Igarashi; Ryuji Ogawa; Shoji Mimotogi
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Improvement on OPC completeness through pre-OPC hot spot detection and fix
Author(s): Yeonah Shim; Jaeyoung Choi; Jeahee Kim; Bo Su; Ping Zhang; Keun-Young Kim
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DFM application on dual tone sub 50nm device
Author(s): Byoung-Sub Nam; James Moon; Joo-Hong Jung; Dong-Ho Kong; Se-young Oh; Cheol-Kyun Kim; Byung-Ho Nam; Dong Gyu Yim
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SEM contour-based model OPC calibrated with optically sensitive patterns
Author(s): Jee-Eun Jung; Mi-Kyeong Lee; Yong-Jin Cho; Sang-Ho Lee; Young-Seog Kang; Young-Kyou Park
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Hot spot management with die-to-database wafer inspection system
Author(s): Kohji Hashimoto; Satoshi Usui; Kenji Yoshida; Ichirota Nagahama; Osamu Nagano; Yasuo Matsuoka; Yuuichiro Yamazaki; Soichi Inoue
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32nm design rule evaluation through virtual patterning
Author(s): Scott Jessen; James Blatchford; Steve Prins; Simon Chang; Yiming Gu; Mark Smith; Dale Legband; Chris Sallee
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A new robust process window qualification (PWQ) technique to perform systematic defect characterization to enlarge the lithographic process window using a die-to-database verification tool (NGR2100)
Author(s): Tadashi Kitamura; Toshiaki Hasebe; Kazufumi Kubota; Futoshi Sakai; Shinichi Nakazawa; Michael Hoffman; Masahiro Yamamoto; Masahiro Inoue
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Continuous process window modeling for process variation aware OPC and lithography verification
Author(s): Qiaolin Zhang; Qiliang Yan; Yunqiang Zhang; Kevin Lucas
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Using composite gratings for optical system characterization through scatterometry
Author(s): Yu Ben; Jing Xue; Costas J. Spanos
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Rules based process window OPC
Author(s): Sean O'Brien; Robert Soper; Shane Best; Mark Mason
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RET selection using rigorous, physics-based computational lithography
Author(s): Sanjay Kapasi; Trey Graves; Mark D. Smith; Stewart Robertson; Chris Sallee
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APF pitch-halving for 22nm logic cells using gridded design rules
Author(s): Michael C. Smayling; Christopher Bencher; Hao D. Chen; Huixiong Dai; Michael P. Duane
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Site portability and extrapolative accuracy of a predictive resist model
Author(s): Jim Vasek; John J. Biafore; Stewart A. Robertson
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A comprehensive model of process variability for statistical timing optimization
Author(s): Kun Qian; Costas J. Spanos
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Application of layout DOE in RET flow
Author(s): Yunqiang Zhang; Paul van Adrichem; Ji Li; Amy Yang; Kevin Lucas
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Impact of gate line edge roughness on double-gate FinFET performance variability
Author(s): Kedar Patel; Tsu-Jae King Liu; Costas Spanos
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Validation and application of a mask model for inverse lithography
Author(s): Thuc H. Dam; Xin Zhou; Dongxue Chen; Anthony Adamov; Danping Peng; Bob Gleason
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Cell-based OPC with standard-cell fill insertion
Author(s): Liang Deng; Kai-Yuan Chao; Hua Xiang; Martin D. F. Wong
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Process variation in metal-oxide-metal (MOM) capacitors
Author(s): Lynn Tao-Ning Wang
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Decomposition difficulty analysis for double patterning and the impact on photomask manufacturability
Author(s): Yuichi Inazuki; Nobuhito Toyama; Takaharu Nagai; Takanori Sutou; Yasutaka Morikawa; Hiroshi Mohri; Naoya Hayashi; Martin Drapeau; Kevin Lucas; Chris Cork
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A method of obtaining optical lithography friendly layout using a model for first level defects
Author(s): Sungsoo Suh; Sukjoo Lee
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Checking design conformance and optimizing manufacturability using automated double patterning decomposition
Author(s): Chris Cork; Brian Ward; Levi Barnes; Ben Painter; Kevin Lucas; Gerry Luk-Pat; Vincent Wiaux; Staf Verhaegen; Mireille Maenhoudt
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Layout patterning check for DFM
Author(s): C. C. Chang; I. C. Shih; J. F. Lin; Y. S. Yen; C. M. Lai; W. C. Huang; R. G. Liu; Y. C. Ku
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Design based binning for litho qualification and process window qualification
Author(s): Andreas Fischer; Uwe Seifert; Arno Wehner; Laurent Karsenti; Mark Geshel; Amiad Conley; Dieter Gscheidlen; Avishai Bartov
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DFM software for photomask production and qualification of its accuracy and functionality
Author(s): Frank A. J. M. Driessen; J. Westra; K. G. Haens; E. Morita
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Electrically driven optical proximity correction
Author(s): Shayak Banerjee; Praveen Elakkumanan; Lars W. Liebmann; James A. Culp; Michael Orshansky
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