Mask Industry Assessment: 2007
Author(s):
Gilbert Shelden;
Patricia Marmillion;
Greg Hughes
Show Abstract
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by SEMI North America to
gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry
equipment makers. This year's assessment is the sixth in the current series of annual reports. With ongoing industry
support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and
microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and
opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path
issues. This year's survey is basically the same as the 2005 and 2006 surveys. Questions are grouped into categories:
General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times,
Returns and Services, Operating Cost Factors, and Equipment Utilization. Within each category is a multitude of
questions that create a detailed profile of both the business and technical status of the critical mask industry.
Compensating for image placement errors induced during the fabrication and chucking of EUVL masks
Author(s):
Roxann L. Engelstad;
Jaewoong Sohn;
Andrew R. Mikkelson;
Madhura Nataraju;
Kevin T. Turner
Show Abstract
With the stringent requirements on image placement (IP) errors in the sub-65-nm regime, all sources of mask
distortion during fabrication and usage must be minimized or corrected. For extreme ultraviolet lithography, the
nonflatness of the mask is critical as well, due to the nontelecentric illumination during exposure. This paper outlines
a procedure to predict the IP errors induced on the mask during the fabrication processing, e-beam tool chucking, and
exposure tool chucking. Finite element (FE) models are used to simulate the out-of-plane and in-plane distortions at
each load step. The FE results are compiled to produce a set of Correction Tables that can be implemented during e-beam
writing to compensate for these distortions and significantly increase IP accuracy. A previous version of this paper appeared in the Proceedings of the European Mask and Lithography Conference (EMLC), SPIE, 6533, 653314 (2007). The paper has been updated, retitled, and published here as a result of winning the Best Paper Award at the EMLC.
PMJ 2007 panel discussion overview: double exposure and double patterning for 32-nm half-pitch design node
Author(s):
Yoshinori Nagaoka;
Hidehiro Watanabe
Show Abstract
As part of the technical program in Photomask Japan 2007, we held a panel discussion to discuss challenges and
solutions for the double exposure and double patterning lithography technique for 32nm half-pitch design node. 4
panelists, Rik Jonckheere of IMEC (Belgium), Tsann-Binn Chiou of ASML Taiwan Ltd. (Taiwan), Judy Huckabay of
Cadence Design Systems Inc. (USA) and Yoshimitsu Okuda of Toppan Printing Co., Ltd. (Japan) were invited to
represent each key technical area.
We also took a survey from the PMJ attendees prior to the panel discussion, to vote which key technical area they think
the challenge exists for the 32nm half-pitch DE/DP lithography. The result of the survey was also presented during the
panel discussion.
One would intuitively think that by using a DE/DP technique you're relaxing the design rule by 2x, thus for 32nm node
it's essentially the 65nm process- you're just repeating it 2 times. Well, not exactly, as identified by the panelists and
the participants in the discussion. We recognized the difficulties in the LSI fabrication process steps, the lithography
tool overlay, photomask CD and registration, and the issue of data splitting conflict.
These difficulties are big challenge for both LSI and photomask manufactures; however, we have confirmed some
solutions are already examined by the theoretical and experimental works of the people in research. Despite these
difficulties, we are convinced that the immersion lithography with double exposure and double patterning techniques is
one of the most promising candidates of the lithography for 32nm half pitch design node.
Characterizing photomask etch processes by phase component analysis (PCA)
Author(s):
Richard Wistrom;
Toru Komizo;
Michael Hibbs;
Gary Reid
Show Abstract
One of the most important parameters of Attenuated Phase Shift Masks (APSM) is the uniformity of the phase over the
active area of the mask. Phase uniformity is an important component of lithographic process window stability.
Typically, an APSM blank consists of a quartz substrate upon which a Molybdenum Silicide (MoSi) attenuating film and
a Chromium (Cr) film have been deposited to act as a hard mask for the MoSi etch. There are many factors that
contribute to phase non-uniformity of the final mask: thickness non-uniformity of the films, non-uniformity of the Cr
etch and MoSi etch, and non-uniformity of the MoSi overetch into the quartz substrate. Phase of a completed mask is
routinely measured, but quantifying how these individual components contribute to the overall phase non-uniformity is
challenging. This report focuses on understanding how MoSi etch contributes to phase non-uniformity. Phase
uniformity is compared for three different MoSi etch processes.
The advanced mask CD MTT control using dry etch process for sub 65 nm tech
Author(s):
Sang Jin Jo;
Ho Yong Jung;
Dong Wook Lee;
Jae Cheon Shin;
Jea Young Jun;
Tae Joong Ha;
Oscar Han
Show Abstract
As the design rule of the semiconductor circuit shrinks, the specification for photomask becomes tighter. So, more
precise control of CD MTT (Critical Dimension Mean to Target) is required. We investigated the CD MTT control of the
attenuated PSM (Phase Shift Mask) by additional Cr dry etch. In conventional process, it is difficult to control CD MTT
precisely because about 5 factors - Blank Mask, E-beam writing, Resist develop, Cr dry etch, MoSiN dry etch - affect
CD MTT error. We designed the new process to control CD MTT precisely. The basic concept of the new process is to
reduce the number of factors which affect the CD MTT error. To correct CD MTT error in the new process, we
measured CD before MoSiN dry etch, and then additional corrective Cr dry etch and MoSiN dry etch was performed. So,
the factors affecting CD MTT error are reduced to 2 steps, which is additional corrective Cr dry etch and MoSiN dry
etch. The reliability of CD measurement before MoSiN dry etch was evaluated. The generable side-effect of the
additional corrective Cr dry etch was analyzed. The relationship between 'CD shift' and 'additional corrective Cr dry
etch time' was found for various patterns. As a result, accurate CD MTT control and significant decrease of CD MTT
error for attenuated PSM is achieved.
CD bias control with in-situ plasma treatment in EPSM photomask etch
Author(s):
Karmen Yung;
Chang-Ju Choi;
Ki-Ho Baik
Show Abstract
As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded
Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials,
Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the
shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi
etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested
to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas
and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface
modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for
redundancy tools in mask production environment.
Effects of exposure environment on pellicle degradation in ArF lithography
Author(s):
Hyungseok Choi;
Yohan Ahn;
Jeongin Yoon;
Yangkoo Lee;
Yongjhin Cho;
Jongann Kim
Show Abstract
With the introduction of ArF laser, its high photon energy affects the pellicle degradation in direct. The components
outgassed from the damaged pellicle have the effect on the CD variation of reticle. In order to resolve this new inevitable
problem, the method of dry gas purge has been proposed among the various solutions recently. Dry gas purge method is
generally applied to two applications. It can be applied to a storage environment such as reticle stocker, reticle SMIF pod
and reticle library in scanner and to the exposure chamber inside of a scanner during ArF laser exposure phase directly.
In this case, it is quite important technologically that which gas is determined as dry purge gas, pure nitrogen or CDA
(clean dry air). In this study, the effects of exposure environment on pellicle degradation according to dry purge gas and
their mechanism has been investigated to propose strategies and solutions of dry gas purge technology.
Development and characterization of a new low stress molybdenum silicide film for 45 nm attenuated phase-shift mask manufacturing
Author(s):
Thomas Faure;
Emily E. Gallagher;
Louis Kindt;
Steven Nash;
Ken Racette;
Richard Wistrom;
Toru Komizo;
Yasutaka Kikuchi;
Satoru Nemoto;
Yushin Sasaki;
Atsushi Kominato;
Toshiyuki Suzuki
Show Abstract
As optical lithography is extended for use in manufacturing 45 nm devices, it becomes increasingly important to
maximize the lithography process window and enable the largest depth of focus possible at the wafer stepper.
Consequently it is very important that the reticles used in the wafer stepper be as flat as possible. The ITRS roadmap
requirement for mask flatness for 45 nm node is 250 nm. To achieve this very tight reticle flatness requirement, the stress
of each film present on the mask substrate must be minimized. Another key reticle specification influenced by film stress
on the mask blank is image placement. In this paper, we will describe the development and detailed characterization of a
new low stress Molybdenum Silicide (MoSi) film for use in manufacturing 45 nm node critical level attenuated phase
shift masks to be used in 193 nm immersion lithography. Data assessing and comparing the cleaning durability, mask
flatness, image placement, Critical Dimension (CD) performance, dry etch properties, phase performance, and defect
performance of the new low stress MoSi film versus the previous industry standard A61A higher stress MoSi attenuator
film will be described. The results of our studies indicate that the new low stress MoSi film is suitable for 45 nm mask
manufacturing and can be introduced with minimal changes to the mask manufacturing process.
Evaluation of the effect of mask-blank flatness on CDU and DOF in high-NA systems
Author(s):
Christopher Lee;
Chia Wen Chang;
Tomas Chin;
Richard Lu;
Steven Fan;
Derek Chen;
Gordon Chan;
Torey Huang
Show Abstract
The purpose of paper is to investigate the impact of mask blank flatness on critical
dimension uniformity (CDU) and depth of focus (DOF) in the wafer printing process
with a test pattern designed for 65nm node technology. In this experiment we use 3
test masks with different flatness (0.3T, 0.5T and 1T), and the same test pattern array.
The mask flatness was measured with a Tropel® UltraFlatTM 200, and the focus error
is extracted from the CD data of the focus and energy matrix (FEM) analysis.
The goal of the study is to quantify the mask flatness influence on the high-numerical
aperture (NA) lithographic process.
The development of full field high resolution imprint templates
Author(s):
Shusuke Yoshitake;
Hitoshi Sunaoshi;
Kenichi Yasui;
Hideo Kobayashi;
Takashi Sato;
Osamu Nagarekawa;
Ecron Thompson;
Gerard Schmid;
Douglas J. Resnick
Show Abstract
Critical to the success of imprint lithography and Step and Flash Imprint Lithography (S-FIL®) in particular is the
manufacturing 1X templates. Several commercial mask shops now accept orders for 1X templates. Recently, there have
been several publications addressing the fabrication of templates with 32nm and sub 32nm half pitch dimensions using
high resolution Gaussian beam pattern generators. Currently, these systems are very useful for unit process
development and device prototyping. In this paper, we address the progress made towards full field templates suitable
for the fabrication of CMOS circuits.
The starting photoplate consisted of a Cr hard mask (≤ 15nm) followed by a thin imaging layer of ZEP 520A. The
EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern
the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the
EBM-5000 include higher current density (70 A/cm2), astigmatism correction in the subfields, optimized variable stage
speed control, and improved data handling to increase the maximum shot count limitation.
To fabricate the template, the patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as
an etch block for the fused silica. A mesa is formed by etching the non-active areas using a wet buffered oxide etch
(BOE) solution. The final step in the template process is a dice and polish step used to separate the plate into four
distinct templates.
Key steps in the fabrication process include the imaging and pattern processes. ZEP520A was chosen as the e-beam
resist for its ability to resolve high resolution images. This paper documents the resolution and image placement
capability with the processes described above. Although ZEP520A is slow relative to chemically amplified e-beam
resists, it is only necessary to pattern 1/16th the area relative to a 4X reduction mask. Write time calculations for 1X
templates have also been performed, and are compared to 4X photomasks.
Defect reduction progress in step and flash imprint lithography
Author(s):
K. Selenidis;
J. Maltabes;
I. McMackin;
J. Perez;
W. Martin;
D. J. Resnick;
S. V. Sreenivasan
Show Abstract
Imprint lithography has been shown to be an effective method for the replication of nanometer-scale
structures from a template mold. Step and Flash Imprint Lithography (S-FIL®) is unique in its ability to address both
resolution and alignment. Recently overlay across a 200 mm wafer of less than 20nm, 3σ has been demonstrated.
Current S-FIL resolution and alignment performance motivates the consideration of nano-imprint lithography as Next
Generation Lithography (NGL) solution for IC production. During the S-FIL process, a transferable image, an imprint,
is produced by mechanically molding a liquid UV-curable resist on a wafer. The novelty of this process immediately
raises questions about the overall defectivity level of S-FIL. Acceptance of imprint lithography for CMOS
manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective
device production. This report specifically focuses on this challenge and presents the current status of defect
reduction in S-FIL technology and will summarize the result of defect inspections of wafers patterned using S-FIL.
Wafer inspections were performed with a KLA Tencor- 2132 (KT-2132) automated patterned wafer inspection tool.
Recent results show wafer defectivity to be less 5 cm-2. Mask fabrication and inspection techniques used to obtain low
defect template will be described. The templates used to imprint wafers for this study were designed specifically to
facilitate automated defect inspection and were made by employing CMOS industry standard materials and exposure
tools. A KT-576 tool was used for template defect inspection.
Fabrication of nano-imprint templates for dual-Damascene applications using a high resolution variable shape E-beam writer
Author(s):
Marcus Pritschow;
Joerg Butschke;
Mathias Irmscher;
Holger Sailer;
Douglas Resnick;
Ecron Thompson
Show Abstract
A 3D template fabrication process has been developed, which enables the generation of high resolution, high aspect
pillars on top of lines. These templates will be used to print both vias and metal lines at once for the dual damascene
technology. Due to the complexity of state of the art CMOS designs only a variable shape e-beam (VSB) writer
combined with chemically amplified resists (CAR) can be considered for the patterning process. We focused our work
especially on the generation of high aspect pillars with a diameter below 50nm and the development of suitable overlay
strategies for getting a precise alignment between the two template tiers. In this context we investigated the influence of
exposure strategies on the overlay result across the entire imprint area of 25mm × 25mm. Finally, we realized templates
according to the MII standard with different test designs and confirmed printability of one of them on a MII tool.
The study of CD error in mid-local pattern area caused by develop loading effect
Author(s):
Man-Kyu Kang;
Jung-Hun Lee;
Seong-Yoon Kim;
Byung-Gook Kim;
Sang-Gyun Woo;
Han-Ku Cho
Show Abstract
As the design rule has decreased in semiconductor manufacturing, the ITRS roadmap requires significantly tighter
critical dimension control. Especially, CD error caused by develop loading become significant in the overall error
budget and has approached to over 5nm. It is very difficult to control dissolution product making the change of
dissolution rate by chemical flow direction in develop process.
These days, the study of develop loading within global area has significantly progressed. However, we will focus on CD
error in mid-local area by using a detailed analysis. And we evaluate these phenomenon caused by pattern density
difference, called chemical flare. Even though using several developer types, CD error appears at the chip to chip
boundary. It is impossible to correct CD error in this area by electron beam correction. Therefore, this paper analyzed
about CD error in a value of several tens ~ hundreds nm. In view of develop loading, we will optimize develop process
for improvement of CD error.
Performance improvement of ALTA4700 for 130nm and below mask productivity
Author(s):
Jyh Wei Hsu;
David Lee;
Chen Rui Tseng;
Eric Hong;
Chun Hung Wu
Show Abstract
ALTA4700 DUV laser pattern generator employs chemical amplified resist to get better resolution. The capability of
ALTA4700 for 130nm technology node mask production is obviously. Further improvement on ALTA4700 was
performed to meet the state-of-the-art mask requirement. System optimization eliminates unusual critical dimension (CD)
points and then reduces the range of uniformity. Appropriate post-exposure baking (PEB) temperature gets larger mask
printing window and better CD linearity. ALTA4700 incorporate NTAR7 blank with particular dry etch recipe, the mask
CD uniformity reduced from 25 to 15nm (range). Good Cr layer profile also obtains.
The behavior of substrate dependency as surface treatment in the positive chemically amplified resist
Author(s):
Sin-Ju Yang;
Han-Sun Cha;
Ju-Hyun Kang;
Chul-Kyu Yang;
Jin-Ho Ahn;
Kee-Soo Nam
Show Abstract
Positive chemically amplified resist (CAR) is widely used because of its benefit to high resolution in the
semiconductor industry. Recent numerous studies have reported that resist pattern error such as resist scum and adhesion
fail at the interface between substrate and positive CAR is caused by substrate dependency. Hence resist pattern error
must be minimized. In this study we have observed the phenomena at the positive CAR coated mask blanks. And then
we applied various surface treatments to the Cr film to minimize resist pattern error.
Firstly, resist pattern error was occurred by the substrate dependency in the positive CAR coated mask blanks. We
have investigated the root causes of this pattern error, we found that nitrogen radical and OH radical in the Cr film could
combine with proton in the positive CAR easily. So various surface treatments were applied to minimize detrimental
effects of substrate dependency to the positive CAR. And the behavior of substrate dependency was observed by various
analyses to verify the effect of surface treatment method. The results showed that substrate dependency could be
controlled by surface treatment in the positive CAR coated mask blanks.
Design for CD correction strategy using a resist shrink method via UV irradiation for defect-free photomask
Author(s):
Jin Ho Ryu;
Dong Wook Lee;
Ho Yong Jung;
Sang Pyo Kim;
Oscar Han
Show Abstract
As the specification for photomask becomes tighter, it is strongly demanded for achieving precise CD MTT (critical
dimension mean to target) and enhanced defect controllability in photomask fabrication. First of all, it is necessary that
reducing the factors of CD MTT error and introducing the reliable method to correct CD error for accurate CD
requirement of attenuated PSM (phase shift mask). From this point of view, one of CD correction methods which consist
of Cr CD measurement step after resist strip (strip inspection CD: SI CD) and additional corrective Cr dry etch step was
developed. Previous SI CD correction process resulted in accurate CD control within the range of CD MTT. However it
was not appropriate for defect control due to additional resist processes for selective protection of Cr pattern during CD
correction process.
In this study, the method for achieving precise CD MTT by correcting CD error without any resist process is
investigated. It is not suitable for the CD correction process to control CD MTT precisely that Cr etched resist (etch
inspection CD: EI CD) is very vulnerable to E-beam scanning during CD measurement. Otherwise, photoresist after Cr
etch selectively shrinks via UV irradiation under ozone (O3) condition, which drives a reduction of CD MTT error as a
result of accurate CD measurement (UV-irradiation inspection CD: UI CD). Moreover, it is not necessary any resist
process for Cr protection due to UV irradiated resist as enough for a etch barrier. It is a strong advantage of novel CD
correction method. This strategy solves the problems such as both CD measurement error on the EI CD correction
method and defects originated from resist process on the SI CD correction method at once. For the successful
incorporation of UI CD correction method, several items related with CD should be evaluated: accuracy and repeatability
of CD measurement under UI CD, control of CD MTT and CD uniformity, additional corrective etch bias for UI CD,
independence of corrective Cr etch process from UV irradiated resist, isolated-dense CD difference,.. etc. In this paper,
strategy of design for the progressive CD correction method for defect-free photomask and process details will be
discussed.
The impact of mask photoresist develop on critical dimension parameters
Author(s):
Adam C. Smith;
Daniel B. Sullivan;
Kazuhiko Sugawara;
Yusuke Okawa
Show Abstract
As the tolerances for photomask Critical Dimension (CD) become smaller, more focus has been placed on all processes
and their contribution to final mask CD. One key contributor to final mask feature dimensions is the resist develop
process and it is the focus of this work. We have studied different resist develop methods to determine optimum process
conditions for 45 nm critical photomasks. In searching for the optimum conditions, special consideration was made to
study the influence of pattern density effects. We focused on variations in the develop nozzle. Results of the nozzles'
impact on pattern density and long range pattern density effects will be presented, for both positive and negative
chemically-amplified resists. A characterization of the repeatability of the processes will be presented as well.
New method of contour-based mask-shape compiler
Author(s):
Ryoichi Matsuoka;
Akiyuki Sugiyama;
Akira Onizawa;
Hidetoshi Sato;
Yasutaka Toyoda
Show Abstract
We have developed a new method of accurately profiling a mask shape by utilizing a Mask CD-SEM.
The method is intended to realize high accuracy, stability and reproducibility of the Mask CD-SEM
adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD
measurement. In comparison with a conventional image processing method for contour profiling, it is
possible to create the profiles with much higher accuracy which is comparable with CD-SEM for
semiconductor device CD measurement. In this report, we will introduce the algorithm in general, the
experimental results and the application in practice.
As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC
(Optical Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the
view point of DFM (Design for Manufacturability), a dramatic increase of data processing cost for
advanced MDP (Mask Data Preparation) for instance and surge of mask making cost have become a big
concern to the device manufacturers. In a sense, it is a trade-off between the high accuracy RET and the
mask production cost, while it gives a significant impact on the semiconductor market centered around
the mask business. To cope with the problem, we propose the best method for a DFM solution in which
two dimensional data are extracted for an error free practical simulation by precise reproduction of a real
mask shape in addition to the mask data simulation. The flow centering around the design data is fully automated and provides an environment
where optimization and verification for fully automated model calibration with much less error is
available. It also allows complete consolidation of input and output functions with an EDA system by
constructing a design data oriented system structure. This method therefore is regarded as a strategic
DFM approach in the semiconductor metrology.
Development of mask-DFM system "MiLE" load estimation of mask manufacturing
Author(s):
Yoshikazu Nagamura;
Kunihiro Hosono;
Shogo Narukawa;
Hiroshi Mohri;
Naoya Hayashi;
Masahiro Kato;
Hidemichi Kawase
Show Abstract
Load of photomask manufacturing for the most advanced semiconductor devices is increasing due to the complexity of
mask layouts caused by highly accurate RET or OPC, tight specification for 2D/3D mask structures, and requirements of
quick deliveries. The mask cost becomes a concern of mask users especially in SoC businesses because the number of
masks required throughout the wafer process is almost the same for each product regardless of the variety in production
volume when a unified platform is applied to the designs. Shares of mask cost within total production cost cannot be
ignored especially in small volume SoC products.
DFM (design for manufacturing) is inevitable in a mask level as well as in a wafer level to solve the cost problem.
"Mask-DFM" is a method to decrease the burden of mask manufacturing and to improve the yield and quality of masks,
not only by modification of mask pattern layouts (design) but also all other things including utilization of designer's
intents.
We have developed our Mask-DFM system called "MiLE", that calculates mask-manufacturing workload through
layout analyses combining information of mask configuration, and visualizes the consequence of Mask-DFM efforts.
"MiLE (Mask manufacturIng Load Estimation)" calculates a relative index which represents the mask manufacturing
workload determined by factors of 1) EB writing, 2) defect inspection/repair, 3) materials and processes and 4)
specification. All the factors are computed before tape-outs for mask making in the system by the following methods.
To estimate EB writing time, we applied high-throughput simulator and counted the number of "shot", minimum figure
unit in EB writing, by using post-OPC layout data. Mask layout that caused troubles and extra load in mask
inspection or repair was specified from MRC (mask rule checking) of the same post-OPC data. Additional layout
analysis perceives designer's intents that are described in the layout data and these are reflected in the calculation of the
"MiLE" index. Finally, chip arrangement on a mask is retrieved from so-called electronic mask spec sheets to construct mask layouts.
"MiLE" notifies to designers the index of mask manufacturing workload that is caused by mask layout, while modification and adjustments of design or OPC are iterated to maximize device productivity in early design phases. Therefore, designers can judge and control the mask manufacturability, or mask cost by designs and additional intents
useful for mask making. In the production phases, our system releases useful information for mask manufacturing to a mask shop and decreases the mask manufacturing workload. In this paper, we report the outline and functions of MiLE system and the results of mask manufacturing workload calculation using post-OPC layout data.
DFM for maskmaking: design-aware flexible mask-defect analysis
Author(s):
Frank A. J. M. Driessen;
J. Westra;
M. Scheffer;
K. Kawakami;
E. Tsujimoto;
M. Yamaji;
T. Kawashima;
N. Hayashi
Show Abstract
We present a novel software system that combines design intent as known by EDA designers with defect inspection
results from the maskshop to analyze the severity of defects on photomasks. The software -named Takumi Design-
Driven Defect Analyzer (TK-D3A)- analyzes defects by combining actions in the image domain with actions in the
design domain and outputs amongst others flexible mask-repair decisions in production formats used by the maskshop.
Furthermore, TK-D3A outputs clips of layout (GDS/OASIS) that can be viewed with its graphical user interface for easy
review of the defects and associated repair decisions. As inputs the system uses reticle defect-inspection data (text and
images) and the respective multi-layer design layouts with the definitions of criticalities.
The system does not require confidential design data from IDM, Fabless Design House, or Foundry to be sent to the
maskshop and it also has minimal impact on the maskshop's mode of operation. The output of TK-D3A is designed to
realize value to the maskshop and its customers in the forms of: 1) improved yield, 2) reduction of delivery times of
masks to customers, and 3) enhanced utilization of the maskshop's installed tool base.
The system was qualified together with a major IDM on a large set of production reticles in the 90 and beyond-65 nm
technology nodes of which results will be presented that show the benefits for maskmaking. The accuracy in detecting
defects is extremely high. We show the system's capability to analyze defects well below the pixel resolution of all
inspection tools used, as well as the capability to extract multiple types of transmission defects. All of these defects are
analyzed design-criticality-aware by TK-D3A, resulting in a large fraction of defects that do not need to be repaired
because they are located in non-critical or less-critical parts of the layout, or, more importantly, turn out to be repairable
or negligible despite of originally being classified as unrepairable when no such criticality knowledge is used. Finally,
we show that the runtimes of TK-D3A are relatively short, despite the fact that the system operates on full-chip designs.
Use of layout automation and design-based metrology for defect test mask design and verification
Author(s):
Chris Spence;
Cyrus Tabery;
Andre Poock;
Arndt C. Duerr;
Thomas Witte;
Jan Fiebig;
Jan Heumann
Show Abstract
This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the
reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made
extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that
was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to
simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create
accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper
allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data
is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the
paper are applicable to all layers.
Intel's AMT enables rapid processing and info-turn for Intel's DFM test chip vehicle
Author(s):
Hazem Hajj
Show Abstract
Transistor dimensions are quickly approaching atomic levels. Metrology is already a challenge. Several technologies
have evolved to keep pace such as scatterometry and bare wafer inspection. Lithography critical dimensions, registration
and pitch are the forefront of dimensional scaling challenges. Variability at these dimensions can limit function,
performance, yield and profitability with design for manufacturing (DFM) challenges. Intel's integrated device
manufacturing (IDM) model has enabled many technologies and disciplines to come together to provide the most cost
effective and optimal solutions to Moore's law scaling challenges. Intel's Automated Manufacturing Technology (AMT)
capabilities play a significant role in enabling optimal Moore's law scaling solutions. The information turn cycle starts
with the definition of the technology Test Chip and ends with the analysis of results from end of line (EOL) metrology.
We will discuss the relevant DFM elements of AMT to enable: test-chip setup, computational lithography and
validation, product & process modeling and setup, intelligence and control to minimize variability, rapid yield learning,
and rapid product design learning.
From rule to model-based design: A need for DfP criteria?
Author(s):
A. Balasinski;
N. Kachwala;
D. Abercrombie
Show Abstract
Traditional design rules to ensure device functionality and yield are defined by multiple criteria. However, in a complex
and mature design and manufacturing environment and a quickly changing marketplace, one should consider a more
comprehensive and efficient way to gradually replace the rigid design rules with yield and product models based on the
extracted layout features, process capabilities, and market conditions. This methodology may be of particular
attractiveness for custom products such as Systems-on-Chip where the complexity of customized design rules can be a
detriment for product optimization. In addition, the key criterion for product development: profitability in the
marketplace, or Design-for-Profit (DfP), has usually not been taken into account in the verification of design kits. In this
paper, we would discuss how yield models can help re-derive the existing design rule and "recommended rule"
methodology and take it to the next level of a comprehensive product development using model based design.
Accurate lithography analysis for yield prediction
Author(s):
Greg Yeric;
Babak Hatamian;
Rahul Kapoor
Show Abstract
New DFM tools appearing on the market hold a promise of assessing parametric and functional
yield loss due to lithography effects. The accuracy of underlying models can limit the veracity
of such assessment. For example, many lithography steps used in the fab are extremely nonlinear
and might exhibit significant differences from models used by the DFM tools.
Furthermore, inputs used in calibrating a model can limit its accuracy, and most organizations
are challenged to characterize the exact needs of a lithography model at a statistically relevant
sampling size. After discussing potential sources of inaccuracy in modeling, the paper will
describe a methodology for modeling and yield prediction based on such accurate modeling.
Production-worthy full chip image-based verification
Author(s):
Zongchang Yu;
Youping Zhang;
Yanjun Xiao;
Wanyu Li
Show Abstract
At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional
model-based verification at only the nominal condition. Full-chip, full process-window verification has started to
integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from
reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at
each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and
predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose
variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried
out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the
robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based
approach for post-OPC verification in detail.
For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly
interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its
susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging.
Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed
situation.
At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is
not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of
the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance
to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers.
We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show
the performance of the full-chip image-based verification.
Layout verification in the era of process uncertainty: requirements for speed, accuracy, and process portability
Author(s):
J. Andres Torres;
Ioana Graur;
Mark C. Simmons;
Suniti Kanodia
Show Abstract
A few years ago, model-based layout verification was used primarily with mask data preparation as a safety net to predict and avoid limited printability performance prior to mask fabrication. If certain layout locations would transfer poorly onto the wafer, the mask data was intercepted, preventing yield loss associated with "mask issues."
Such mask-related issues come primarily from three sources: Mask manufacture bias, OPC limitations and intrinsic layout configurations. While mask manufacture bias and OPC limitations can be addressed during the final stages of mask synthesis and manufacture, layout configurations that exhibit poor lithographic performance for a given process cannot be modified without considering the electrical effect such new topologies will induce in the modified layout.
In principle, marginally performing layouts can be removed from the design by adequately interpreting geometric design rules. Unfortunately, while such rules are strictly defined for 1D, they are not as well-defined for arbitrary 2D configurations. For that reason, several approaches to transferring sufficient process information to the layout synthesis tools to prevent the presence of layout configurations incompatible with the production process have been attempted. However, when the production process is not fully developed, using these approaches can potentially limit the portability of the layout.
In this paper, we describe and evaluate different approaches to defining reasonable layout verification targets by exploring various methods to reduce verification time, maintain accuracy and improve layout portability. First, to reduce verification time, we implement a method to quickly scan the layout for large variations without the need to run the actual OPC recipe. This paper describes the characteristics of a model that defines a pseudo-OPC process. Next, because the pseudo-OPC process cannot be mapped exactly to the real OPC process, there are accuracy limitations when using only the pseudo-OPC process. To overcome these limitations, the verification system follows an incremental approach, in which those regions previously selected are evaluated with the full mask synthesis recipe to reduce the number of falsely detected errors. Finally, to investigate the issue of portability, we evaluate how different errors evolve with maturing process and OPC recipe conditions for different layout patterns.
A lithography aware design optimization using foundry-certified models and hotspot detection
Author(s):
L. Karklin;
A. Arkhipov;
D. Blakely;
M. Dingenen;
A. Mehrotra;
B. Watson;
C. Zelnik;
M. Cote;
P. Hurat
Show Abstract
An automated litho-aware design migration solution has been implemented to enable designers to port existing IP layouts
(custom, library, and block) to nanometer technologies while optimizing layout printability and silicon yield.
With rapidly shrinking technology nodes, the industry consolidation toward fabless or fab-lite manufacturing, demand
for second-sourcing and dramatic increase in cost of IP development, the automation of "vertical" (between nodes) and
'horizontal" (between chip manufacturers) migration becomes a very important task. The challenge comes from the fact
that even within the same technology node design and process-induced rules deviate substantially among different IDMs
and foundries, which leads to costly, error-prone and time consuming design modifications. At the same time, fast and
reliable adjustments to design and ability to switch between processes and chip manufacturers could represent significant
improvement to TTM, and respectively improving ROI. Using conservative rules (or restricted design rules) is not
always a viable option because of the area, performance and yield penalties. The difficulty of migration is augmented by
the fact that design rules are not sufficient to guaranty good printability, maximum process window and high yield.
Model-based detection of lithography-induced systematic yield-limiting defects (a.k.a. hotspots) is becoming a vital part
of the design-for-manufacturing flow for advanced technology nodes at 65nm and below. Driven by customer demand, a
collaborative effort between EDA vendors provides a complete design-for-manufacturing migration solution that allows
sub-65 nanometer designers to comprehensively address the impact of manufacturing variations on design yield and
performance during layout migration. First, the physical hard IP is migrated from its existing 90nm process to a more
advanced 65 and 45 nm processes, resulting in an area-optimized DRC-clean 65nm design retaining the original
hierarchy to facilitate further editing and design verification the original hierarchy is maintained. Then, the design
manufacturability is checked using a model-based hotspot detection solution, applying foundry-certified models. Along
with hotspots, it is also critical for the hotspot detection tool to generate directives on how to modify the layout to fix
hotspots and prevent creation of new hotspots. Several alternative fixing guidelines, ranked by amount of design
perturbation, are generated to provide focus and maximum flexibility to the correction tool. The correction tool reads
hotspot locations, severities along with the fixing guidelines, identifies area to be fixed and converts the fixing guidelines
into geometry constraints. Correction is then done on each area while respecting design rules, managing ripple effects
through multiple layers and maintaining the hierarchy. When all the corrections are completed areas that have been
affected are identified to allow these to be incrementally checked by the lithography verification tool (LPC) and re-assembled.
In case new or residual hotspots are detected, this fix-verify flow iterates over to converge on a DRC and
lithography-compliant design. Usually no more than three iterations are needed to output hotspot-free, DRC and Lithocompliant
design. We present the results of this fully automated lithography-aware migration flow on layout IPs ranging
from 65 nm to 45 nm design and migrated across foundries. Results show substantial layout quality improvements,
reduced design sensitivity to process variability by eliminating hotspots. Run-time and hotspot fixing performance are
shown.
Litho-aware extraction for the 32nm double patterning node
Author(s):
Judy Huckabay;
Quentin Chen;
Craig Thayer;
Robert Naber
Show Abstract
A methodology to predict the impact of mask overlay and litho-induced process variations on Statistical
Timing for Double Patterning is presented. As we migrate to the 32nm node and Double Patterning
techniques, Mask Makers, Ebeam providers and Scanner providers are given very aggressive requirements
for maintaining overlay accuracy. This method takes into account Mask CD Uniformity and Mask Image
placement error budgets presented in the 2006 ITRS. It is assumed the ITRS requirements are met. This
methodology combines the infrastructure used in Single Exposure Litho-Aware Layout Implementation
tools with Double Patterning decomposition results to determine a meaningful layout-specific analysis for
pre-tape-out timing sign-off. Traditional timing analysis uses a set of look-up tables for simulating device
distortions. These tables have been proven to require excessive guardbanding in Single Exposure masks.
Adding the additional dimension of overlay distortion to these tables will have the effects of hiding
parametric failures, or requiring excessive guardbanding to ensure timing predictability. Results will be
shown that describe the timing effects with and without taking into account these distortions, as well as
design samples that contribute to these distortions.
Silicon-verified automatic DFM layout optimization: a calibration-lite model-based application to standard cells
Author(s):
Kuang-Kuo Lin;
Ban P. Wong;
Frank A. J. M. Driessen;
Etsuya Morita;
Simon Klaver
Show Abstract
DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product
designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful,
these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With
these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long
and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness.
An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM
optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM
model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and
silicon experiment results will be presented.
Non-uniform yield optimization for integrated circuit layout
Author(s):
Fedor G. Pikus;
J. Andres Torres
Show Abstract
We demonstrate a consolidated metric that can quantitatively express design quality with respect to multiple yield loss
mechanisms. Using this metric and the design analysis and optimization framework we have developed, we study the
effectiveness of different layout enhancements and the effect of combining multiple enhancements in a single layout.
Previous works attempted to select a single combination of design enhancements that presents the optimal trade-off
between different yield loss mechanisms and optimizes the total yield. We show that the optimal solution depends on
the layout features on a small scale, thus the best yield can be achieved by selecting different combinations of
enhancements in different locations. We introduce a general form of the cost function and compare different layout
configurations, taking into account lithography process variations, random defect distributions, and recommended
design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically
determine the most robust layout implementation according to the cost function that incorporates the relative
importance of each yield loss contributor. We compare the globally optimized layout, where the sequence of yield
enhancements is selected based on the overall design yield, with locally optimized layouts, where the enhancements are
fine-tuned for each location.
We show that when comparing different layout enhancements it is important to consider two types of yield tradeoffs,
local tradeoffs where the same layout feature impacts several yield loss mechanisms, and global tradeoffs where the net
effect of a particular type of layout enhancement depends on its location. By selectively applying yield enhancements to
the areas of the layout where they are needed we can considerably improve the overall design quality.
Lateral interactions between standard cells using pattern matching
Author(s):
Lynn Tao-Ning Wang;
Andrew R. Neureuther
Show Abstract
This paper proposes a novel method of identifying interactions between neighboring standard cells via fast-CAD pattern
matching. Studies of cell-to-cell interactions for both metal 1 and poly layouts are made for selected samples from
libraries for 130 and 90 nm generations provided under an NDA agreement by ST Microelectronics. Both simulation and
pattern matching are utilized to identify and quantify hot-spots. The physical basis for pattern matching is described. In
validating pattern matching compared to full simulation, changes in linewidth for a fixed defocus setting varied
quadratically with pattern match factor and can be modeled by a parabolic equation with an r-squared value of 0.77.
Results demonstrate that there is a considerable best-to-worst variation of 4-7% in the linewidth among neighbors, which
is produced through a focus swing of 0.58 Rayleigh Units (RU). The focus swing is oscillatory with cell separation
distance, and a slight shift in spacing on the order of 0.5 λ /NA can mitigate lateral interaction effects.
Selecting and using a lithography compliance DFM tool for 65-nm foundry production
Author(s):
Babak Hatamian;
Rahul Kapoor
Show Abstract
DFM tools have been all the rage in recent years. By exposing potential
manufacturability, timing and variation issues early, these tools can help the designers
correct such issues before the tape out. Such an early intervention delivers a faster
yield ramp for the product. For the lower volume devices, the faster yield ramp can help
meet the market window while for higher volume devices it can also mean millions of
dollars in cost savings. While there have been several DFM product announcements,
case studies focusing on actual usage of such tools are not publicly available.
In this article we share the data from a real customer evaluation and deployment. This
North American customer has deployed the tool and completed several TSMC 65nm
layouts.
By focusing on the motivation to use such a tool, the article will first quantify the
expected value from such a tool. Next the article will present the detailed evaluation
criteria for choosing a tool. Finally, actual error data from production tape outs and
performance metrics of the LCC tool will be presented showing runtime, scalability and
memory numbers.
Investigation of mask defectivity in full field EUV lithography
Author(s):
Rik Jonckheere;
Fumio Iwamoto;
G. F. Lorusso;
A. M. Goethals;
K. Ronse;
H. Koop;
T. Schmoeller
Show Abstract
A detailed defect printability analysis is reported for conditions that are fully representative for the world's first full field
EUV scanner, using 4X reticles, as obtained by simulation. For absorber type defects the historical rule of thumb
underestimates the printability. An opaque defect located in a space within a 40nm lines and space pattern can already
cause more than a 10% change in the space width from 80% of the space width onwards (>32nm at mask scale, >8 nm at
wafer scale) depending on its location. Absorber type clear defects start affecting line width in 40nm lines and spaces
from about twice the size of an opaque defect. Particles simulated as carbon cubes have a similar effect as absorber type
opaque defects provided that they are about 50% larger. Other possible particle materials are investigated as well. Local
carbon deposition, which may originate from SEM inspection, can cause a printing effect already at a thickness of only
2nm. Multilayer or substrate type defects require surface smoothing to less than about 2nm, as to keep the impact of so-called
phase defects under control. Experimental plans for comparison of simulations to exposures on the ASML Alpha
Demo Tool installed at IMEC are included.
Detectability and printability of EUVL mask blank defects for the 32-nm HP node
Author(s):
Wonil Cho;
Hak-Seung Han M.D.;
Kenneth A Goldberg;
Patrick A Kearney;
Chan-Uk Jeon
Show Abstract
The readiness of a defect-free extreme ultraviolet lithography (EUVL) mask blank infrastructure is one of the main
enablers for the insertion of EUVL technology into production. It is essential to have sufficient defect detection
capability and understanding of defect printability to develop a defect-free EUVL mask blank infrastructure. The
SEMATECH Mask Blank Development Center (MBDC) has been developing EUVL mask blanks with low defect
densities with the Lasertec M1350 and M7360, the 1st and 2nd generations, respectively, of visible light EUVL mask
blank inspection tools. Although the M7360 represents a significant improvement in our defect detection capability, it
is time to start developing a 3rd generation tool for EUVL mask blank inspection. The goal of this tool is to detect all
printable defects; therefore, understanding defect printability criteria is critical to this tool development.
In this paper, we will investigate the defect detectability of a 2nd generation blank inspection tool and a patterned
EUVL mask inspection tool. We will also compare the ability of the inspection tools to detect programmed defects
whose printability has been estimated from wafer printing results and actinic aerial images results.
Measuring and characterizing the nonflatness of EUVL reticles and electrostatic chucks
Author(s):
Roxann L. Engelstad;
Kevin T. Turner;
Madhura Nataraju;
Jaewoong Sohn;
Andrew R. Mikkelson;
Venkata Siva Battula;
Pradeep Vukkadala;
Jacob R. Zeuske;
Chris K. Van Peski
Show Abstract
According to the International Technology Roadmap for Semiconductors, meeting the strict requirements on image
placement errors in the sub-45-nm regime may be one of the most difficult challenges for the industry. For Extreme
Ultraviolet Lithography (EUVL), the nonflatness of both the mask and chuck is critical as well, due to the
nontelecentric illumination during exposure. To address this issue, SEMI Standards P37 and P40 have established the
specifications on flatness for the EUVL mask substrate and electrostatic chuck. This study investigates the procedures
for implementing the Standards when measuring and characterizing the shapes of these surfaces. Finite element
simulations are used to demonstrate the difficulties in supporting the mask substrate, while ensuring that the measured
flatness is accurate. Additional modeling is performed to illustrate the most appropriate methods of characterizing the
nonflatness of the electrostatic chuck. The results presented will aid in identifying modifications and clarifications that
are needed in the Standards to facilitate the timely development of EUV lithography.
Recent performance of EUV mask blanks with low-thermal expansion glass substrates
Author(s):
Tsutomu Shoki;
Takeyuki Yamada;
Shouji Shimojima;
Yuuki Shiota;
Mitsuharu Tsukahara;
Kesahiro Koike;
Hiroaki Shishido;
Osamu Nozawa;
Toshiyuki Sakamoto;
Morio Hosoya
Show Abstract
A high flatness of 50 nm, zero defects at more than a size of 30 nm and a high reflectivity of more than 66% for
extreme ultraviolet (EUV) light are critical issues related to EUV mask blanks. In this paper, progress on these issues
and the recent performance of EUV blanks is reported. Steady progress in defect reduction was achieved in the past six
years by improving fabrication processes. When inspected by a Lasertec M1350, defect quality as low as 0.02
defects/cm2 at 70-nm sensitivity was demonstrated on a multilayer (ML) blank with a quartz (QZ) substrate. A QZ
substrate with a high flatness of around 90 nm peak-to-valley (P-V) on both sides and a high defect quality of 0.006
defects/cm2 at 60-nm sensitivity was obtained using a newly developed polishing process consisting of local polishing,
touch polishing and cleaning. The cleaning process was developed for low thermal expansion (LTE) glass to reduce the
defects associated with it. Using the cleaning process, the ULETM substrates showed defectivity similar to the QZ
substrates. An average flatness of 117 nm P-V, and best flatness of 84 nm P-V on the front side and 56 nm P-V on the
back side were obtained on ULE substrates using the new polishing process. Multilayer (ML) blanks with a high defect
quality of 0.08 defects/cm2 at 80-nm sensitivity were produced on a ULE substrate. The ML blanks, consisting of 50 bilayers,
have high peak reflectivity of more than 66% and excellent uniformity of less than 0.04 nm in centroid wavelength, which meets the desired specifications.
Investigation of resist effects on EUV mask defect printability
Author(s):
Zhiyu Zhang;
Ted Liang
Show Abstract
In this paper, we report our recent investigations into the effect of resist processing on defect printability.
Simulations are conducted using both aerial image threshold and resist models in an attempt to determine the effect of
the resist process. There is good agreement between the resist model simulation and the printing data obtained using the
EUV micro exposure tool (MET) and a programmed defect mask. The CD error, or defect printability, introduced by
edge defects on 70nm semi-iso lines predicted by the aerial image threshold model is larger than that by both the resist
model and the actual printing results. However, this favorable difference vanishes for edge defects on 30nm lines. Mask
error enhancement factor (MEEF) is used to understand the discrepancy between the aerial image threshold model and
the resist model. Image quality measured by normalized image log slope (NILS) and resist process window characterized
by exposure latitude are closely related to image MEEF and resist MEEF respectively, and ultimately determine defect
printability for a given patterning and resist processing. Defect printability increases exponentially as the feature size
shrinks. This nonlinear behavior presents a challenge for defining defect specifications for EUV lithography based on
extrapolations from currently available printing data.
Impact of mask absorber properties on printability in EUV lithography
Author(s):
Takashi Kamo;
Hajime Aoyama;
Toshihiko Tanaka;
Osamu Suga
Show Abstract
The impact of mask absorber properties on printability in EUV lithography was studied from the viewpoint of
lithographic requirements which can give high imaging contrast and reduce the shadowing effect. By using the
refractive indices of the elements and compounds employed as absorbers, their reflectivity on multilayer blanks, aerial
image on wafer plane and printed CDs depending on absorber thicknesses were simulated. This predicted an optimum
Ta-based absorber's thickness. Several patterned masks of LR-TaBN absorber with various thicknesses were prepared.
Each patterned mask was exposed with the newly developed small-field-exposure-tool (SFET). It was demonstrated
that optimized absorber thickness can, without loss of printability performance, reduce CD difference between
horizontal and vertical pattern that has been known to be caused by shadowing effect.
Capability of eco-friendly cleaning strategy corresponding to advanced technology
Author(s):
Sookyeong Jeong;
Dongwook Lee;
Jisun Ryu;
Jinho Ryu;
Sangpyo Kim;
Oscar Han
Show Abstract
In sub-60nm technology node, cleaning process becomes specialized to clear the defects without pattern damage as
decreasing critical particle size to control. While cleaning process has to meet the primary requisite, removal of particle
including organic residue and prevention of particle re-deposition, it should enable to suppress haze phenomena for a
long life of photomask. However, to solve the problem of haze, the chemical materials caused haze seed should be
hardly used and physical force becomes strengthen as the compensation for cleaning efficiency. Unfortunately it brings
about another problem, pattern damage seriously.
In this paper, adequate cleaning conditions which are applicable in sub-60nm technology node are evaluated to meet the
dilemma among three requirements, high cleaning efficiency, and prevention of pattern collapse, and prevention of haze
phenomenon. All cleaning steps in photomask process were set up using only 172nm UV irradiation for degradation of
organic contaminants and deionized water (DI) with acoustic power for particle lift-off. The effect of UV and DI
cleaning on cleaning efficiency and haze phenomena was derived from carrying out chemical and physical analysis
simultaneously. Also, we could quantify the statistical probability of pattern collapse in each of technology node and
layer shape as different condition of megasonic frequency and its power. As a result, it was known that this cleaning
process have various merits to make out dilemma mentioned above, if it satisfies optimized conditions.
Compositional analysis of progressive defects on a photomask
Author(s):
Koichiro Saga;
Hiroichi Kawahira
Show Abstract
Progressive mask defects are a critical mask-reliability issue in DUV lithography. It is well known that the
majority of the defects are ammonium sulfates. We have found using ToF-SIMS that metallic atoms are localized at
ammonium-sulfate defects on the mask surface, can influence the growth of the defects. Carbon compounds containing
nitrogen atoms are also localized at the some defects. These carbon compounds are the result of the adsorption of organic
volatiles outgassing from a reticle SMIF pod. Metal residues and organic contamination on a photomask as well as
airborne acidic and basic contamination must be controlled to avoid progressive defects on photomasks.
A practical solution to the critical problem of 193 nm reticle haze
Author(s):
Oleg Kishkovich;
Dave Halbmaier;
Xavier Gabarre;
Brian Grenon;
James Lo;
Andy Lam;
Tom Chen
Show Abstract
The authors have developed and successfully implemented a practical, yet effective solution to help eliminate haze
formation in the production fab. Based on a novel mechanism of haze formation described earlier, along with a
thorough understanding of the reticle surface chemistry changes during the manufacturing process, the authors
found an unexpectedly simple and straightforward way to prevent haze formation. This is possible regardless of the
origin of the reticle, by controlling the purity of the immediate reticle environment.
Rapid and precise monitor of reticle haze
Author(s):
Terrence Zavecz;
Bryan Kasprowicz
Show Abstract
Reticle Haze results from the deposition of a chemical residue of a reaction that is initiated by Deep Ultra Violet (DUV)
or higher frequency actinic radiation. Haze can form on the backside of the reticle, on the chrome side and on the pellicle
itself.
The most commonly reported effect of haze is a gradual loss in transmission of the reticle that results in a need to
increase the exposure-dose in order to maintain properly sized features. Since haze formation is non-uniform across the
reticle, transmission loss results in an increase in the Across Chip Linewidth Variation (ACLV) that is accompanied by a
corresponding reduction in the manufacturing process window. Haze continues to grow as the reticle is exposed to
additional low wavelength radiation through repeated use.
Early haze formation is a small-area phenomenon in comparison to the total area of the reticle and may initiate
simultaneously in separate areas. The early stages of reticle haze therefore results in a degradation of Best Focus, Depth
of Focus and the Exposure latitude of individual features in the "hazed" area prior to any noticeable large area
transmission loss. Production lots subject to reticle hazing on critical layers will experience a direct loss of lithographic
yields, loss of capacity, an increase in rework rates and an ultimate loss in overall final-test yield long before the need for
an overall image exposure-dose increase is detected.
Feature profiles and process response are degraded at the earliest stages of haze formation. While early hazing may occur
in a small area of the reticle, the area influenced by the initial deposition is relatively large in comparison to the size of
an individual circuit feature. A sampled metrological inspection of a regular array of points across the exposure field is
therefore able to detect any form of reticle haze if the analysis monitors the feature-profile response rather than simply
feature widths. A model-driven method for the early detection of reticle-haze using basic feature metrology is developed
in this study. Application results from a production reticle are used to demonstrate validation of the technique that
employs a highly accurate method of calculation of the uniformity of the reticle exposure-response for individual
features across the exposure.
Investigation of airborne molecular contamination adsorption rate as storage materials in mask
Author(s):
Chul-Kyu Yang;
Han-Sun Cha;
Sin-Ju Yang;
Ju-Hyun Kang;
Jin-Ho Ahn;
Kee-Soo Nam
Show Abstract
The haze issue has gradually increased in the 65 nm node technology and beyond. This issue has been reporting that it
is caused by chemical reaction among ions like SO42-, NH4+ and aromatic hydrocarbon compounds (AHCs) such as
butylated hydroxy toluene (BHT), toluene and etc. on mask by 193 nm laser in general. This haze growth causes defects
with accumulation of exposure energy. Finally, it decreases the lifetime of photomask with an increase in defects. The
source of this haze is generated from storage materials as well as chemical residue in the photomask process. Therefore,
we investigated the adsorption rate of airborne molecular contamination (AMC) on each layer with storage materials
which were assumed to be the source of the haze.
We analyzed adsorbed ions and volatile organic compounds (VOCs) on each layer to verify the effects of storage
materials for some storage periods by automatic thermal desorption gas chromatography/mass spectrometer (ATD
GC/MS) and ion chromatography (IC). Also, we investigated the contact angle of each layer as AMC concentration of
storage materials. From the experimental results, we confirmed that the adsorption rate of AMC was different on each
layer as storage materials.
Study of time dependent 193 nm reticle haze
Author(s):
Joseph Gordon;
Larry Frisa;
Christian Chovino;
David Chan;
John Keagy;
Colleen Weins
Show Abstract
While significant progress has been made in reducing the occurrence rate of progressive
defect growth on photomasks used at 193nm, the issue continues to be a problem for
many semiconductor fabs. Increasing evidence from multiple sources indicates that
further reduction in haze risk involves closely controlling the storage and exposure
environment of the photomask. Further controlled testing is necessary to characterize the
impact of environment and individual components on growth. In this way, photomask
users, equipment and material providers may be better prepared to ensure the proper
storage and use of photomasks in order to reduce the risk of haze growth.
In continuation of work previously reported by Toppan Photomasks, advanced test
apparatus, recently designed and built, now enables researchers to generate and maintain
stable and controlled levels of multiple impurities which potentially effect haze growth.
Supported by on-line and off-line analytical methods and instrumentation, new
experimental set-up enables accuracy in the testing and validation of the impacts of
environmental variables.
Different classes of pollutants in multiple combinations have been studied to more
precisely characterize environmental sensitivity of varying types of 193 nm reticles.
Authors report further on the study of the effect of environmental conditions on severity
and rate of haze formation to provide insight into the requirements for reducing or even
preventing such conditions.
Full sulfate-free process: joint achievement of minimal residual ions and yield improvement
Author(s):
Francesca Perissinotti;
Luca Sartelli;
Davide Cassago;
Hiroyuki Miyashita
Show Abstract
Reducing the amount of ionic residues coming from cleaning chemistry became necessary for photomask manufacturing
process in order to eliminate the major cause of haze. The achievement of this target involves using sulphate-free steps
from resist removal to final cleaning, maintaining good performances on particles or residues removal as well as
minimization of pattern damages and preservation of the substrate properties. In this paper the cleaning strategies for
high-end masks are discussed and a tight dependency on substrate and contamination type is highlighted as the major
aspect that influences the good performances for ozone-based technique. The data collected from both tests and real
production for sulfate-free cleaning show that the key point to achieve the full effectiveness is the careful definition of
the sequence of treatments and rinses, allowing also the minimization of pattern damages.
The cleaning capability of the full sulphate-free process is tested on various types of contaminants and the achieving of
excellent removal performance is demonstrated for contaminations of sizes down to 100nm. When the sulfate-free
cleaning is not fully effective, a pre-treatment is applied before the cleaning in order to reduce the interaction between
contamination and substrate, thus enlarging the removal capability of the ozone-based cleaning. The ion chromatography
confirms that the sulphate residues can be reduced below the threshold value for haze formation.
Using the AIMS 45-193i for hyper-NA imaging applications
Author(s):
Peter De Bisschop;
Vicky Philipsen;
Robert Birkner;
Ute Buttgereit;
Rigo Richter;
Thomas Scherübl
Show Abstract
We have tested the validity of the so-called 'vector-effect emulation mode' of the newest member of the AIMSTM
family, the AIMSTM45-193i, that was recently developed for Hyper-NA applications. This vector-effect emulation mode
(also called 'scanner mode') converts the measured signals into a prediction of what the image-in-resist of a Hyper-NA
scanner would be (so including vector- and polarization effects). We've done a number of experiments that directly test
the validity of this vector-effect emulation, by comparing them to rigorous lithographic simulations and to CD-measurements
from printed NA=1.20 scanner wafers, and found that the AIMSTM 45-193i results are in fact quite
accurate. Afterwards we looked at a number of potential Hyper-NA imaging applications for the AIMSTM 45-193i, again
comparing it to rigorous simulations and wafer CD-measurements. These results indicate that, next to its traditional use
as reticle-inspection tool, the AIMSTM 45-193i has potential use also in the wafer fab as an 'imaging-inspection' or
'OPC-defect inspection' tool, especially when applied to 2D patterns.
Mask characterization for double patterning lithography
Author(s):
Karsten Bubke;
Eric Cotte;
Jan Hendrik Peters;
Robert de Kruif;
Mircea Dusa;
Joerg Fochler;
Brid Connolly
Show Abstract
Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32nm node if high index
immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the
obvious drawbacks of additional exposure, processing steps and the resulting reduced throughput, DPT possesses a
number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the
wafer fab but also to mask performance and metrology. In this paper we will address the mask performance.
To characterize the mask performance in an actual DPT process, conventional parameters need to be re-evaluated.
Furthermore new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle
overlay but also to CD differences between masks of a DPT reticle set. A DPT target of reticle to reticle induced overlay
of 6nm, 3σ at mask level was proposed recently for the 32nm node. The results show that this target can be met.
Besides that, local CD variations and local displacement become critical. Finally, the actual mask metrology for
determination of these parameters might not be trivial and needs to be set up and characterized properly. In this paper
we report on the performance of two-reticle sets based on a design developed to study the impact of mask global and
local placement errors on a DPT dual line process.
In a first step we focus on reticle to reticle overlay. The overlay between two masks evaluated for different wafer
overlay targets is compared with measurements on actual resolution structures. In a second step, mask to mask CD
variations are addressed. Off-target CD differences as well as variations of CD signatures on both reticles of a set are
investigated. Finally, local CD variations and local displacements are examined. To this aim, local variations of adjacent
structures on the reticle are characterized. The contribution of local effects to the overall CD and registration budget is
estimated.
DPL performance analysis strategy with conventional workflow
Author(s):
Nobuhito Toyama;
Yuichi Inazuki;
Takanori Sutou;
Takaharu Nagai;
Yasutaka Morikawa;
Hiroshi Mohri;
Naoya Hayashi;
Junji Miyazaki;
Alek Chen;
Nandasiri Samarakone
Show Abstract
DPL (Double Patterning Lithography) has been in public as one of candidates for 45nm or 32nm HP since
ITRS2006update disclosed. A lot of report of the performances and issues regarding to DPL were published.
The current main concerns are evaluation of the infrastructures such as decomposition software, advanced
photomasks, higher-NA exposure tool and leading-edge hard-mask process. If there is simpler procedure to
evaluate DPL using a conventional environment without hard-mask process, the development of DPL will be
accelerated. Here, the simple evaluation procedure for DPL using actual photomasks combining double
exposure technique was proposed. The pseudo DPL result in terms of mask CD uniformity, image placement
and overlay were demonstrated. In this evaluation procedure, decomposition restriction, mask latitude and
fabrication load were also discussed
Estimating DPL photomask fabrication load compared with single exposure
Author(s):
Nobuhito Toyama;
Yuichi Inazuki;
Takanori Sutou;
Takaharu Nagai;
Yasutaka Morikawa;
Hiroshi Mohri;
Naoya Hayashi;
Judy A. Huckabay;
Yoshikuni Abe
Show Abstract
DPL (Double Patterning Lithography) has been identified as one of major candidates for 45nm and 32nm HP since
ITRS2006update and several reports of the performance or challenges of DPL have been published. DPL requires
at least two photomasks with tighter specification of image placement and the difference of mean to target
according to ITRS2006update. On the other hand, approximately half of whole features of single layer are written
on each photomask and the densest features are split into other photomask in consequence of pitch relaxation for
DPL. Then the photomask writing data of two sets for DPL and single data for single exposure are evaluated for
photomask fabrication load. The design will be automatically decomposed with EDA tool and OPC will be tuned
as DPL or single exposure. Not only number of fractured features but also feasibility study of automatic
decomposition will be presented and discussed. The consequences of relaxed pitch on process, inspection, repair,
yield, MEEF and cycle time will be discussed with results as available.
The MEEF NILS divergence for low k1 lithography
Author(s):
Richard Schenker;
Wen-hao Cheng;
Gary Allen
Show Abstract
For tight pitch patterning with sub-wavelength mask features, simulations and wafer data show that many mask stacks
that provide superior image contrast, can provide inferior MEEF performance. For example, 6% MoSi EPSM is found
to have higher MEEF than binary masks despite having better contrast and exposure latitude when equal lines and spaces
on the mask are used to pattern equal lines and spaces on the wafer. Likewise, the deposition of SiO2 on-top of the
chrome surface of a binary mask improves contrast but degrades MEEF compared to a binary mask. When contrast is
varied by mask stack or by print bias, MEEF is poorly correlated with contrast and often increases with increasing
contrast. The optimal print bias for exposure latitude is significantly different than the optimum print bias for MEEF.
MEEF, on the other hand, is highly correlated with the difference between maximum and minimum intensity when one
varies mask stack, print bias and illumination. Analytical MEEF equations are derived that support this strong
relationship between MEEF and the difference between maximum and minimum intensity.
Impact of alternative mask stacks on the imaging performance at NA 1.20 and above
Author(s):
Vicky Philipsen;
Kei Mesuda;
Peter De Bisschop;
Andreas Erdmann;
Giuseppe Citarella;
Peter Evanschitzky;
Robert Birkner;
Rigo Richter;
Thomas Scherübl
Show Abstract
The lithographic performance of current state-of-the-art resolution enhancement techniques (RET) will become critical at
hyper numerical aperture (NA>1) due to mask 3D effects. We have studied the impact of the mask material on the
lithographic performance at NA 1.2 and above. The assessment, both by rigorous simulations and experiments, involves
the standard mask stacks, Cr binary mask (BIM) and MoSi 6% attenuated phase shift mask (attPSM), as well as
alternatives such as thick Cr BIM, Ta/SiO2 1% and 6% attenuated PSM, and Ta/SiON 1% attenuated PSM.
Using the rigorous electro-magnetic field (EMF) and lithographic process simulations (IISB DrLiTHO) the mask
structure is optimized taking into account the trade_off with mask error enhancement factor (MEEF). Next, a throughpitch
evaluation of the 45nm half-pitch (HP) node at NA1.2-1.35 is carried out examining maximum exposure latitude
(EL), depth-of-focus (DOF), best focus shifts, and MEEF behavior for the various mask stacks.
For the validation of the simulation methodology a correlation is made between scanner (ASML XT:1700Fi), AIMS
(Zeiss AIMSTM45-193i), and simulation results indicating the importance of the mask quality and mask properties.
Based on the lithographic performance and the mask manufacturability we put together a ranking of the commercially
available mask stacks for the 45nm HP node at NA 1.2 and 1.35.
Requirements of photomask registration for the 45nm node and beyond: Is it possible?
Author(s):
Jin Choi;
Hee Bom Kim;
Sang Hee Lee;
Dong Hun Lee;
Hae Young Jeong;
Jeung Woo Lee;
Byung Gook Kim;
Sang-Gyun Woo;
Han Ku Cho
Show Abstract
As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration
becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required
to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce
registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle
attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite
element modeling and by experiment. Based on these results, we present the current status and the goal of each error for
the roadmap of sub-45 nm node.
Simulation of larger mask areas using the waveguide method with fast decomposition technique
Author(s):
Peter Evanschitzky;
Feng Shao;
Andreas Erdmann;
David Reibold
Show Abstract
A new and optimized waveguide based electromagnetic field solver with decomposition technique for rigorous optical
and extreme ultraviolet (EUV) mask near field simulations is presented. The model allows to perform full three
dimensional (full 3D) simulations as well as three dimensional simulations based on a decomposition technique (Q3D,
"Q" means "quasi"). After a short introduction of the waveguide method the decomposition technique is presented.
Subsequently the capabilities of the new electromagnetic field solver are demonstrated exemplarily based on state-of-the-art
optical and EUV systems. The simulation of larger mask areas and the fast simulation of standard sized mask areas is
shown. A comparison between the full 3D and the Q3D approach demonstrates the field of application of the
decomposition technique.
Polarization aberration modeling via Jones matrix in the context of OPC
Author(s):
Qiaolin Zhang;
Hua Song;
Kevin Lucas
Show Abstract
The increasingly stringent demand for shrinkage of IC device dimensions has been pushing the development of new
resolution enhancement technologies in micro-lithography. High NA and Ultra-High NA (NA>1.0) applications for low
k1 imaging strongly demand the adoption of polarized illumination as a resolution enhancement technology since
proper illumination polarization configuration can greatly improve the image contrast hence pattern printing fidelity.
For polarized illumination to be fully effective, ideally all the components in the optical system should not alter the
polarization state during propagation from illuminator to wafer surface. In current OPC modeling tools, it is typically
assumed that the amplitude and polarization state of the electric field do not change as it passes through the projection
lens pupil. However, in reality, the projection lens pupil of the scanner does change the amplitude and the polarization
state to some extent, and ignorance of projection pupil induced polarization state and amplitude changes may cause CD
errors which are un-tolerable at the 45nm device generation and beyond.
We developed an OPC-deployable modeling approach to model polarization aberration imposed by the projection lens
pupil via Jones matrix format. This polarization aberration modeling capability has been integrated into the Synopsys
OPC modeling tool, ProGen, and its accuracy and efficiency have been validated by comparing with an industry
standard lithography simulator SolidE. Our OPC simulations show that the impact of projection lens pupil polarization
aberrations on optical proximity effect (OPE) could be as large as several nanometers, which is not negligible given the
extremely stringent CD error budget at 45nm node and beyond. This modeling approach is applicable to arbitrary
polarization aberrations imposed by any components in the lithography system that can be characterized in Jones matrix
format.
Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better approximation to
the physical scanner pupil, we propose a more physics-centric methodology to evaluate the optical model accuracy of
OPC simulator.
Validation of a fast and accurate 3D mask model for SRAF printability analysis at 32nm node
Author(s):
Peng Liu;
Christian Zuniga;
Zhongtuan Ma;
Hanying Feng
Show Abstract
The accuracy of a fast 3D thick mask model is evaluated for 6% AttPSM having sub-resolution assist features (SRAF).
The main features and SRAFs are designed to print 40nm lines or spaces on wafer (k1~0.28) through pitch from 100nm
to 500nm. The resulting optimum SRAF sizes vary from 10nm to 48nm depending on the main feature pitch, mask tone
and illuminator shape. The model accuracy is evaluated on both main feature CDs and SRAF side lobe intensities by
comparing with a rigorous model. The fast 3D model shows improvements in both areas over thin mask model,
particularly in SRAF printability prediction.
Fast three-dimensional simulation of buried EUV mask defect interaction with absorber features
Author(s):
Chris H. Clifford;
Andrew R. Neureuther
Show Abstract
To simulate the interaction of buried defects and absorber features in EUV masks, a full three-dimensional, fast,
integrated, simulator based on ray tracing and a thin mask model is presented. This simulator allows rapid assessment of
the effects of buried defects on EUV printing. This new simulator, RADICAL (Rapid Absorber Defect Interaction
Computation for Advanced Lithography), gives a 450X speed increase compared to FDTD, and matches FDTD within 1.5nm for predicting CD change due to a buried defect. RADICAL consists of three sequential steps: the propagation of the mask illumination down through the absorber pattern, the reflection off the defective multilayer, and the propagation back up through the absorber. A propagated thin mask model is used to model the down/up propagation through the
absorber pattern and a ray tracing simulator is used for the multilayer reflection. These simulators are linked together
using a Fourier transform to convert the near field output of one simulator step into a set of plane wave inputs for the next.
Polarization-induced astigmatism caused by topographic masks
Author(s):
Johannes Ruoff V.D.M.;
Jens Timo Neumann;
Emil Schmitt-Weaver;
Eelco van Setten;
Nicolas le Masson;
Chris Progler;
Bernd Geh
Show Abstract
With the continuous shrink of feature sizes the pitch of the mask comes closer to the wave length of light.
It has been recognized that in this case polarization effects of the mask become much more pronounced and
deviations in the diffraction efficiencies from the well-known Kirchhoff approach can no longer be neglected.
It is not only the diffraction efficiencies that become polarization-dependent, also the phases of the diffracted
orders tend to deviate from Kirchhoff theory when calculated rigorously. This also happens for large structures,
where these phase deviations can mimic polarization dependent wave front aberrations, which in the case of
polarized illumination can lead to non-negligible focus shifts that depend on the orientation and the features
size themselves. This orientation dependence results in a polarization induced astigmatism offset, which can be
of the same order of magnitude or even larger as polarization effects stemming from the lens itself. Hence, for
correctly predicting polarization induced astigmatism offsets, one has to both consider lens and mask effects at
the same time. In this paper we present a comprehensive study of polarized induced phase effects of topographic
masks and develop a simple theoretical model that accurately describes the observed effects.
Characterization and monitoring of photomask edge effects
Author(s):
Marshal A. Miller;
Andrew R. Neureuther;
Daniel P. Ceperley;
Juliet Rubinstein
Show Abstract
An experimental technique for quantitatively characterizing edge effect contributions in transmission through thick
photomasks is described and evaluated through electromagnetic simulation. The technique consists of comparing the 0th
order transmission for various duty cycles to the expected experimental behavior from a thin mask model. The real
electric field component from the edges is proportional to the shift in the position of the minimum energy in the 0th order
field away from the expected thin mask location. The square root of the minimum 0th order diffraction energy
normalized to a clear mask gives the imaginary edge contribution. The results indicate that Alternating Phase Shifting
Masks (ALT-PSM) and Attenuating Phase Shifting Masks (ATT-PSM) technologies have significant edge effects on the
order of 0.1λ to 0.2λ per edge respectively, as well as polarization dependence. For periods of 2 wavelengths and larger
these edge contribution values are nearly independent of pitch. The existence of an imaginary (or quadrature) phase
component is shown to result in an additive linear variation of line edge shortening through focus. This tilt can be
interpreted as a focus shift of the normal parabolic behavior and is about 0.5 Rayleigh units (RU). This focus shift
depends to some extent on the surrounding layout as well as the feature itself.
EMF simulations of isolated and periodic 3D photomask patterns
Author(s):
Sven Burger;
Lin Zschiedrich;
Frank Schmidt;
Roderick Köhle;
Bernd Küchler;
Christoph Nölscher
Show Abstract
We present rigorous 3D EMF simulations of isolated features on photomasks using a newly developed finite-element
method. We report on the current status of the finite-element solver JCMsuite, incorporating higher-order
edge elements, adaptive refinement methods, and fast solution algorithms. We demonstrate that rigorous
and accurate results on light scattering off isolated features can be achived at relatively low computational cost,
compared to the standard approach of simulations on large-pitch, periodic computational domains.
Fast and accurate laser bandwidth modeling of optical proximity effects
Author(s):
Ivan Lalovic;
Oleg Kritsun;
Joeseph Bendik;
Mark Smith;
Chris Sallee;
Nigel Farrar
Show Abstract
In this work, we model the effects of excimer laser bandwidth on optical proximity effects in high-NA ArF dry and immersion lithography. We quantify the errors introduced by using common
approximation methods for the laser spectrum, such as the modified Lorentzian and Gaussian forms.
Although these approximations are simple to use, and their symmetry properties can lead to reduced
simulation run-times, they typically induce significant CD error when compared to the use of measured
spectral profiles, which are obtained from high-resolution spectrophotometry. In this paper we establish
some accuracy benchmarks and demonstrate the need for inclusion of information about the spectral
profile - for the laser type of interest - in order to achieve sub-nanometer image calculation accuracy
required for optical proximity correction. We further assess the speed-accuracy tradeoffs in terms of data
truncation and sampling, and propose some practical limits for sampling the illumination spectrum.
Additionally, in this work, we propose a new physically-based spectrum approximation method,
which significantly reduces computation time at a cost of less than 0.25nm residual image-CD error from
the fully-sampled image calculation. In addition to aerial image, we compare 45nm-node calibrated resist
models and latent image results for 0.92NA dry and 1.2NA immersion processes using measured
illumination profiles and lens aberrations. Finally, we consider the laser bandwidth sensitivity of 2D line-end
patterns and typical post-OPC designs for a logic gate-process.
Advanced mask particle cleaning solutions
Author(s):
Tod Robinson;
Andrew Dinsdale;
Ron Bozak;
Bernie Arruza
Show Abstract
The majority of trends in lithography technology necessitate the use of smaller, higher aspect, patterns on
photomasks which are increasingly sensitive to traditional cleaning processes. Particle defects are of increasing
concern since, in deep and even overhanging structures, they can become fixed to the surface with such strength
that any traditional cleaning technique would destroy any small, high-aspect, mask structures. A series of
advanced new solutions are presented here which have been shown to remove these types of problem particles as
applied to 45 nm node nanomachining mask repair with a RAVE nm450 system. In the first method, a cryogenic
cleaning system is modified to greatly enhance selective removal of nanoparticles from high aspect structures. In
the second method, the nm450 repair tool itself is applied to selectively remove targeted particles from a nanoscale
area of the mask surface thus only affecting the region of interest and not touching any sensitive surrounding
surfaces or structures.
Integrated photomask defect printability check, mask repair, and repair validation procedure for phase-shifting masks for the 45-nm node and beyond
Author(s):
Christian Ehrlich;
Ute Buttgereit;
Klaus Boehm;
Thomas Scheruebl;
Klaus Edinger;
Tristan Bret
Show Abstract
The decreasing feature sizes as induced by the ITRS have a growing impact on the cost of current and future
photolithographic masks. The assessment, repair and repair validation of these expensive masks has become a very
substantial factor of the total mask production cost. The introduction of immersion lithography and the proposed
introduction of double exposure strategies will further amplify this trend. In order to make the whole procedure more
manageable in a production environment, with its constraints on timing and resource allocation, a seamless workflow of
the repair and validation procedure is sought. A proposed way to achieve this is the set up of a dedicated tool set with a
backbone infrastructure designed for this workflow as well as for the specific high resolution task. In this paper we
concentrate on masks with feature sizes relevant for the 45nm node and defects with typical size and shape as they
appear in production. Phase shifting masks with synthetic defects have been manufactured and the printability of the
defects is analyzed with an AIMSTM45-193i. In part the defect outline and three-dimensional shape as well as further
characteristics have been visualized with an electron microscope, prior to repairing them with an electron beam based
repair system. In addition we will show the behaviour of the phase of the mask in a region of interest, that is in this case
the repair area and its immediate vicinity. This will be done by a special new tool, named Phame®, developed for
measuring the actual phase of smallest mask features with a high spatial resolution.
In the conclusion we will give an outlook how the proposed workflow and the how the employed technologies will
influence the masks that are expected to emerge for the 32nm node.
A semi-automated AFM photomask repair process for manufacturing application using SPR6300
Author(s):
Mario Dellagiovanna;
Hidenori Yoshioka;
Hiroyuki Miyashita;
Shiaki Murai;
Takuya Nakaue;
Osamu Takaoka;
Atsushi Uemoto;
Syuichi Kikuchi;
Ryoji Hagiwara;
Stephane Benard
Show Abstract
For almost a decade Nanomachining application has been studied and developed to repair next generation of
photomasks. This technique, based on Atomic Force Microscopy (AFM), applies a mechanical removing of the defects
with almost negligible quartz-damage, high accuracy of the edge-placement and without spurious depositions (stain,
implanted elements, etc.) that may affect the optical transmission. SII NanoTechnology Inc. (SIINT) is carrying out a
joint-development project with DNP Photomask Europe S.p.A. (DPE) that has allowed the installation in DPE of the
next generation state-of-the-art AFM based system SPR6300 to meet the repair specifications for the 65 nm Node.
Drift phenomena of the AFM probe represent one of the major obstacles for whichever kind of nano-manipulation
(imaging and material or pattern modification). AFM drift undermines the repeatability and accuracy performances of
the process. The repair methodology, called NewDLock, implemented on SPR6300, is a semi-automated procedure by
which the drift amount, regardless of its origin, is estimated in advance and compensated during the process. Now AFM
Nanomachining approach is going to reveal properties of repeatability and user-friendly utilization that make it suitable
for the production environment.
Repairing 45 nm node defects through nano-machining
Author(s):
Roy White;
Andrew Dinsdale;
Tod Robinson;
David Brinkley;
Jeffrey Csuy;
David Lee
Show Abstract
Recently questions have been raised about whether high aspect ratio (HAR) NanoBitsTM can be effectively utilized to
repair extension defects in 45 nm node and beyond. The primary concern has been how the effect of NanoBitTM
deflection impacts edge placement, sidewall angle and z-depth control repeatability. Higher aspect ratio bits are required
for defects that arise as mask feature sizes become smaller. As the aspect ratio of the NanoBitTM continues to increase to
meet these demands, the cross sectional area of the bit used for nanomachining becomes thinner and more susceptible to
bending under the forces applied during the nanomachining process. This is especially true when deeper features that
require HAR NanoBitsTM are being repaired. To overcome this trend RAVE LLC has developed a new repair process
that utilizes the strength of the bit shape. Repair of 45 nm node defects that require HAR NanoBitsTM will be
demonstrated using a new repair process and cantilever design.
The cleaning effects of mask aerial image after FIB repair in sub-80nm node
Author(s):
Hyemi Lee;
Goomin Jeong;
Sookyeong Jeong;
Sangchul Kim;
Oscar Han
Show Abstract
The Aerial Image Measurement Tool (AIMS) can estimate the wafer printability without exposure to wafer by using
scanner. Since measured aerial images are similar with wafer prints, using AIMS becomes normal for verifying issue
points of a mask. Also because mask design rule continues to shrink, defects and CD uniformity are at issues as factors
decreasing mask yield. Occurred defects on a mask are removed by existing mask repair techniques such as
nanomachining, electron beam and focused ion beam. But damages and contaminants by chemical and physical action
are found on the mask surface and contaminants above special size lead to defects on a wafer. So cleaning has been
necessary after repair process and detergency has been important. Before AIMS measurement, cleaning is done to make
same condition with shipped mask, which method brings repeated process - repair and cleaning - if aerial image was
not usual.
So cleaning effect after the FIB repair is tested by using the AIMS to find the optimized process minimizing the
repeated process and to get similar scanner results. First, programmed defect mask that includes various defect size and
type is manufactured on some kinds of patterns in DRAM device and sub-80nm tech. Next the defects on the
programmed mask are repaired by FIB repair machine. And aerial images are compared after the chemical cleaning,
non-chemical cleaning and without cleaning.
Finally, approximate aerial images to scanner results are taken regardless of cleaning process. It means that residue
originated from repair process doesn't affect aerial images and flexible process is possible between AIMS, repair and
cleaning process. But as the effect of minute particles and contaminations will be increased if pattern size is much
smaller, it needs to reconfirm the effect below the sub-60nm in DRAM device.
Wafer inspection as alternative approach to mask defect qualification
Author(s):
Christian Holfeld;
Frank Katzwinkel;
Uwe Seifert;
Andreas Mothes;
Jan Hendrik Peters
Show Abstract
Defect inspection is one of the major challenges in the manufacturing process of photomasks. The absence of any
printing defect on patterned mask is an ultimate requirement for the mask shop, and an increasing effort is spent in order
to detect and subsequently eliminate these defects. Current DUV inspection tools use wavelengths five times or more
larger than the critical defect size on advanced photomasks. This makes the inspectability of high-end mask patterns
(including strong OPC and small SRAF's) and sufficient defect sensitivity a real challenge. The paper evaluates the
feasibility of inspecting the printed wafer as an alternative way for the high-sensitivity defect inspection of photomasks.
Defects originating in the mask can efficiently be filtered as repeated defects in the various dies on wafer. Using a
programmed-defect mask of 65-nm technology, a reliable detection of the printing defects was achieved with an
optimized inspection process. These defects could successfully be traced back to the photomask in a semi-automated
process in order to enable a following repair step. This study shows that wafer inspection is able to provide a full defect
qualification of advanced photomasks with the specific advantage of assessing the actual printability of arbitrary defects.
A pragmatic approach to high sensitivity defect inspection in the presence of mask process variability
Author(s):
Sang Hoon Han;
Jin Hyung Park;
Dong Hoon Chung;
Sang-Gyun Woo;
Han Ku Cho;
David Kim;
Chunlin Chen;
Ki-Hun Park;
Gregg Inderhees
Show Abstract
As design rules continue to shrink towards 4x nm, there are increase usage of aggressive Optical Proximity Correction
(OPC) in reticle manufacturing. One of the most challenging aggressive OPCs is Sub Resolution Assist Feature (SRAF)
such as scattering and anti-scattering bars typically used to overlap isolated and dense feature process windows. These
SRAF features are sub-resolution in that these features intentionally do not resolve on the printed wafer. Many reticle
manufacturers struggle to write these SRAFs with consistent edge quality even the most advanced E-Beam writers and
processes due to resolution limitations. Consequently, this inconsistent writing gives reticle inspection
challenges. Large numbers of such nuisance defects can dominate the inspection and impose an extraordinarily high
burden on the operator reviewing these defects. One method to work around inconsistent assist feature edge quality or
line-end shortening is to adjust the mask inspection system so that there is a substantial sensitivity decrease in order to
achieve good inspectability, which then compromises the sensitivity for the defects on main geometries.
Modern defect inspection tools offer multiple modes of operation that can be effectively applied to optimize defect
sensitivity in the presence of SRAF feature variability. This paper presents the results of an evaluation of advance
inspection methods and modes such as die to database selective thinline desense, transmitted & reflected light
inspections, review system and die to die selective desense to increase inspectability and usable sensitivity using
challenging production and R&D masks.
Key learnings are discussed.
Sensitivity comparison of fast integrated die-to-die T+R pattern inspection, standard database inspection, and STARlight2 contamination mode for application in mask production
Author(s):
Heiko Schmalfuss;
Thomas Schulmeyer;
Jan Heumann;
Michael Lang;
Jean-Paul Sier
Show Abstract
'Fast Integrated Die-to-Die T+R' pattern inspection (DDTR), reflected tritone database inspection (DBRt) and
STARlight2TM (SL2) contamination inspection are employed by mask makers in order to detect pattern defects and
contamination defects on photomasks for in process inspection steps.
In this paper we compare the detection capabilities of these modes on real production masks with a representative set of
contamination and pattern defects.
Currently, SL2 inspection is used to find contamination defects and die-to-die and die-to-database are used for pattern
defects. In this paper we will show that the new introduced 'Fast Integrated Die-to-Die T+R' pattern inspection
(DDTR)1 in combination with the DBRt can be used in production environment, instead of SL2 without any loss in the
sensitivity.
During the study, we collected and analyzed inspection data on critical layers such as lines & spaces and contact holes.
Besides, performance of the modes on product plates characterization was done using a test mask with programmed
defects.
Enhancing productivity and sensitivity in mask production via a fast integrated die-to-database T+R inspection
Author(s):
Eric Haodong Lu;
David Wu;
Ellison Chen;
Raj Badoni
Show Abstract
Inspection strategies of transmitted die-to-database pattern inspection (DBT), reflected die-to-database inspection (DBR)
and STARlight2TM (SL2) contamination inspection are employed by mask makers in order to detect pattern defects and
contamination defects on photo-masks in process inspection steps and outgoing quality control (OQC). Currently, SL2
inspection is used to detect contamination defects while die-to-database inspections are used to detect pattern defects.
However, such inspection strategies need two passes to detect both pattern defects and contamination defects. In this
paper we introduce 'Fast Integrated Die-to-Database T+R' (Fast dbTR) and compare its detection capabilities and the
productivity to conventional standard detection modes, such as, DBT, DBR and SL2. Programmed reticles and
production reticles with pattern defects and contamination defects were used for comparative data collection.
During the study, we collected and analyzed inspection data on critical layers such as lines & spaces and contact holes.
Empirical data show that 'Fast dbTR' is able to cover the sensitivity required by DBT, DBR and SL2 to detect both
pattern defects and contamination defects in one single scan without any loss of productivity in production runs.
Progressive growth and hard defect disposition integrated system for 65nm and 45nm ArF immersion lithography
Author(s):
Gek Soon Chua;
Sia Kim Tan;
Byoung Il Choi;
Oi Yin Lee;
Jeong Soo Kim
Show Abstract
In this paper, a defect disposition integrated system for progressive growth and hard defects has been proposed and
discussed for 65 nm and 45 nm immersion lithography. Pre-programmed hard defects on mask with minimum defect size
of 60 nm are studied. These mask defects are scanned by STARlight inspection with pixel size P90 for mask defect
capturing. Aerial Image Measurement System (AIMS) and printed photoresist features are used for modeling. Line,
space and hole in both bright and dark field are used for model setup. Printability for these programmed mask defects is
determined from process critical dimension (CD) variability. Experimental wafer results on the programmed defect mask
are obtained using 193 nm immersion tool with effective NA of 1.2 imaging lens. The resist CDs response to the mask
defect area are measured under the different exposure dose or focus. The correlation of AIMS CD, simulated CD and
wafer CD for different defect types and sizes to printability is performed. Scan result of progressive growth defects are
captured and verification of its printability using AIMS and Automated Mask Defect Disposition (AMDD) from KLATencor
is obtained.
Characterizing contamination inspection capabilities using programmed defect test reticles
Author(s):
Anthony Nhiev;
John Riddick;
Joseph Straub;
Trent Hutchinson;
Bryan Reese;
Aditya Dayal
Show Abstract
The ORIONTM series of test reticles have been used for many years as the photomask industry standard for evaluating contamination inspection algorithms. The deposition of Polystyrene Latex (PSL) spheres on various reticle pattern
designs allow STARlightTM tool owners to measure the relative contamination inspection performance in a consistent and quantifiable manner. However, with recent inspection technology advances such as shorter laser (light source)
wavelengths and smaller inspection pixels, PSL spheres were observed to physically degrade over relatively short time
periods: especially for the smallest sized spheres used to characterize contamination inspection performance at the most
advanced technology nodes.
Investigations into using alternative materials or methods that address the issue of PSL shrinkage have not yet proven
completely successful. Problems such as failure to properly adhere to reticle surfaces or identification of materials that
can produce consistent and predictable sphere sizes for the reliable manufacture of these critical test masks are only some
of the challenges that must be solved. Even if these and other criteria are met, the final substance must appear to
inspection optics as pseudo soft defects which resemble actual contamination that inevitably appears on production
reticle surfaces.
In the interim, programmed pindot defects present in the quartz region of the SPICATM test reticle are being used to characterize contamination performance while a suitable long-term solution to address the issue of shrinking PSL
spheres on ORION masks can be found. This paper examines the results of a programmed pindot test reticle specifically
designed to evaluate contamination algorithms without the deposition of PSL spheres or similar structures. This
alternative programmed pindot test reticle uses various background patterns similar to the ORION, however, it also
includes multiple defects sizes and locations making it more desirable than the limited range of defects found on the
SPICA.
Mask inspection method for 45nm node device
Author(s):
Sunghyun Oh;
Yongkyoo Choi;
Daeho Hwang;
Goomin Jeong;
Oscar Han
Show Abstract
Sensitivity of newly developed photo mask inspection tool with reflective optic was evaluated for 45nm DRAM device.
To get the required defect sensitivity of mask, printability of mask defect on wafer were simulated using in house
simulation tool. Simulation results were compared with inspection results. Characteristic and sensitivity comparison
between conventional transmissive and reflective optic tools were evaluated for several types of mask layer of 45nm and
55nm DRAM according to pixel size of detector of inspection tools. This reflective optic with short working distance
was equivalent in sensitivity to transmissive optic tool. Mask for 45nm DRAM can be qualified by current status of the
art inspection tools.
Inspection results for 32nm logic and sub-50nm half-pitch memory reticles using the TeraScanHR
Author(s):
Jean-Paul Sier;
William Broadbent;
Farzin Mirzaagha;
Paul Yu
Show Abstract
Results from the recently available TeraScanHR reticle inspection system were published in early 2007. These
results showed excellent inspection capability for 45nm logic and 5xnm half-pitch memory advanced production
reticles, thus meeting the industry need for the mid-2007 start of production. The system has been in production use
since that time. In early 2007, some evidence was shown of capability to inspect reticles for the next nodes, 32nm
logic and sub-50nm half-pitch memory, but the results were incomplete due to the limited availability of such
reticles. However, more of these advanced reticles have become available since that time. Inspection results of
these advanced reticles from various leading edge reticle manufacturers using the TeraScanHR are shown. These
results indicate that the system has the capability to provide the needed inspection sensitivity for continued
development work to support the industry roadmap.
Automatic optimization of MEEF-driven defect disposition for contamination inspection challenges
Author(s):
Tracy Huang;
Aditya Dayal;
Kaustuve Bhattacharyya;
Joe Huang;
William Chou;
Yung-Feng Cheng;
Shih-Ming Yen;
James Cheng;
Peter Peng
Show Abstract
Ever-tightened design rules and ensuing aggressive OPC features pose significant challenges for wafer fabs in the pursuit
of compelling yield and productivity. The introduction of advanced reticles considerably augments the mask error
enhancement factor (MEEF) where progressive defects or haze, induced by repeated laser exposure, continue to be a
source of reticle degradation threatening device yield. High resolution reticle inspection now emerges as a rescue venue
for wafer fabs to assure their photomask integrity during intensive deep UV exposure. Integrated in the high resolution
reticle inspection, a MEEF-driven lithographic detector "Litho3" can be used run-time to group critical defects into a
single bin. Previous investigations evinced that critical defects identified by such detector were directly correlated with
defects printed on wafer, upon which fab users can make cogent decisions towards reticle disposition and cleaning
therefore reduce cycle time.
One of the challenges of implementing such detector resides in the lengthy set up of user-defined parameters, from
practitioner standpoint, can considerably extend reticle inspection time and inevitably delay production. To overcome
this, an automatic simulation program has been written to optimize Litho3 settings based off a pre-inspection in which
only default Litho3 values are needed. Upon completion of the pre-inspection, the images are then scanned and
processed to extract the optimal Litho3 parameters that are largely dependent upon the feature size characteristics and
local MEEF. Thus optimized Litho3 parameters can then be input into the recipe set up to enable a real-time inspection,
as such fab user can timely access the defect criticality information for subsequent defect disposition. In the interest of
printability validation, such defect information and associated coordinates can be passed onto defect review via XLINK
for further analysis. Corresponding MEEF values are also available for all identified critical defects. Through this
automatic program the set up time for Litho3 can be reduced by up to 90%.
For high capacity production fabs running a pre-inspection is deemed infeasible; this automatic optimization program
can also serve as a direct interpretation of any regular reticle inspection even without invoking Litho3 set up, yet in the
end provide output in the context of defect criticality. Results acquired from this program were found in good accordance
with those from the real-time Litho3 inspection, for both critical and non-critical layers of 90 nm design node. Such
capability allows detailed study of defect criticality in relation to its size, defect optical transmittance, residing surface,
its proximity to a printing pattern as well as lithography parameters such as NA and sigma. Furthermore, coupling this
automatic program with high resolution inspection also assists in determining lithography process window and an indepth
comprehension of defect progression mechanism.
Paving the way to a full chip gate level double patterning application
Author(s):
Henning Haffner;
Jason Meiring;
Zachary Baum;
Scott Halle
Show Abstract
Double patterning lithography processes can offer significant yield enhancement for challenging circuit designs. Many
decomposition (i.e. the process of dividing the layout design into first and second exposures) techniques are possible, but
the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first
exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g.
dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist
features" or PrAFs) are designed to support the process window of critical features much like the role of the subresolution
assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more
design options, and hence a greater process and decomposition parameter exploration space, than are available for
SRAFs.
A decomposition scheme using PRAFs was developed for a gate level process. A critical driver of the work was to
deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single exposure process
while providing support for a larger range of critical features. A variety of PRAF techniques were investigated by
simulation, with a PrAF scheme similar to standard SRAF rules being chosen as the optimal solution [1].
This paper discusses aspects of the code development for an automated PrAF generation and placement scheme and the
subsequent decomposition of a layout into two mask levels. While PrAF placement and decomposition is straightforward
for layouts with pitch and orientation restrictions, it becomes rather complex for unrestricted layout styles. Because this
higher complexity yields more irregularly shaped PrAFs, mask making becomes another critical driver of the optimum
placement and clean-up strategies. Examples are given of how those challenges are met or can be successfully
circumvented. During subsequent decomposition of the PrAF-enhanced layout into two independent mask levels, various
geometric decomposition parameters have to be considered. As an example, the removal of PrAFs has to be guaranteed
by a minimum required overlap of the cut mask opening past any PrAF edge. It is discussed that process assumptions
such as CD tolerances and overlay as well as inter-level relationship ground rules need to be considered to successfully
optimize the final decomposition scheme. Furthermore, simulation and experimental results regarding not only ACLV
but also across-device linewidth variation (ADLV) are analyzed.
Automatic assist feature placement optimization based on process-variability reduction
Author(s):
Srividya Jayaram;
Ayman Yehia;
Mohamed Bahnas;
Hesham A. Maaty Omar;
Zeki Bozkus;
John L. Sturtevant
Show Abstract
To maximize the process window and CD control of main features, sizing and placement rules for sub-resolution assist
features (SRAF) need to be optimized, subject to the constraint that the SRAFs not print through the process window.
With continuously shrinking target dimensions, generation of traditional rule-based SRAFs is becoming an expensive
process in terms of time, cost and complexity. This has created an interest in other rule optimization methodologies, such
as image contrast and other edge- and image-based objective functions.
In this paper, we propose using an automated model-based flow to obtain the optimal SRAF insertion rules for a design
and reduce the time and effort required to define the best rules. In this automated flow, SRAF placement is optimized by
iteratively generating the space-width rules and assessing their performance against process variability metrics. Multiple
metrics are used in the flow. Process variability (PV) band thickness is a good indicator of the process window
enhancement. Depth of focus (DOF), the total range of focus that can be tolerated, is also a highly descriptive metric for
the effectiveness of the sizing and placement rules generated. Finally, scatter bar (SB) printing margin calculations
assess the allowed exposure range that prevents scatter bars from printing on the wafer.
Full-chip-based subresolution assist features correction for mask manufacturing
Author(s):
Ju-Mi Bang;
Issei Masumoto;
Min-Kyu Ji;
Sung-Hoon Jang;
Isao Aburatani;
Ji-Hyun Choi;
Sang-Gyun Woo;
Han-Ku Cho
Show Abstract
Sub Resolution Assist Features (SRAFs) are now the main option for enabling low-k1 photolithograpy. These technical challenges for the 45nm node, along with the insurmountable difficulties in EUV lithography, have driven the semiconductor mask-maker into the low-k1 lithography era under the pressure of ever shrinking feature sizes. Extending lithography towards lower k1 puts a strong demand on the resolution enhancement technique (RET), and better exposure tool. However, current mask making equipments and technologies are facing their limits. Particularly, due to smaller feature size, the critical dimension (CD) linearity of both main cell patterns and SRAFs on a mask is deviated from perfect condition differently. There are certain discrepancies of CD linearity from ideal case. For example, as the CD size gets smaller, the bigger CD discrepancy is to be.
There are many technologies, such as hard-mask process and negative-resist process and so on. One of them is an assist feature correction, which can be applied to achieve better CD control. In other words, in order to compensate this CD linearity deviation, the new correction algorithm with SRAFs is applied in data process flow. In this paper, we will describe in detail the implement of our study and present results on a full 65nm node with experimental data.
Etch proximity correction by integrated model-based retargeting and OPC flow
Author(s):
Shumay Shang;
Yuri Granik;
Martin Niehoff
Show Abstract
Model-based Optical Proximity Correction (OPC) usually takes into consideration optical and resist process
proximity effects. However, the etch bias proximity effect usually can not be completely eliminated by etch process
optimization only and needs to be compensated for in OPC flow for several critical layers. Since the understanding of
the etch process effect is getting better and accurate etch bias modeling is available now, lithographers start to migrate
from rule-based correction to model-based correction. Conventionally when etch bias is considered in model-based
correction, optical/resist/etch effect is corrected in one step by using the input layout as the final etch target. In this
paper, we proposed a new flow in which etch and optical/resist process effect are separated in both model calibration and
layout correction. This double separation allows easier control over etch and resist target, resulting in drastic reduction
of OPC runtime. In addition it enables post-OPC verification at both resist and etch level. Advantages of the new
integrated model-based retarget/OPC flow in RET implementation are also discussed.
Resolution enhancement by aerial image approximation with 2D-TCC
Author(s):
Kenji Yamazoe;
Yoshiyuki Sekine;
Miyoko Kawashima;
Manabu Hakko;
Tomomi Ono;
Tokuyuki Honda
Show Abstract
A newly developed sub-resolution assist feature (SRAF) placement technique with two-dimensional
transmission cross coefficient (2D-TCC) is described in this paper. In SRAF placement with 2D-TCC, Hopkins'
aerial image equation with four-dimensional TCC is decomposed into the sum of Fourier transforms of diffracted
light weighted by 2D-TCC, introducing an approximated aerial image so as to place SRAFs into a given reticle
layout. SRAFs are placed at peak positions of the approximated aerial image for enhanced resolution. Since the
approximated aerial image can handle the full optical model, SRAFs can be automatically optimized to the given
optical condition to generate the optimized reticle. The validity of this technique was confirmed by experiment
using a Canon FPA6000-ES6a, 248 nm with a numerical aperture (NA) of 0.86. A binary reticle optimized by this
technique with mild off-axis illumination was used in the experiment. Both isolated and dense 100 nm contacts (k1
= 0.35) were simultaneously resolved with the aid of this technique.
Exploring the sources of MEEF in contact SRAMs
Author(s):
Emily Gallagher;
Ian Stobert;
Masaru Higuchi;
Donald Samuels
Show Abstract
Optical Proximity Correction (OPC) relies on predictive modeling to achieve consistent wafer results. To that end,
understanding all sources of variation is essential to the successful implementation of OPC. This paper focuses on
challenging SRAM layouts of contacts to study the sources of wafer variation. A range of shape geometries and contact
configurations are studied. Contact shapes are no longer restricted to simple rectangles on the mask, some more complex
OPC outputs may include shapes like H's or T's or even more fragmented figures. The result is a large group of
parameters that can be measured at both mask and wafer level. The dependence of mask variation on geometry is studied
through the statistical distributions of parameter variations. The mask metrology output is expanded from traditional
linear dimensional measurements to include area, line edge roughness, corner rounding, and shape-to-shape metrics.
Wafer mask error enhancement factor (MEEF) is then calculated for the various contact geometries. This collection of
data makes it possible to study variation on many levels and determine the underlying source of wafer variations so that,
ultimately, they can be minimized.
The improvement of OPC accuracy and stability by the model parameters' analysis and optimization
Author(s):
No-Young Chung;
Woon-Hyuk Choi;
Sung-Ho Lee;
Sung-Il Kim;
Sun-Yong Lee
Show Abstract
The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to
meet the device performance and the process window latitude for the production level. The OPC model is generally
composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer
data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical
terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms
can deteriorate OPC stability in case of being overestimated by a small cost function.
Several physical terms have been used with ideal value in the optical property and even weren't be considered because
those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied
to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the
laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and
those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and
stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without
careful handling.
The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the
sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in
the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a
reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure
machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the
measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y
intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC
modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The
focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot
which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method.
Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source
and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into
the modeling.
With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device
node.
Simultaneous model-based main feature and SRAF optimization for 2D SRAF implementation to 32 nm critical layers
Author(s):
Ayman Yehia;
Alexander Tritchkov
Show Abstract
Sub-resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement
Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for
the optimum placement of 2D SRAF structures using state of the art Calibre RET flow. In this approach, the
optimal SRAF shapes are achieved simultaneously during the OPC step. The SRAF and main features are
optimized to account for their edge placement and process window metrics (aerial image slope/contrast, out of
focus/dose EPE, etc...). The resulting mask shapes deliver some of the properties that can be obtained using the
Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost
no impact on the runtime. The implemented model-based optimization flow remains compatible with the current
OPC production flows.
A generic technique for reducing OPC iteration: fast forward OPC
Author(s):
Le Hong;
John Sturtevant
Show Abstract
The drive toward advanced technology nodes has drastically increased the computational complexity of optical
proximity correction (OPC). Applying full-chip OPC to all critical layers has become the most computational demanding
step in the tape-out process. Tuning for fast and accurate OPC recipes is a critical step in the development of a total
manufacturing solution. OPC is by design an iterative cycle, where one iteration is a single simulation and polygon
fragmentation shift sequence. Typically an accurate OPC recipe requires eight or more iterations to converge to a final
best solution. The number of iterations in a recipe directly impacts the full-chip OPC runtime. Engineers often find
themselves spending hours tuning an OPC recipe to reduce just one iteration. This paper presents a generic technique
called Fast Forward OPC (FFOPC). FFOPC will help to reduce any golden OPC recipe that meets certain requirements
to a fixed 4 iterations with minimum accuracy lost. Most importantly this technique can be easily implemented as a plugin
with any existing OPC tools.
Fast synthesis of topographic mask effects based on rigorous solutions
Author(s):
Qiliang Yan;
Zhijie Deng;
James Shiely
Show Abstract
Topographic mask effects can no longer be ignored at technology nodes of 45 nm, 32 nm and beyond. As
feature sizes become comparable to the mask topographic dimensions and the exposure wavelength, the popular
thin mask model breaks down, because the mask transmission no longer follows the layout. A reliable mask
transmission function has to be derived from Maxwell equations. Unfortunately, rigorous solutions of Maxwell
equations are only manageable for limited field sizes, but impractical for full-chip optical proximity corrections
(OPC) due to the prohibitive runtime. Approximation algorithms are in demand to achieve a balance between
acceptable computation time and tolerable errors.
In this paper, a fast algorithm is proposed and demonstrated to model topographic mask effects for OPC
applications. The ProGen Topographic Mask (POTOMAC) model synthesizes the mask transmission functions
out of small-sized Maxwell solutions from a finite-difference-in-time-domain (FDTD) engine, an industry leading
rigorous simulator of topographic mask effect from SOLID-E. The integral framework presents a seamless solution
to the end user. Preliminary results indicate the overhead introduced by POTOMAC is contained within the same order of magnitude in comparison to the thin mask approach.
Improving hyper-NA OPC using targeted measurements for model parameter extraction
Author(s):
Brian S. Ward
Show Abstract
An alternative method of OPC model fitting based on model parameter sensitivity is presented. Theoretical advantages
are discussed, including improved model quality and time to results. The parameter sensitivity method is applied using a
basic optical model to 32nm logic node experimental data. Results include standard and parameter sensitivity model fits
using both constant and variable threshold models. The results show that the parameter sensitivity methodology enables
an overall model fit that is more physically-predictive than a standard OPC model fit.
Selective process aware OPC for memory device
Author(s):
Woosuk Shim;
Sungsoo Suh;
Frank Amoroso;
Robert Lugg;
Sooryung Lee;
Sukjoo Lee;
Seok-Hwan Oh;
Junghyeon Lee;
Tae-Hyuk Ahn;
Chang-Jin Kang
Show Abstract
Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The
repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay
issues while accuracy of first pattern is critical for the space technology. Both technologies
require improved model accuracy and process margin. Because of this, even traditionally noncritical
regions of a layout may contain process margin-limiting defects for double patterning
technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve
quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast
OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a
thorough check of the OPC results, including process window analysis. This determines which
points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas
limiting process margin. These advanced OPC techniques may include broader lithographic
analysis, field-based correction and process window consideration. Since advanced OPC
methods are only applied to part of the design, TAT is fast. TAT can be further improved by
treating critical regions differently. Critical regions will not be processed in the initial OPC or
intermediate verification steps, but will be corrected by the advanced OPC methods. This
methodology is called Incremental OPC as it applies the most appropriate OPC techniques to
each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution
assist feature printing can be eliminated prior to mask tape-out with minimal impact
to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which
must be applied across an entire pattern.
Validating optical proximity correction with models, masks, and wafers
Author(s):
Sajan Marokkey;
Edward W. Conrad;
Emily E. Gallagher;
Hidehiro Ikeda;
James A. Bruce;
Mark Lawliss
Show Abstract
Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC
models are used to convert input design shapes into mask data that often deviate significantly from both the initial design
and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections,
and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model
and this is done by invoking OPC verification programs. The verification models identify points of failure to specific
criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional
processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes
near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the
OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results,
there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level
and through OPC verification method. For each test case, five points in the process window space are chosen to provide
comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial
Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to
measurable metrics and provide an improved understanding of OPC verification validity.
The study of phase-angle and transmission specifications of 6% att-EAPSM for 90nm, 65nm, and 45nm node wafer manufacturing patterning process
Author(s):
Gong Chen;
Cesar Garza D.D.S.
Show Abstract
6% attenuated embedded PSM (att-EAPSM) has been widely used in semiconductor wafer
manufacturing industry at 130nm, 90nm, 65nm and 45nm nodes. To effectively use the 6% att-EAPSM
photomask technology and reduce its manufacturing costs, it is important for the industry to develop a
comprehensive mask specification that can fully meet the wafer level lithography requirements without
over-constraining the control parameters in 6% att-EAPSM manufacturing process. In this paper, we used
computer simulation software, Prolith by KLA-Tencor to study the impact of local phase-angle and
transmission errors to wafer lithography process. The simulation results indicated that phase-angle and
transmission errors result in a best focus plane shift, and hence reduce the common focus exposure window
across the mask. The data also indicated that as the NA (numerical aperture) of the lithography system
increases, the same amount of phase-angle error results less amount of focus shift. Based on this study and
the practical common focus windows in semiconductor industry, we proposed a new phase-angle and
transmission specification of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer process.
Better on wafer performance and mask manufacturability of contacts with no or non-traditional serifs
Author(s):
Donald Samuels;
Ian Stobert
Show Abstract
In the course of using Optical Proximity Correction (OPC) to optimize contact printing, the obvious solution is not
always the correct solution. This paper will explore two different types of contact layers, with two different sets of
objectives. In the first type of contact layer, the primary objective is to achieve consistent area uniformity. For these
designs, use of contacts without serifs over contacts with traditional corner serifs will result in a mask that has a lower
data volume input to the mask writer and an easier time in inspection and repair. We also show that on the wafer, this
simpler style of OPC will result in lower variation of area and CD. In second type of contact layer, there are additional
complicating factors over the first type of contact layer in that these mask designs include layouts with different sizes of
contacts that must be printed simultaneously. As contacts get pushed close together on corner to corner type spacing,
traditional serifs will be more likely to drive mask inspection issues and high mask error enhancement factor (meef). One
way to address this is with OPC that employs inverse serifs, with the center fragment of the rectangle pushed out and the
corners pushed in. This approach reduces meef and provides better image parameters for lower variability through
process window. However, this solution does not lend itself to very aggressive correction to achieve aggressive contact
aspect ratios. We compare these different OPC strategies (squares, traditional corner serifs and inverse corner serifs) and
describe the strengths and weaknesses of each approach.
Optimization of OPC runtime using efficient optical simulation
Author(s):
Mohamed Al-Imam;
Walid A. Tawfic
Show Abstract
Model-Based Optical Proximity Correction (MBOPC) is now found in nearly all resolution enhancement recipes
used in leading technology integrated circuit fabrication facilities. Many masks now have critical dimensions less
than the exposure wavelength, which results in light diffraction that distorts the image projected onto the wafer. The
industry is relying more and more on MBOPC to compensate for optical effects that are induced during the exposure
of these masks. The MBOPC operation is usually the highest computational time contributor in the RET flow.
MBOPC procedures include the fragmentation of layout edges longer than a specific value into a number of sub-edges
(fragments). The software engine can move and manipulate each fragment to improve the image transferred to
the wafer. In the sparse MBOPC approach, each fragment receives one or more optical simulation sites, which is a
one-dimensional array of points where light intensity is sampled and calculated. To correctly capture the resist
behavior at each simulation site, there must be enough points to ensure extension of the site to a certain distance
from the fragment. Adding more points beyond this distance does not add any benefit, but can significantly increase
the runtime.
This paper presents an automated method that analyzes layouts for different technology nodes that depend on sparse
simulations as their MBOPC engine, and reports the optimized number of simulation points that need to be in the
simulation site to get the desired accuracy and optimum runtime performance.
Full-chip process window aware OPC capability assessment
Author(s):
Robert Lugg;
Matt StJohn;
Yunqiang Zhang;
Amy Yang;
Paul Van Adrichem
Show Abstract
In the past technology generations, Optical Proximity Correction (OPC) has been applied using a model
capturing the Optical proximity effects in a single focal plane. In the newer generations, this method is more and
more difficult to maintain because of very small process windows in specific situations. These specific situations
include 1D configurations (e.g. isolated small lines) but increasingly complex 2D configurations.
In the more advanced technology nodes 2D configuration are starting to play a much bigger role. Process
windows need to be preserved in all cases, and so this brings about another challenge for the OPC flow. The more
traditional OPC approaches may result in un-acceptable small process window in such cases, whereas well
characterized Process Window aware OPC (PW-OPC) can provide better results, with much less engineering
interventions.
In this paper the method of Process Window aware OPC is applied on special designed test structures and on a
larger scale (full chip). Verifications and assessments are demonstrated and compared with alternatives. In the past
OPC engineers have been pushing for more and more design constraints in order to allow the OPC flow to be
successful. The PW-OPC approach is more adaptive compared with traditional single focal plane OPC, and can
still converge to an acceptable solution in complicated (unforeseen) layout configurations, without the need to
introduce complicated design constraints.
E-beam direct write is free
Author(s):
Lance A. Glasser
Show Abstract
In this paper we discuss four business concepts that will impact the adoption of e-beam direct write (EbDW). They are:
(1) The economically advantageous region for EbDW. At what costs and volumes EbDW is economically advantageous
is controlled by a two-sided constraint involving the cost of reticles on one hand and the cost of design on the other. (2)
The important role of product derivatives and other markets that can be satisfied by designs with heavy IP reuse. The
natural long tail in demand for differentiated products is today chopped off by the high costs of reticles. We show data
on the elasticity of the product derivative market with respect to certain costs. (3) That because reticle prices typically
decline at a 30% per year for the first few years after a new node is introduced, delaying the fabrication of that first reticle
set for a new product can save millions, more than paying for EbDW. The applicability of this technique is, however,
limited by the need for product requalifaction. (4) Finally, we introduce the business concept of the virtual reticle as a
possible component in EbDW pricing.
Driving photomask supplier quality through automation
Author(s):
Drew Russell;
Andrew Espenscheid
Show Abstract
In 2005, Freescale Semiconductor's newly centralized mask data prep organization (MSO) initiated a project
to develop an automated global quality validation system for photomasks delivered to Freescale
Semiconductor fabs. The system handles Certificate of Conformance (CofC) quality metric collection,
validation, reporting and an alert system for all photomasks shipped to Freescale fabs from all qualified
global suppliers. The completed system automatically collects 30+ quality metrics for each photomask
shipped. Other quality metrics are generated from the collected data and quality metric conformance is
automatically validated to specifications or control limits with failure alerts emailed to fab photomask and
mask data prep engineering. A quality data warehouse stores the data for future analysis, which is performed
quarterly. The improved access to data provided by the system has improved Freescale engineers' ability to
spot trends and opportunities for improvement with our suppliers' processes. This paper will review each
phase of the project, current system capabilities and quality system benefits for both our photomask suppliers
and Freescale.
Multi-layer reticle (MLR) strategy application to double-patterning/double-exposure for better overlay error control and mask cost reduction
Author(s):
Yasuhisa Yamamoto;
Rodney Rigby;
Jason Sweis
Show Abstract
Double-patterning lithography / double-exposure lithography is believed to be a solution in order to enable the
32nm-Half-Pitch (HP) and below process node until EUV lithography infrastructure is ready. However, one of the
biggest challenges is the overlay budget along with critical dimension (CD) control. In this paper, we propose that
instead of using multiple masks for the DPL (STD DPL), multiple split patterns are printed on a single mask so that each
pattern is separately or simultaneously exposed onto a wafer in order to reduce the mask-to-mask overlay error. This can
also reduce the mask cost and mask manufacturing time compared with STD DPL, at the expense of reducing
manufacturing throughput. We propose two ideas about how to place the split patterns in a single mask and simulate
corresponding shot throughput comparisons. The results show that by using multi-layer reticle (MLR) strategy for
splitting the original layout into 2 split patterns onto a single mask (Method I), we achieve: 1) reduction of the
mask-to-mask overlay error factor 2) use of a single mask (reducing mask costs) and 3) reduction of wafer shot
throughput to roughly 50% of that achieved by STD DPL. Also by using our new approach of placing multiple-split
patterns to form the arrays within the mask scribe (Method II), we achieve: 1) reduction of the mask-to-mask overlay
error factor 2) use of a single mask (reducing mask costs) and 3) drastically improved wafer shot throughput (at least
90% of the STD DPL, 180% of Method I).
Polygon-based compensation of proximity and density effects in photomask processes
Author(s):
Kiyoshi Kageyama;
Katsuyuki Miyoko;
Yoshimitsu Okuda;
Gökhan Perçin;
Apo Sezginer;
Jesus Carrero;
Alan Zhu;
Anwei Liu
Show Abstract
In recent years, mask critical dimension (CD) linearity and uniformity has become increasingly important. The ITRS roadmap shows the mask CD control requirements exceeding those of the wafer side beyond the 45nm node. Measurements show that there are systematic, uncorrected proximity effects even when a state-of-the-art proximity effect correction (PEC) algorithm is used. The uncorrected proximity effect is predictable with a computational model. The model for e-beam lithography and etch process contains terms to model short-range pattern density effects and plasma shadowing effect in Cr-etch. The model is calibrated using CD measurements on a test mask. The model is valid for arbitrary 2-D patterns. We present a model-based mask process compensation (MPC) method which applies geometric changes to polygons as in OPC. We discuss the goodness of model fit to the calibration data; verification of the calibrated model by SEM images; and the improvement obtained by MPC. The mask writing error, i.e. final inspection CD minus incoming database CD, was reduced by a factor of 2 through the use of MPC.
Improvement of mask CD uniformity for below 45-nm node technology
Author(s):
Hojune Lee;
Seokjong Bae;
Junghoon Park;
Dongseok Nam;
Byunggook Kim;
Sang-Gyun Woo;
HanKu Cho
Show Abstract
According to device shrinkage, pattern load, layout geometry and process induced critical dimension (CD) trend are the
most important factors deciding mask CD uniformity in a mask manufacturing process. The CD distribution is generally
divided by two categories - contribution of pattern load and process induced CD distribution. Etch bias uniformity on a
mask is one of the decisive contributors at a standpoint of pattern load. The signature of etch bias uniformity totally
depends on the pattern load in a mask. In a low pattern load, etch bias uniformity shows a radial signature which is
geometrically distributed regardless of pattern position. In a high pattern load, etch loading effect becomes dominant.
The pattern load, however, can have various definitions, which means that a criterion of low and high pattern load can be
obscure. Specific layouts which have same pattern load over mask but separated region of low and high load pattern in
one mask was designed to specify the effect of pattern load. The radial CD signature is mitigated as pattern load
increases locally. At the same time, etch loading trend grows and dominates total CD uniformity. The radial signature and
etch loading trend have inverse signs on central region which enables to compensate each signature. Therefore a specific
pattern load which can make etch bias uniformity minimized can exist. "Transition pattern load" is detected here. One
can use this specific pattern load as an indicator to specify design categories for mass production. In addition, geometry
of layout should be considered to achieve uniformity number required in 45nm node technology. In high pattern load
over transition pattern load, etch bias shows saddle shape uniformity. Since the saddle shape uniformity is uncorrectable
with conventional etch loading kernel, new correction model should be considered to meet the confined CD specification
in future device nodes.
Coping with double-patterning/exposure lithography by EB mask writer EBM-6000
Author(s):
Takashi Kamikubo;
Rieko Nishimura;
Kaoru Tsuruta;
Kiyoshi Hattori;
Jun Takamatsu;
Shusuke Yoshitake;
Hiroshi Nozue;
Hitoshi Sunaoshi;
Shuichi Tamamushi
Show Abstract
Double exposure / Double pattering methodologies are being adopted to extend 193nm optical lithography until the next
generation lithography, most likely the EUV, is solidified. The Double exposure / Double patterning methodologies
require tighter image-placement accuracy and Critical Dimension (CD) controls on a mask than the conventional single
exposure technique. NuFlare Technology's mask writer, EBM-6000 (1), is capable of achieving the required CD control
and high patterning resolution as fine as 35 nm, that are required for the hp 45nm lithography with Double exposure /
Double patterning methodologies, when newly developed resist (i.e. "low-sensitivity" resist) is used, as shown at several
occasions to date. Further, image-placement control with EBM-6000 has been improved based on extensive error
budget analysis to comply with the tight image-placement specifications required by the Double exposure / Double
Patterning lithography. This paper will show the results of the analysis and improvement of the image-placement
accuracy of EBM-6000 series mask writers.
Performance comparison of techniques for intra-field CD control improvement
Author(s):
Rainer Pforr;
Mario Hennig;
Jens Reichelt;
Guy Ben Zvi;
Martin Sczyrba
Show Abstract
Intra-field CD variation is a main contributor to the total CD variation budget in IC manufacturing. It is essentially
caused by mask CD variations and imperfections of the exposure tool. Techniques to reduce the IF CD error will be
introduced. Tool and mask based CDU improvement techniques will be compared. Their CDU improvement potential
and their correction accuracy will be analyzed. The correction methodology will be discussed, specifically none-wafer
based CD measurement techniques as correction data input. Implementation efforts of the techniques will be compared.
Projection maskless patterning (PMLP) for the fabrication of leading-edge complex masks and nano-imprint templates
Author(s):
Elmar Platzgummer;
Hans Loeschner;
Gerhard Gross
Show Abstract
The reliable and cost-effective fabrication of 2D and 3D structured nano-surfaces is prerequisite for a number of industrial
and emerging applications: (i) leading-edge complex masks, (ii) high precision nano-imprint templates, (iii) nano-functionalized
surfaces and 3D structures for applications in nano-photonics, nano-magnetics, and nano-biotechnology.
Projection Mask-Less Patterning (PMLP) is based on many hundred thousands of ion beams working in parallel. A PMLP
proof-of-concept tool has been realized as part of the European project CHARPAN (Charged Particle Nanotech;
www.charpan.com). The novel ion beam projection optics with 200x reduction shows 16nm half pitch resolution. First
results with a programmable aperture plate system have been achieved demonstrating high accuracy and flexible pattern
fabrication.
Improving the CD linearity and proximity performance of photomasks written on the Sigma7500-II DUV laser writer through embedded OPC
Author(s):
Anders Österberg;
Lars Ivansen;
Angela Beyerl;
Tom Newman;
Amanda Bowhill;
Emile Sahouria;
Steffen Schulze
Show Abstract
Optical proximity correction (OPC) is widely used in wafer lithography to produce a printed image that best matches the
design intent while optimizing CD control. OPC software applies corrections to the mask pattern data, but in general it
does not compensate for the mask writer and mask process characteristics. The Sigma7500-II deep-UV laser mask writer
projects the image of a programmable spatial light modulator (SLM) using partially coherent optics similar to wafer
steppers, and the optical proximity effects of the mask writer are in principle correctable with established OPC methods.
To enhance mask patterning, an embedded OPC function, LinearityEqualizeTM, has been developed for the Sigma7500-
II that is transparent to the user and which does not degrade mask throughput. It employs a CalibreTM rule-based OPC
engine from Mentor Graphics, selected for the computational speed necessary for mask run-time execution. A multinode
cluster computer applies optimized table-based CD corrections to polygonized pattern data that is then fractured
into an internal writer format for subsequent data processing. This embedded proximity correction flattens the linearity
behavior for all linewidths and pitches, which targets to improve the CD uniformity on production photomasks.
Printing results show that the CD linearity is reduced to below 5 nm for linewidths down to 200 nm, both for clear and
dark and for isolated and dense features, and that sub-resolution assist features (SRAF) are reliably printed down to 120
nm. This reduction of proximity effects for main mask features and the extension of the practical resolution for SRAFs
expands the application space of DUV laser mask writing.
Contrast properties of spatial light modulators for microlithography
Author(s):
J. Heber;
D. Kunze;
P. Dürr;
D. Rudloff;
M. Wagner;
P. Björnängen;
J. Luberek;
U. Berzinsh;
T. Sandström;
T. Karlin
Show Abstract
The present article discusses steps for the realistic description of optical properties of micro-mirror arrays (MMA),
which are utilized as programmable masks for microlithography. The article focuses on global contrast as an
elementary example for the understanding of MMA's diffractive operation principle. Central point will be a
discussion of those MEMS properties that influence the global MMA contrast, and how to introduce them into
simulation. Surface corrugations of single mirrors and slit properties will be taken into account. Comparison is
made with experimental contrast data to validate the theoretical assumptions.
Accuracy of mask pattern contour extraction with fine-pixel SEM images
Author(s):
Shinji Yamaguchi;
Eiji Yamanaka;
Hidefumi Mukai;
Toshiya Kotani;
Hiromitsu Mashita;
Masamitsu Itoh
Show Abstract
The specification of photomask patterns is defined for each semiconductor device technology node based on the
ITRS (International Technology Roadmap for Semiconductors). The quality of the photomask patterns has been
managed by using a metrology tool for CD (Critical Dimension) and an inspection tool for pattern shape. According
to shrinkage of semiconductor device patterns, the lithography margin has gradually become smaller. Consequently,
the quality of photomask patterns has been managed by observing small lithography margin patterns in addition to
the conventional quality management patterns with the conventional metrology tool. Furthermore, recently, as each
successive device generation has become shorter, rapid improvement of not only turnaround time of photomask
manufacturing but also yield of semiconductor device manufacturing has become necessary. Therefore, the
importance of the flexible mask specifications concept is increasing. The quality of photomask patterns with respect
to the specifications is judged in terms of pass/fail based on the allowable lithography margin. The methodology
is that small lithography margin patterns are selected, micrographs of the selected photomask patterns are acquired by
a metrology tool, photomask pattern contours are extracted with the micrographs, resist patterns exposed on Si wafer
are simulated by using the photomask pattern contours with lithography simulation under actual exposure conditions,
the lithography margin is calculated and the quality of the photomask is judged in terms of pass/fail criteria based on
the lithography margin for each generation, device and layer.
For management of the quality of photomask patterns based on the flexible mask specifications, it is necessary to
measure two-dimensional patterns such as hot-spot patterns for each critical layer in devices having small lithography
margin. Therefore, in order to manage quality in the case of flexible mask specifications, a two-dimensional
photomask pattern contour extraction tool was studied and developed. The photomask pattern contour extraction
tool realizes the combination of acquisition of fine-pixel SEM images of the photomask patterns in wide field and
extraction of photomask pattern contours by using the acquired fine-pixel SEM images.
There have been many reports on the repeatability and reliability of CD and two-dimensional pattern metrology
tools based on the conventional specifications. However, there are very few reports on the repeatability and reliability
of photomask pattern metrology tools based on flexible mask specifications. In this paper, using small lithography
margin patterns, firstly, the fine-pixel SEM images of photomask patterns are acquired. Secondly, contours of the
photomask patterns are extracted with the SEM images. Thirdly, contours of resist patterns on Si wafer are simulated
with lithography simulation under actual exposure condition by using the actual photomask pattern contours. Finally,
the lithography margin is calculated by using FEM (Focus Exposure Matrix) for the simulated contours of resist
patterns. This flow is repeated. The lithography margin with this flow is compared with that of actual exposed
wafers. Repeatability and reliability of the lithography margin is evaluated. As a result, accuracy of the photomask
pattern contour extraction tool is discussed.
2D measurement using CD SEM for arbitrarily shaped patterns
Author(s):
Hyung-Joo Lee;
So-Yoon Bae;
Dong-Hoon Chung;
Sang-Gyun Woo;
HanKu Cho;
Jun Matsumoto;
Takayuki Nakamura;
Dong Il Shin;
TaeJun Kim
Show Abstract
As the design rule of lithography becomes smaller, accuracy and precision in Critical Dimension (CD) and
controllability of pattern-shape are required in semiconductor production. Critical Dimension Scanning Electron
Microscope (CD SEM) is an essential tool to confirm the quality of the mask such as CD control, CD uniformity and CD
mean to target (MTT). Unfortunately, in the case of extremely rounded region of arbitrary enclosed patterns, CD
fluctuation depending on Region of Interest (ROI) is very serious problem in Mask CD control, so that it decreases the
yield. In order to overcome this situation, we have been developing 2-dimensonal (2D) method with system makers and
comparing CD performance between mask and wafer using enclosed arbitrary patterns. In this paper, we summarized the
results of our evaluation that compare error budget between 1-dimensonal (1D) and 2D data using CD SEM and other
optical metrology systems.
Images in photoresist for self-interferometric electrical image monitors
Author(s):
Juliet Rubinstein;
Andrew R. Neureuther
Show Abstract
Self-interferometric electrically measurable image focus monitors have been designed and tested in photoresist in a
double exposure implementation. The Pattern-and-Probe monitors for this experiment were placed on a multiple student
phase shift mask, and were validated by means of SEM images in photoresist on wafers shot at 193nm with an NA of
0.85, with 40nm focus steps. A large number of monitor parameters were varied in the experiment, such as the number
of rings, linewidth and center probe size, and recommendations for the optimal combination of parameters for the design
are given. Misalignment is accounted for by placing multiple patterns on the mask, translated a small amount so that at
least one will be centered exactly over the line. The results exhibit sufficient sensitivity to produce an open circuit after
0.3 - 0.6 Rayleigh Units defocus, and thus detect when the process is at the edge of the process window.
Preliminary verifiability of the aerial image measurement tool over photolithography process
Author(s):
Hyemi Lee;
Goomin Jeong;
Sangchul Kim;
Oscar Han
Show Abstract
The AIMS (Aerial Image Measurement Tool) measures approximate aerial images to scanner results by adjusting the
numerical aperture, illumination type and partial parameters. Accordingly, AIMS tool is used generally to verify the
issue points during manufacturing a mask. Normally using a mask for photolithography needs twice verifications. One
is the qualification in the mask shop. The other is verification over the photo process using the mask in the wafer fab. If
evaluated data at AIMS can be trusted about photo process ability including energy latitude (EL), depth of focus (DOF),
CD uniformity (CDU), pattern fidelity and mask defects including repair area, AIMS can function as a first filter before
shipping the mask. That means the AIMS data can be used as a preliminary data in the wafer fab.
So this study is focused on correlation between measured data at AIMS fab 193i and ArF scanner over the photo
process such as EL, DOF, CDU, pattern fidelity and mask defects. First, various patterns are made on attenuated PSM
from 80 to 65nm tech. Next correlations are calculated about EL, DOF and CDU by using same optical conditions,
measurement points and etc at AIMS and Scanner. Also the aerial images from AIMS are compared with scanner results
on defective side how those are matched with each other.
Consequently defect printability and CDU map at AIMS were similar to the scanner. In CDU point of view, AIMS
exceeds the predictive ability of the mask CD SEM. Moreover it means that wafer CDU can be corrected (improved)
independently on the CDU result of the wafer fab by using CDU correctable femto laser tool which reduces
transmittance of the mask. Surprisingly, it is possible. And Aerial image about mask defects including repair area is
useful to predict the problem of the mask, since it is similar to wafer results. But aerial image compared with wafer
image has more difference at 65nm technology node than at 80nm. If adjustment of threshold or measuring method can
be done, prediction of the scanner result will have no matter. In conclusion, predictive results at AIMS over photo
process can be applied as a preliminary data and it can be used to another index verifying the mask quality.
Calibration of contact areas: the influence of corner rounding
Author(s):
Jan Richter;
Eva-Maria Zerbe;
Thomas Marschner
Show Abstract
The precise reporting of critical dimension (CD) features on photolithographic masks is an essential part of
the mask production process. A wide range of external (standardization by national institutes) and internal
(standardization within mask houses to match different tools) methods has been set up to ensure calibration
consistency for the simple one dimensional case. One of the current developments is to expand these
concepts to area measurements. This is to achieve better reproducibility of CD tools and to achieve a better
characterization of contacts with respect to their imaging behaviour in wafer scanners. Here, we report some
very fundamental constrains of this approach that have to be taken into account regardless of the actual
measurement strategy. The major result is that for two dimensional contacts the shape has to be considered.
This is due to the fact that the usually constant offset for calibration of critical dimensions in one dimension
is no longer a constant but depends on the absolute size of the contact and the value of the corner rounding.
For standard values of 200 nm contacts with corner rounding of 75 nm and calibration offsets around 20 nm
maximum systematic differences of about 2nm will be obtained. Given the fact that even 40 nm calibration
differences for photomask standards can be observed even for national institutes, these systematic errors can
be easily as large as 6 nm for 200 nm structures. This systematic error clearly exceeds the road map targets
for critical dimension off-target specifications for the coming technology node. This statement is even
emphasized by the fact that in future contact layer specifications will be smaller than for lines/space layers.
Once tool independent characterization of contact areas has to be achieved, area measurement in each mask
house needs a second thought to implement these systematic constrains. Here, we show that the additional
measurement of the corner rounding ís a relatively easy method to accomplish this.
Measurements of corner rounding in 2D contact holes on phase-shift masks using broadband reflectance and transmittance spectra in conjunction with RCWA
Author(s):
Alexander Gray;
John C. Lam;
Stanley Chen;
Jan Richter
Show Abstract
For the first time, Rigorous Coupled-Wave Analysis (RCWA) is used for the analysis of both polarized broadband
reflectance and transmittance spectra with the purpose of measuring the degree of corner rounding in 2D contact holes.
The use of transmittance spectra proves to be advantageous for the characterization of the shape of the contact holes. In
contrast with the conventional reflectance-only techniques, transmittance measurements prove to be more sensitive to
the angstrom-level variations in the shape of the contact hole. Therefore, the new technique is capable of accurately
determining the degree of rounding of the contact hole corners and characterizing a variety of shapes - from perfectly
round to perfectly square. Additionally, the high intensity of the transmitted spectra improves the signal-to-noise ratio
and guarantees better repeatability of the results.
For the current study, 2D arrays of square contact holes with 800 nm pitch are measured on an After Clean Inspection
(ACI) phase-shift mask, using a spectrophotometer-based instrument capable of collecting four continuous spectra
during one measurement - two polarized reflectance spectra (Rs and Rp) and two polarized transmittance spectra (Ts and
Tp). The measured spectra are analyzed using the Forouhi-Bloomer dispersion equations, in conjunction with RCWA.
The method provides accurate and repeatable results for the degree of corner rounding of the square contact holes. In
addition, the method provides trench depth, critical dimensions, film thickness, and optical properties (n and k spectra
from 190 - 1000 nm) of phase-shift photomasks. The results of the measurements are represented as high-resolution
uniformity maps obtained for all the parameters mentioned above. The results show excellent correlation with
conventional CD metrology techniques.
Photomask applications of traceable atomic force microscope dimensional metrology at NIST
Author(s):
Ronald Dixson;
Ndubuisi G. Orji;
James Potzick;
Joseph Fu;
Richard A. Allen;
Michael Cresswell;
Stewart Smith;
Anthony J. Walton;
Andreas Tsiamis
Show Abstract
The National Institute of Standards and Technology (NIST) has a multifaceted program in atomic force microscope
(AFM) dimensional metrology. Three major instruments are being used for traceable measurements. The first is a
custom in-house metrology AFM, called the calibrated AFM (C-AFM), the second is the first generation of
commercially available critical dimension AFM (CD-AFM), and the third is a current generation CD-AFM at
SEMATECH - for which NIST has established the calibration and uncertainties. All of these instruments have useful
applications in photomask metrology.
Linewidth reference metrology is an important application of CD-AFM. We have performed a preliminary comparison
of linewidths measured by CD-AFM and by electrical resistance metrology on a binary mask. For the ten selected test
structures with on-mask linewidths between 350 nm and 600 nm, most of the observed differences were less than 5 nm,
and all of them were less than 10 nm. The offsets were often within the estimated uncertainties of the AFM
measurements, without accounting for the effect of linewidth roughness or the uncertainties of electrical measurements.
The most recent release of the NIST photomask standard - which is Standard Reference Material (SRM) 2059 - was also
supported by CD-AFM reference measurements. We review the recent advances in AFM linewidth metrology that will
reduce the uncertainty of AFM measurements on this and future generations of the NIST photomask standard.
The NIST C-AFM has displacement metrology for all three axes traceable to the 633 nm wavelength of the iodine-stabilized
He-Ne laser. One of the important applications of the C-AFM is step height metrology, which has some
relevance to phase shift calibration. In the current generation of the system, the approximate level of relative standard
uncertainty for step height measurements at the 100 nm scale is 0.1 %. We discuss the monitor history of a 290 nm step
height, originally measured on the C-AFM with a 1.9 nm (k = 2) expanded uncertainty, and describe advances that bring
the step height uncertainty of recent measurements to an estimated 0.6 nm (k = 2). Based on this work, we expect to be
able to reduce the topographic component of phase uncertainty in alternating aperture phase shift masks (AAPSM) by a
factor of three compared to current calibrations based on earlier generation step height references.
Laterally resolved off-axis phase measurements on 45-nm node production features using Phame
Author(s):
Ute Buttgereit;
Sascha Perlitz;
Dirk Seidel;
Kyung M. Lee;
Malahat Tavassoli
Show Abstract
As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever.
To ensure an accurate printing both attenuated and alternating PSMs (Phase Shift Masks) need precise control of phase
as a function of both pitch and target sizes. However critical target CDs fall much below conventional phase metrology
tools capabilities. Interferometer-based phase shift measurements are limited to large CD targets and require custom
designed features in order to function properly, which limits phase measurement. AFM (Atomic Force Microscopy)
methods are able to capture small feature sizes but do not consider any diffraction effects which are caused by the
topography of the features itself when getting close to the used wavelength.
Imaging simulations, both, in a rigorous and a Kirchhoff regime, show the dependency of the phase in the image plane
of a microlithography exposure tool on numerical aperture and pitch due to the loss of phase information in the imaging
pupil. Additionally, for small features the phase is strongly impacted by polarization and 3D mask effects. For these
feature sizes, the image phase does not coincide with the etch depth equivalent phase calculated from the nominal depth
and optical constants of the shifter material. Deviations up to 20° have been observed leading to strong variations in the
imaging quality and process window variations during scanner printing. Considerations of CD variation between 0 and
pi features by simulation show lowest 0/pi CD variation and therefore largest process window if the scanner relevant
phase is at 180°. The simulation results illustrate the importance to measure the scanner relevant phase, effective in the
image plane of the scanner.
Consequently Zeiss, in collaboration with Intel, has developed a laterally resolving Phase Metrology Tool - Phame® -
for in-die phase measurements. The optical metrology tool is able to perform in-die phase measurement on alternating
PSM, attenuated PSM and CPL masks down to 120nm half pitch at mask. On-axis measurement results have already
been published.
In this paper we elaborate on off-axis phase measurement theory and procedure. Furthermore we present first off-axis
measurement results over varying features sizes using different illumination conditions.
LRC techniques for improved error detection throughout the process window
Author(s):
Venson Lee;
Sheng-Hua Tsai;
Jun Zhu;
Lantian Wang;
Shu-Mei Yang;
Dan White
Show Abstract
Litho rule checking (LRC) is now an established component in the mask synthesis flow. Yet the requirements placed on
LRC have grown as process complexity has increased. At 45nm and beyond, new techniques are required to thoroughly
and efficiently evaluate a layout for potential lithographic problems. This paper examines new modeling and checking
techniques which improve the detection of lithographic errors. For more thorough error detection across a wider range
of process points, a process window technique provides checking of potential lithographic errors at nine different process
points. To better detect potential pinches or bridges induced by deep sub-wavelength lithography, a technique which
identifies problems regardless of orientation is used. These techniques provide more thorough checking, both better
accuracy and improved runtime performance across the complete process window.
Teracomputing for mask data preparation
Author(s):
John Nogatch;
Hartmut Kirsch;
Kamal Mostafa;
Glenn Newell;
Johnny Yeap
Show Abstract
Current and future Mask Data Preparation continues to see larger file sizes and longer processing times. Distributed
processing using multiple processors provides more compute power, but file Input/Output time remains a significant
portion of MDP processing. Data compression, fast disk storage, and fast network hardware are shown to provide some
benefit, but are not sufficient for unlimited scalability. Most MDP file formats store pattern data in a single disk file,
which creates a performance obstacle in the process flow. Dividing data into multiple files is shown to improve writing
speed, and to facilitate pipelined execution of multistage process flows. The advantages, disadvantages, and system
management of distributed files in the terabyte era are described.
Compressing MEBES data enabling multi-threaded decompression
Author(s):
Mark Pereira;
Anil Parchuri
Show Abstract
With the resolution enhancement techniques such as OPC (Optical Proximity Correction) and SRAF (Sub-Resolution
Assist Features), the size of layout data have grown significantly. It is quite common now to find layout files that are tens
of GBs in size. Unlike GDSII which can store data hierarchically, mask data formats such as MEBES are essentially flat
and more voluminous. Moreover, polygonal data present in layout data files is fractured, thereby increasing the data
volume before getting stored in MEBES data format. This results in huge MEBES files. As per the ITRS roadmap of
2005, for a 45nm half-pitch node that is expected to be in use by 2010, the mask data volume for a single layer is
expected to reach up to 825 GB. Storing and transferring such large mask data are issues for which the mask industry
needs solutions.
Historically, MEBES is the most prevalent EB format in the industry. Moreover, in many Mask Data Preparation (MDP)
flows, the MEBES format is being used as the de-facto standard for specifying the fractured EB data even though the
final target EB machine might be different. In this paper we present techniques for lossless reversible compression of
MEBES data, i.e., when the compressed file is decompressed, the generated uncompressed file matches the original
MEBES file bit- by-bit. By applying these compression techniques a compression ratio of 5X to 15X can be obtained.
In practice, compressing MEBES files is usually a one-time task, but decompression of compressed files is expected to
be done multiple times as every time a compressed MEBES file needs processing, it has to be decompressed. MEBES is
essentially an efficient data format and the geometries are stored compactly. As a result the compression/decompression
techniques described in this paper are quite computation intensive in order to achieve higher compression ratio. This in
turn leads to higher CPU time for compression/decompression compared to generic compressors such as gzip. However,
as the format-specific compressors produce higher compression ratios, the disk I/O time for compression and
decompression is expected to be less compared to the generic compressors such as gzip and gunzip. In spite of this, the
format-specific decompressor is usually 3-5X times slower than the generic decompressor such as gunzip. Since
decompression is expected to be done more frequently as compared to compression, speeding up decompression is
highly desirable. We present a compression technique for MEBES data which enables multiple process threads to
decompress the compressed MEBES data. With the multi-core multiprocessor machines becoming quite inexpensive and
common, the multi-threaded decompression is expected to perform close to the disk I/O time on such machines.
The paper details out the techniques, experimental results in terms of comparative compression ratios, compression and
decompression speed using single threads and multiple threads. The possibility of getting higher compression ratios as
well as higher or comparable decompression speed makes it more practical to use format specific reversible compression
schemes rather than using generic compressors. Even though, the paper focuses on compression and decompression of
MEBES, it can be easily extended to the compression of GDSII [1].
Mask manufacturability improvement by MRC
Author(s):
A. Balasinski;
D. Coburn;
P. Buck
Show Abstract
Mask data which can not be properly resolved by the mask writing tools, such as sub(resolution (reticle-scale) features or
singularities can interfere with design intent or manufacturing capabilities in the absence of design guidelines or formal
verification procedures. As a consequence, mask writing tools may introduce defects to device or metrology structures
by snapping geometries to grid or misrepresenting process based sizing. To reduce the visibility of these defects by
detuning inspection tools to release the mask with non-resolvable data in the production cycle or by waiving minimum
CD rules compromises high fidelity of die pattern transfer to wafer. Driven by poor data quality, mask tool would
provide degraded resolution without contextual analysis, such as correlations to the overlying and underlying mask
layers and without regard to device models. The key reasons for this situation are arbitrary layout of technology
structures and design layout-to-mask post-processing for OPC and fill pattern for which design has no intention or
knowledge to intervene. The post-processing of mask data to eliminate errors effectively detaches design responsibility
from the mask shop actions and may have other detrimental effects on the production cycle such as iterative defect
analysis and long write times due to the large polygon count. In this work we propose mask rule check based on the
principles to which the masks are being written and inspected. Running this mandatory rule set should reduce the
product cycletime, benefit the cost and improve mask quality and reproduction of design intent. It feeds the prospective
mask information back to the layout time making it possible to make design adjustments in the interest of pattern fidelity
and device parameters.
Reduction of layout complexity for shorter mask write-time
Author(s):
Sean Hannon;
Travis Lewis;
Scott Goad;
Kenneth Jantzen;
Jianlin Wang;
Hien T. Vu;
Emile Sahouria;
Steffen Schulze
Show Abstract
As tolerance requirements for the lithography process continue to shrink, the complexity of the optical proximity
correction is growing. Smaller correction grids, smaller fragment lengths and the introduction of pixel-based simulation
lead to highly fragmented data fueling the trend of larger file sizes as well as increasing the writing times of the vector
shaped beam systems commonly used for making advanced photomasks. This paper will introduce an approach of
layout modifications to simplify the data considering both fracturing and mask writing constraints in order to make it
more suitable for these processes. The trade-offs between these simplifications and OPC accuracy will be investigated.
A data processing methodology that allows preserving the OPC accuracy and modifications all the way to the mask
manufacturing will also be described. This study focuses on 65nm and 45nm designs.
Optimizing defect inspection strategy through the use of design-aware database control layers
Author(s):
Dvori Stoler;
Wayne Ruch;
Weimin Ma;
Swapnajit Chakravarty;
Steven Liu;
Ray Morgan;
John Valadez;
Bill Moore;
John Burns
Show Abstract
Resolution limitations in the mask making process can cause differences between the features that appear in a database
and those printed to a reticle. These differences may result from intentional or unintentional features in the database
exceeding the resolution limit of the mask making process such as small gaps or lines in the data, line end shortening on
small sub-resolution assist features etc creating challenges to both mask writing and mask inspection. Areas with high
variance from design to mask, often referred to as high MEEF areas (mask error enhancement factor), become highly
problematic and can directly impact mask and device yield, mask manufacturing cycle time and ultimately mask costs.
Specific to mask inspection it may be desirable to inspect certain non-critical or non-relevant features at reduced
sensitivity so as not to detect real, but less significant process defects. In contrast there may also be times where
increased sensitivity is required for critical mask features or areas. Until recently, this process was extremely manual,
creating added time and cost to the mask inspection cycle. Shifting to more intelligent and automated inspection flows is
the key focus of this paper. A novel approach to importing design data directly into the mask inspection to include both
MDP generated MRC errors files and LRC generated MEEF files.
The results of recently developed inspection and review capability based upon controlling defect inspection using design
aware data base control layers on a pixel basis are discussed. Typical mask shop applications and implementations will
be shown.
New method of identification of false or nuisance defects using defect imaging system DIS-05
Author(s):
Hao Zhang;
Katsuyuki Takahashi;
Hideaki Bando;
Yasunobu Kitayama;
Akio Sugano;
Kenichi Kobayashi
Show Abstract
This article presents novel defect review tool developed from CD-SEM, and its application for identification,
classification and judgment of false or nuisance defects.
Mask inspection tool is indispensable for mask production. Since conventional inspection tools use the optical source,
some of the defects are difficult to be identified and classified in the proper manner because the tool resolution is not
sufficient.
We have developed the Defect Imaging System (DIS-05) based on CD-SEM which uses secondary electron and
backscattered electron images. These SEM images are used for reviewing the defects detected in advance by optical
inspection tools. This system also includes Die-to-Die, Die-to-Database and "any shaped pattern area measurement" of
Holon original development.
Improving inspectability with KLA-Tencor TeraScan thin line de-sense
Author(s):
Chunlin Chen;
David Kim;
Ki Hun Park;
NamWook Kim;
Sang Hoon Han;
Jin Hyung Park;
Dong Hoon Chung
Show Abstract
In the ever-changing semi-conductor industry, new innovations and technical advances constantly bring new
challenges to fabs, mask-shops and vendors. One of such advances is an aggressive optical proximity
correction (OPC) method, sub-resolution assist features (SRAF). On one hand, SRAFs bring a leap forward
in resolution improvement during wafer printing; on the other hand they bring new challenges to many
processes in mask making. KLA-Tencor Corp. working together with Samsung Electronics Co. developed an
additional function to the current HiRes 1 detector to increase inspectability and usable sensitivity during the
inspection step of the mask making process. SRAFs bring an unique challenge to the mask inspection process,
which mask shops had not experienced before. SRAF by nature do not resolve on wafer and thus have a
higher tolerance in the CD (critical dimension) uniformity, edge roughness and pattern defects.
This new function, Thin-Line De-sense (TLD), increase the inspectability and usable sensitivity by generating
different regions of sensitivity and thus will match the defect requirement on a particular photomask with
SRAFs better. The value of TLD was proven in a production setting with more than 30 masks inspected, and
resulted in higher sensitivity on main features and a sharp decrease in the amount of defects that needed to be
classified.
Implementation of an efficient defect classification method in photomask mass production
Author(s):
Cathy Liu;
Crystal Wang;
Skin Zhang;
Eric Guo;
Steven Liu;
Eric Haodong Lu;
Dongsheng Fan;
Den Wang;
Weiming Ma
Show Abstract
In photomask production environments, increasing productivity of defect inspection and improving fidelity of defect
classification are important for mask makers to improve capacity of defect inspection tools and to enhance quality of
production. In particular, defect classification time corresponds directly to the cost and the cycle time of mask
manufacturing and new product development. KLA-Tencor has introduced an automatic defect grouping tool
"ReviewSmart" which automatically bins defects with high fidelity. ReviewSmart has been reported in engineering R&D
and evaluation. In this paper, we focus on implementation of ReviewSmart in photomask production. 592 plates
were processed during the evaluation period. Those plates are for products of logic, memory and flash. Technology
nodes are from 65nm to 180nm. With optimized production setting, the automatic defect grouping tool - ReviewSmart
improves productivity of defect inspection by 7% with 100% fidelity. In addition to improve productivity, ReviewSmart
is helpful to classify aggressive OPC caused nuisance, troubleshoot process issues and expedite product development and
improve usable inspection sensitivity as well.
To improve reticle re-qualification process and reduce reticle re-cleaning frequency using efficient defect classification and defect tracking
Author(s):
Eric Haodong Lu;
Jim Wang;
Raj Badoni;
Ellison Chen;
Weimin Ma
Show Abstract
For improving productivity and reducing manufacturing cost, it is critical for wafer fabs to reduce the frequency of
reticle re-clean and control the risk of missing defects of lithographic significance from overall haze defected. Haze
classification and haze behavior monitoring are highly time consuming processes. Many wafer fabs skip such operations
and instead re-clean reticles frequently in order to reduce the risk of missing killer haze defects. Such Reticle Re-Qual
rule leads to more than necessary reticle re-cleaning, shortening the life cycle of reticles and increasing the
manufacturing cost. In this paper, we investigate an efficient defect classification method - ReviewSmart, and defect
auto tracking method to classify defects and efficient tracking haze growth. A solution is discussed for wafer fabs to
monitor haze behaviors and improve Reticle Re-Qual rules for controlling and reducing manufacturing cost at lower risk.
A total of more then 30 production reticles of critical layers of OD, Poly, Contact and Metal 1 were inspected by
STARLight2TM on KLA-Tencor TeraScan SL516 system. ReviewSmart processed all the defects detected during Reticle
Re-Qual inspection. The results showed significant reduction in defect review times, with 100% fidelity rate.
Automating defect disposition in fabs and maskshops
Author(s):
Peter Fiekowsky;
S. Narukawa;
T. Kawashima
Show Abstract
ADAS (Automated Defect Analysis Software) is the first product to fully automate mask defect analysis for mask shops
and fabs. ADAS classifies and dispositions photomask defects quickly and accurately. Disposition is based on defect
size and printability measurements from simulation.
Full analysis of inspection reports with 100 defects requires 2 seconds. Printability measurements match AIMS within 6
percent at 3 sigma on 45 nm test masks. Repeatability is 5 percent at 3 sigma over multiple inspections. ADAS can
reduce the need for production AIMS measurements by 90% and eliminate operator review errors and the repelliclizations
they cause. ADAS increases overall inspection efficiency for mask shop first-inspection and final
inspection. It can automate fab requalification inspections and eliminate the need for incoming inspection.
Automatic OPC repair flow: optimized implementation of the repair recipe
Author(s):
Mohamed Bahnas;
Mohamed Al-Imam;
James Word
Show Abstract
Virtual manufacturing that is enabled by rapid, accurate, full-chip simulation is a main pillar in achieving successful
mask tape-out in the cutting-edge low-k1 lithography. It facilitates detecting printing failures before a costly and time-consuming
mask tape-out and wafer print occur. The OPC verification step role is critical at the early production phases
of a new process development, since various layout patterns will be suspected that they might to fail or cause
performance degradation, and in turn need to be accurately flagged to be fed back to the OPC Engineer for further
learning and enhancing in the OPC recipe. At the advanced phases of the process development, there is much less
probability of detecting failures but still the OPC Verification step act as the last-line-of-defense for the whole RET
implemented work.
In recent publication the optimum approach of responding to these detected failures was addressed, and a solution was
proposed to repair these defects in an automated methodology and fully integrated and compatible with the main
RET/OPC flow. In this paper the authors will present further work and optimizations of this Repair flow.
An automated analysis methodology for root causes of the defects and classification of them to cover all possible causes
will be discussed. This automated analysis approach will include all the learning experience of the previously
highlighted causes and include any new discoveries. Next, according to the automated pre-classification of the defects,
application of the appropriate approach of OPC repair (i.e. OPC knob) on each classified defect location can be easily
selected, instead of applying all approaches on all locations. This will help in cutting down the runtime of the OPC repair
processing and reduce the needed number of iterations to reach the status of zero defects. An output report for existing
causes of defects and how the tool handled them will be generated. The report will with help further learning and
facilitate the enhancement of the main OPC recipe. Accordingly, the main OPC recipe can be more robust, converging
faster and probably in a fewer number of iterations. This knowledge feedback loop is one of the fruitful benefits of the
Automatic OPC Repair flow.
Database and data analysis strategy for multi-designer testchips
Author(s):
Wojtek J. Poppe;
Patrick Au;
Darshana Jayasuriya;
Andrew Neureuther
Show Abstract
A database and data analysis strategy is proposed for multi-designer test chips that involve a wide array of different test
structures aimed at process characterization. The database described in this paper has been custom built for the multi-student
FLCC testchip that has six contributing students and over 15,000 individually probably transistors/test
structures. It has an interface with the Parametric Yield Simulator (PYS) that drives simulation parameters and
automatically populates the database with simulation results of each test structure at the specified process conditions. A
well-designed database forces structure into measurement and design related data, but includes enough flexibility as to
adapt to different types of test structures and experiments. The database is split into four separate sections that store
description of test structures, simulated results, experiment results, and process conditions. All data is centrally located
and web accessible for easy access from any computer with Internet access. Simulation results can be uploaded from the
server running the PYS, experimental results can be uploaded directly from the lab and data can be compared and
queried by all users of the database. Data analysis strategies can be compared and reused as queries and data analysis
results can be shared among users through the website. Queries can be saved, loaded, rated, and reused, so even novice
SQL users can utilize advanced queries. Advanced queries form the basis of a strategy that first identifies good process
monitors based on simulation results and then uses them to extract process conditions from electrical measurements via
an iterative process. This paper describes strategies that can be used to help facilitate collaboration and hence leverage
the benefits of combining multiple sets of test structures from different designers on one chip.
Determining OPC target specifications electrically instead of geometrically
Author(s):
Qiaolin Charlie Zhang;
Paul van Adrichem
Show Abstract
Deep sub-wavelength optical lithography significantly distorts the shape of transistor channel,
particularly causing gate corner rounding at the beginning of active area (i.e. active margin), due to
proximity effect. Optical Proximity Correction (OPC) aims at compensating for lithography induced
geometry distortion, but still could not completely fix geometry distortion especially corner
rounding. The OPC target specification of corner rounding at active margin, i.e. how many
nanometer of corner rounding is allowed, is usually determined subjectively based geometric specs
without considering the actual electrical performance impact on transistor. Instead of determining
the OPC corner rounding target specs geometrically, we proposed a methodology to determine
corner rounding specs electrically, particularly in this case, based on the impact on transistor drain
current in saturation mode.
We first assessed the impact of corner rounding on transistor drain current using a first order
analytical model, then compared it with the HSPICE simulation result using a non-rectangular
transistor channel whose shape was obtained through post-OPC lithography simulation. Reasonably
good agreement was observed between the first order model approach and the HSPICE simulation
based approach, which is more rigorous intrinsically.
This methodology can also be used in the determination of lithography process specification such as
misalignment between active and poly gate layers.
Application of modified jog-fill DRC rule on LFD OPC flow
Author(s):
Young-Mi Kim;
Sang-Uk Lee;
Jea-Hyun Kang;
Jea-Hee Kim;
Kee-Ho Kim
Show Abstract
The methodology of lithography friendly design (LFD) has been widely adopted since it dramatically reduces cycle of
design revision as well as number of learning cycles to reach acceptable yield. LFD is, for example, the reduction
number of small jogs and notches in original, pre-OPC layouts. We can call them as OPC-unfriendly patterns since they
create unnecessarily complicated OPC patterns. They usually meet design rule so that DRC does not detect or screen
them out. Also, they make many errors after OPC because OPC model recognizes just as one of small features that it
should care. This generates many false alarms at OPC verification and mask rule check.
General approach to implement LFD is to update rule table or design rule by taking actual yield and failure analysis
data into consideration of database handling flow. Another method is the utilization of simulation to predict lithography
unfriendly designs. It takes time to setup excellent rule for accurate prediction even if they are very good approach as
fundamental solution for LFD. It will be better to have a simple solution with fast setup and improvement on major
lithography unfriendly designs such as small jogs and notches.
In this paper, we proposed new type of LFD flow which is the application of modified DRC step on LFD flow. This
modified DRC identifies OPC-unfriendly patterns, and changes to "OPC-friendly" as well as fixing design rule
violations. It is a pre-OPC layout treatment to remove small jogs and notches. After finding small jogs or notches, DRC
software removes jogs and notches. In this case, unnecessary OPC fragments could be avoided. Using this jog-fill
technique, we can dramatically reduce the incidence of necking or bridging, improve contact coverage, and, as a result, it
enhances the final yield and reliability of circuit.
Pellicle dimensions for high NA photomasks
Author(s):
Frank Erber;
Thomas Schulmeyer;
Christian Holfeld
Show Abstract
At photomask manufacturing, post pellicle inspection suffers from an interference of pellicle size and height dimensions
with the inspection equipment requirements. This pellicle shadow causes nonreliable inspection results. The evolution
of this effect as well as similar potentially upcoming effects during other lithography processes need to be understood in
order to identify potential problems ahead of time and guide the industry accordingly. The study recommends
standardizing pellicle size and height dimensions in order to coordinate the required changes at scanner, mask inspection,
mask metrology and pellicle vendors in the near and long term. Since frequent changes in other pellicle properties are
expected over time to fulfill the requirements for high NA lithography and haze reduction, a standard in pellicle
dimensions will also help controlling the complexity of pellicle variations.
Evaluation of attenuated PSM photomask blanks with TF11 chrome and FEP-171 resist on a 248 nm DUV laser pattern generator
Author(s):
Kezhao Xing;
Charles Björnborg;
Henrik Karlsson;
Adisa Paulsson;
Anna Rosendahl;
Peter Beiming;
Jukka Vedenpää;
Jonathan Walford;
Tom Newman
Show Abstract
Tighter requirements on mask resolution, CD and image positioning accuracy at and beyond the 45 nm technology node
push the development of improved photomask blanks. One such blank for attenuated phase-shift masks (att-PSM)
provides a thinner chrome film, named TF11, with higher chrome etch rate compared to the previous generation Att-
PSM blank (NTAR5 chrome film) from the same supplier. Reduced stress in the chrome film also results in less image
placement error induced by the material. FEP-171 is the positive chemically amplified resist (PCAR) that is most
commonly used in advanced mask manufacturing with both 50 keV variable shaped e-beam (VSB) and DUV laser
pattern generators. TF11 allows an FEP-171 resist film down to about 2000 Å thickness with sufficient etch resistance,
while the standard resist thickness for NTAR5 is around 3000 Å.
This work has experimentally evaluated the use of TF11 chrome and FEP-171 resist together with a 248 nm DUV laser
pattern generator, the Sigma7500. First, patterning performance in resist with thicknesses from 2000 Å to 2600 Å, in
steps of 100 Å, was tested with respect to swing curve and basic lithographic parameters including resolution, CD
linearity, CD iso-dense bias and dose sensitivity. Patterning results on mask showed a swing minimum at around 2200 Å
and a swing maximum at around 2500 Å, which correspond to reflectivity measurements for 248 nm wavelength
performed by the blank supplier. It was concluded that the overall patterning performance was best close to the swing
maximum. Thereafter the patterning performance using TF11 at two resist thicknesses, 2000 Å and 2550 Å, was studied
in more detail and compared to performance using NTAR5 with 3200 Å resist. The evaluation showed that the
Sigma7500-II offers good compatibility with TF11, especially using the optimized FEP-171 resist thickness of 2550 Å. It
also showed that the patterning capability of the Sigma7500-II using TF11 and 2550 Å resist is improved compared to
using NTAR5 and 3200 Å resist.
Bimetallic thermal resists potential for double-exposure immersion lithography and grayscale photomasks
Author(s):
James M. Dykes;
Calin Plesa;
Chinheng Choo;
Glenn H. Chapman
Show Abstract
Double exposure/patterning is considered the best candidate for extending 195nm optical lithography below 40nm
resolution. However, double exposure techniques require a resist where the exposures do not add linearly to produce the
final result. A class of negative thermal resists that show this effect are bimetallic thin-films consisting of Bi/In or Sn/In.
The films are bi-layered structured until sufficiently heated by a laser exposure pulse (7 mJ/sq. cm for 4 nsec).
Experiments with interference lithography at 266nm in air demonstrated that Bi/In resists have a resolution limit <42nm,
the exposure system limit. As a first investigation into the resist's potential for immersion lithography, the response of
bimetallic resists to immersion lithography was examined. The Sn/In film used demonstrated successful development as
thermal resist for immersion exposures and the power level required to convert the film was only slightly higher than the
level required for exposing the film in air.
Bimetallic films have demonstrated transmittances <0.1% when unexposed and >60% when highly exposed to an
Argon laser, enabling their application as grayscale photomasks. However, direct laser-writing of the photomasks causes
fine variations in their transparency due to the laser beam's Gaussian power profile. To correct this problem, a beam-shaping
mask was designed to manipulate the power profile of the laser. To help measure mask transparency at a
resolution suitable for characterizing a photomask, two photodiode sensors were added to the writing system. The
profiling ability offered by the modified system allows the use of test structures 100x smaller then previously required.
Acid diffusion length limitation for 45 nm node attenuated and chromeless phase shift mask
Author(s):
Young-Min Kang;
Seung-Wook Park;
Hye-Keun Oh
Show Abstract
Microlithography has shown an amazing development over the last decade and has continued to be one of the critical
success factors for enabling ever smaller feature sizes. The fabrication of leading edge devices strongly relies on the use
of chemically amplified resist, where the post exposure bake (PEB) is among the most important process steps for
obtaining smaller feature size with better linewidth control. PEB sensitivity is defined as the dependency of pattern size
(or critical dimension, CD) variation on the perturbation of the PEB temperature and time throughout this paper. From
the beginning of ArF (193 nm) lithography, PEB sensitivity becomes serious problem because ArF photoresist shows
very severe dependency on PEB temperature and time. PEB sensitivity relies largely on photo-generated acid diffusion.
If acid diffusion can be effectively controlled, PEB sensitivity will be improved. As pattern size decreases for a higher
density device, this variation can be more than 10% of target CD. Therefore, PEB sensitivity and diffusion length
becomes very important property for sub-90 nm pattern. This paper demonstrates the effect of acid diffusion length for
each PEB temperature and time for the mask types of attenuated and chromeless phase shift mask. Differences can
between the attenuated and chromeless phase shift masks as functions of PEB temperature and time and develop time.
We compared the acid diffusion lengths as a function of PEB time. And we calculated acid distribution as functions of
PEB time and diffusion length. CD uniformity, thickness loss and exposure latitude are also compared.
Critical dimension control for 32 nm random contact hole array with resist reflow process
Author(s):
Joon-Min Park;
Young-Min Kang;
Seung-Wook Park;
Joo-Yoo Hong;
Hye-Keun Oh
Show Abstract
50 nm random contact hole array by resist reflow process (RRP) was studied to make 32 nm node device. Patterning
of smaller contact hole array is harder than patterning the line and space. RRP has a lot of advantages, but RRP strongly
depends on pattern array, pitch, and shape. Thus, we must have full knowledge for pattern dependency after RRP, and
then we need to have optimum optical proximity corrected mask including RRP to compensate the pattern dependency in
random array.
To make optimum optical proximity and RRP corrected mask, we must have better understanding that how much resist
flows and where the contact hole locations are after RRP. A simulation is made to correctly predict RRP result by
including the RRP parameters such as viscosity, adhesion force, surface tension and location of the contact hole. As a
result, we made uniform 50 nm contact hole patterns even for the random contact hole array and for different shaped
contact hole array by optical proximity corrected RRP.
Self-aligned resist patterning with 172nm and 193nm backside flood exposure on attenuated phase shift masks
Author(s):
Jun Chun;
Taejoong Ha;
Hoyong Jung;
Sangjin Jo;
Oscar Han
Show Abstract
We have investigated self-aligned resist patterning for a patterning accuracy of photo mask. Self-aligned resist
pattern can be formed by backside flood exposure on photo-mask. It had been already proved by the experiments with
248 nm light source exposure on binary (Cr on Quartz) and KrF attenuated phase shift masks. Attenuated phase shift
masks are generally composed of Cr/MoSiN/Quartz, MoSiN/Quartz, and Quartz layers. MoSiN layers of attenuated
phase shift mask have the optical property of 6% transmittance at 248 nm light source, and the interference of the 6%-
transmitted light makes the undesirable resist pattern profile on MoSiN-Quartz boundary. This paper shows the fresh
possibility of the self-aligned resist pattern fabrication on attenuated phase shift masks using backside flood exposure. To
solve the optical property of MoSiN layer, self-aligned resist patterns of KrF attenuated phase shift mask was fabricated
using 193 nm wavelength backside flood exposure and ArF attenuated phase shift mask used 172 nm wavelength. The
shorter wavelength than generally applied wavelength could minimize transmittance on MoSiN area. Besides we used
Negative PR to make the self-aligned resist pattern on exposed regions. These experimental concepts help to form the
selective PR patterning on only quartz regions of attenuated phase shift mask.
Practical use of hard mask process to fabricate fine photomasks for 45nm node and beyond
Author(s):
Yasuyuki Kushida;
Hitoshi Handa;
Hiroshi Maruyama;
Yuuki Abe;
Yukihiro Fujimura;
Toshifumi Yokoyama
Show Abstract
New process with hard-mask (HM) blanks was evaluated as one of candidates for photomasks beyond 45nm-node.
Through the fabrication of gate-layer photomasks, aptitude of the HM process for practical use was confirmed from the
view of controllability on CDs and defects. Although conventional process for attenuated PSM was shown to have
critical CD error which belongs to the "patterns" in bright-field masks, experimental data proved effectiveness of the
HM process to control CDs after process optimization. With the HM blanks, remarkable reduction of CD error more
than 80% of conventional process was confirmed. In this report, peculiar opaque defects are also shown to be a critical
issue on the HM process. From results of design of experiment (DOE), combining the proper means to prepare the HM
blanks with the optimized HM etching condition, these defects were proved to be controlled within the tolerance for
production. Through the investigations, validity of the HM process on practical use for mask fabrication of 45nm-node
and beyond is considered as conclusions.
Overcoming loading challenges in a mask etcher for 45 nm and beyond
Author(s):
M. Chandrachood;
T. Y. B. Leung;
K. Yu;
M. Grimbergen;
S. Panayil;
I. Ibrahim;
A. Sabharwal;
A. Kumar
Show Abstract
Increasingly complex RET techniques need to be used in the sub wavelength regime
which will drive up the mask costs, as well as the design costs. Some of the RET
techniques used involves the use of OPC, PSM and hard mask. In order to reduce the
costs it is desirable to have uniform performance on shuttle masks, which can help to
reduce manufacturing costs. The micro loading and macro loading are of concern to mask
makers because of the varying loads being etched within the mask. It is critical to have a
mask etcher that provides excellent CD uniformity, CD bias, CD linearity and etch profile
in order to have image fidelity of the OPC structures as well as sustainable yields. This
paper discusses micro and macro loading challenges on BIM and APSM masks and the
advantages of using the Applied Materials' next generation mask etcher.
Resistless mask structuring using an ion multi-beam projection pattern generator
Author(s):
Joerg Butschke;
Mathias Irmscher;
Florian Letzkus;
Hans Loeschner;
Lorenz Nedelmann;
Elmar Platzgummer
Show Abstract
Line edge roughness (LER) and substrate resist interaction of chemically amplified resists (CAR) might be limitations for future mask making. An alternative solution could be the direct patterning of a thin hard mask on top of an absorber using a multiple ion beam pattern generator. Goal of this work was to assess a resistless hard mask structuring by direct patterning and a subsequent transfer into chrome by a dry etch process. Hard mask structuring has been done on the IMS Nanofabrication proof of concept tool which is designed for 40,000 multi-beam operations. For comparison to the resistless approach, a resist based stack patterning has been set up. Hard mask opening and subsequent chrome etching have been accomplished in a state of the art mask etcher. The assessment of both process schemes has been done in terms of feature profile and resolution capability. Finally, throughput estimation for a future production tool, operating with precursor gases and 1.000.000 ion beams has been calculated.
Reconfigurable lithographic applications using polymer liquid crystal composite films
Author(s):
Anna E. Fox;
Adam K. Fontecchio
Show Abstract
The proposed application of holographically formed polymer dispersed liquid crystal (H-PDLC) thin films is a
real-time dynamically reconfigurable mask for the resist exposure step in the photolithographic process. H-PDLC
films, or thin periodic nanostructures of alternating layers of polymer and liquid crystal have unique electro-optic
properties including the ability to modulate a particular wavelength as a function of bias applied to the film.
The H-PDLC photomask device consists of patterned electrodes that form pixels with independent bias control
over each segment. This is achieved by etching the optically clear yet electrically conductive indium-tin-oxide
electrodes on the glass confining the H-PDLC film. This mask has been used to cure Shipley 1800 series positive
photoresist at its peak sensitivity wavelength of 440 nm. Structures formed using the H-PDLC photomask device
have been compared to similar structures formed with a static photomask using an optical profilometer. Near
vertical walls have been achieved using the H-PDLC photomask for structures with line width of 260 μm, and
more narrow structures have been fabricated with resolution nearing 100 μm. Line width between structures
formed using the H-PDLC mask and static photomask differ by less than 15%. Additionally, morphology studies
have been performed on developed regions of glass and resist formed using a static and an H-PDLC mask to
demonstrate that no structural defects exist due to formation under an H-PDLC grating.
Pattern density and process related CD corrections at 32nm node
Author(s):
Zdenek Benes;
Jun Kotani
Show Abstract
With mask critical dimension (CD) uniformity requirements becoming tighter with each new technology node, mask
manufacturing must deploy a wide range of corrections to meet the CD specifications. These corrections compensate for
e-beam proximity effects, fogging effects, etch loading effect, and other global process non-idealities. In this paper, we
present data demonstrating that the current capability of universal e-beam dose corrections meets 32nm CD uniformity
requirements in the presence of various systematic CD errors. Given that the resist process demonstrates enough
latitude to accommodate the required dose variations, it is the stability and repeatability of the process itself that limits
the ability to meet CD requirements. Substrates, resist coating, post-coat delay, develop variations, and etch stability all
contribute to CD variations. Rather than simply focusing on reducing systematic errors, the process stability must be
addressed.
Automatic residue removal for high-NA extreme illumination
Author(s):
James Moon;
Byong-Sub Nam;
Joo-Hong Jeong;
Dong-Ho Kong;
Byung-Ho Nam;
Dong Gyu Yim
Show Abstract
An epidemic for smaller node has been that, as the device architecture shrinks, lithography process requires
high Numerical Aperture (NA), and extreme illumination system. This, in turn, creates many lithography problems such
as low lithography process margin (Depth of Focus, Exposure Latitude), unstable Critical Dimension (CD) uniformity
and restricted guideline for device design rule and so on. Especially for high NA, extreme illumination such as
immersion illumination systems, above all the related problems, restricted design rule due to forbidden pitch is critical
and crucial issue. This forbidden pitch is composed of numerous optical effects but majority of these forbidden pitch
compose of photo resist residue and these residue must be removed to relieve some room for already tight design rule.
In this study, we propose automated algorithm to remove photo resist residue due to high NA and extreme
illumination condition. This algorithm automatically self assembles assist patterns based on the original design layout,
therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist
residue created by extreme illumination condition. Also we tested our automated algorithm on full chip FLASH
memory device and showed the residue removal effect by using commercial verification tools as well as on actual test
wafer.
Effective area partitioning for preparing parallel processing in mask data preparation
Author(s):
Yoshiyuki Satou;
Yasushi Okamoto;
Manabu Fujimoto;
Hiroshi Tsuchida;
Akiko Satou
Show Abstract
Mask Data Preparation (MDP), which typically consists of Boolean operations, sizing, mask rule check (MRC) and
fracturing, requires intense computing power. For today's increasingly large data, utilizing distributed parallel processing
with multiple CPUs or using a host server is an established approach to reduce turn around time (TAT). A data analysis
and distributing loads are usually required in its preparation process, however it is inevitably a sequential process by its
nature, which severely affects the overall TAT. An inappropriate preparation process causes uneven loads for the parallel
processing and leads to an increase of TAT. It is challenging especially when a large number of parallel processing nodes
are used. This paper introduces a novel methodology of an efficient parallel processing to run an MDP. The involving
tests and analysis have been applied to layout data formats by using MaskStudio version 6 (MS6) fracturing system.
MS6 takes the method of grid-based partitioning as the preparing process of parallel processing, and each partition is
processed for such as Boolean operation, sizing and MRC. By increasing parallel processing nodes, this methodology
successfully showed the reduction of the process time.
Mask calibration dominated methodology for OPC matching
Author(s):
Liang Zhu;
Mark Lu;
Dion King;
Yili Gu;
Steve Yang;
Lawrence S. Melvin III
Show Abstract
The effectacy of the OPC model depends greatly on test pattern data calibration that accurately captures mask and wafer
processing characteristics. The CD deviation caused by an off-center mask process can easily consume the majority of
the lithography process CD budget. Mask manufacturing variables such as write tools' resolution, etch process effects,
and pre-bias of the fractured data have great impacts on OPC model performance. As a result, wafer performance using
masks from different mask shops varies due to variations in the mask manufacturing process, even if the masks are
written with the same data set and use the same manufacturing specifications. A methodology for mask manufacturing
calibration is proposed in order to make an OPC model consistent between two mask manufacturing processes. The
methodology consists of two parts: mask manufacturing calibration and wafer-level OPC accuracy verification. The
mask manufacturing process and metrology are calibrated separately. The OPC model is built based on the database of
the first-party mask shop, and OPC verification is carried out by wafer data using the newly calibrated mask from the
second-party mask shop. By checking wafer performance of both OPC model matrix items and complicated 2D
structures, the conclusion can be drawn that different mask shops can share the same OPC model with rigorous mask
calibration. This methodology leads to lower engineering costs, shorter turn around time (TAT) and robust OPC
performance.
Integration of OPC and mask data preparation for reduced data I/O and reduced cycle time
Author(s):
Ray Morgan;
Manoj Chacko;
Dan Hung;
Johnny Yeap;
Mathias Boman
Show Abstract
As process geometries continue to shrink to the 45nm node and beyond, the resulting increases in design complexity and
chip pattern density have fueled a data explosion on advanced semiconductor designs. This extends product
development cycles and potentially impacts product yield.
Two areas in the design flow that are most adversely affected include both mask synthesis (OPC, RET) and Mask Data
Preparation. Minimizing data I/O and providing an integrated optical proximity correction (OPC) and mask data
preparation solution (MDP), plays an increasingly critical role in reducing the mask synthesis and mask data prep total
cycle time.
In this paper, an integrated flow of Proteus OPC and CATS MDP are discussed. This integrated flow virtually eliminates
the data I/O step between OPC and MDP pre-processing and delivers faster total turn around time by effectively
eliminating the time originally spent on MDP pre-processing. The integrated flow and its turn around time performance
will be presented.
Mask rule check using priority information of mask patterns
Author(s):
Kokoro Kato;
Yoshiyuki Taniguchi;
Kuninori Nishizawa;
Masakazu Endo;
Tadao Inoue;
Ryouji Hagiwara;
Anto Yasaka
Show Abstract
Association of Super-Advanced Electronics Technologies (ASET) has started a project called "Mask Design, Drawing
and Inspection Technology (MaskD2I)" with the sponsorship from The New Energy and Industrial Technology Development Organization (NEDO) since 2006. SIINT has joined the MaskD2I project and we have been developing MRC software considering DFM information for more effective data verification. By converting design level information
called as "Design Intent" to the priority information of mask manufacturing data called as "Mask Data Rank (MDR)", the
MRC process based on the importance of reticle patterns is possible. Our main purpose is to build a novel data checking
flow with the priority information of mask patterns extracted from the design intent. In this paper, we address the effectiveness of MRC technologies which have been widely applied in many mask data
fields. Then we present the current status of the new MRC development, its experimental results so far and the future
outlook using further Design Aware Manufacturing (DAM) information.
Improving the efficiency of pattern extraction for character projection lithography using OPC optimization
Author(s):
Hirokazu Nosato;
Tetsuaki Matsunawa;
Hidenori Sakanashi;
Masahiro Murakawa;
Tetsuya Higuchi
Show Abstract
This paper proposes an approach to improving pattern extraction efficiency for character projection lithography
(CPL). CPL is a promising technology for electron beam direct-write lithography. The advantage of CPL is
the reduced number of electron beam (EB) shots compared to conventional variably-shaped beam lithography,
because character patterns that frequently appear within a layout can be simultaneously written by a single EB
shot with a CP aperture mask. This means that it is important to extract frequently-used character patterns
and prepare CP aperture masks in order to reduce the number of EB shots. However, with random logic devices,
each character pattern is subject to being deformed into many different patterns that have complicated optical
proximity correction (OPC) features, which cannot be extracted as a unique CP aperture mask. In order to
overcome this problem, we propose a method of improving the efficiency of pattern extraction for CPL with
random logic devices by employing OPC optimization. Our proposed method can reduce the variety in the
deformed patterns with two developed cell-based algorithms: (1) a cell grouping algorithm that categorizes
differentiated cells and extracts some typical cell groups, and (2) an OPC optimization algorithm that regards
the cells in a group as one typical cell and corrects for the OPC features of a typical cell to form a CP aperture
mask. In conducted experiments, we successfully achieved a 30% improvement in extraction efficiency.
A user-programmable link between data preparation and mask manufacturing equipment
Author(s):
Weidong Zhang;
Grant Davis;
Emile Sahouria;
Steffen Schulze;
Mohammed Saad;
Arne Seyfarth;
Eric Poortinga
Show Abstract
In order to fully exploit the design knowledge during the operation of mask manufacturing equipment, as well as to
enable the efficient feedback of manufacturing information upstream into the design chain, close communication links
between the data processing domain and the machine are necessary.
With shrinking design rules and modeling technology required to drive simulations and corrections, the amount and
variety of measurements, for example, is steadily growing. This requires a flexible and automated setup of parameters
and location information and their communication with the machine.
The paper will describe a programming interface based on the Tcl/Tk language that contains a set of frequently
reoccurring functions for data extraction and search, site characterization, site filtering, and coordinate transfer. It
enables the free programming of the links, adapting to the flow and the machine needs. The interface lowers the effort
to connect to new tools with specific measurement capabilities, and it reduces the setup and measurement time. The
interface is capable of handling all common mask writer formats and their jobdecks, as well as OASIS and GDSII data.
The application of this interface is demonstrated for the Carl Zeiss AIMSTM system.
32nm half pitch node OPC process model development for three dimensional mask effects using rigorous simulation
Author(s):
Lawrence S. Melvin III;
Thomas Schmoeller;
Jianliang Li
Show Abstract
32 nm half-pitch node processes are rapidly approaching production development, but most tools for this process are
currently in early development. This development state means that significant data sets are not yet readily available for
OPC development. However, several physical mask effects are predicted to become more prominent at the 32 nm half-pitch
node. One of the most significant effects is the three dimensional (3D) mask effects where the mask transmittance
and phase are impacted by the mask topography. Already at larger process nodes this effect impacts imaging
performance, especially when sub-resolution assist features are employed. For the 32nm node it is essential that this
effect is correctly captured by the OPC model. As wafer data for the 32nm half-pitch is difficult to obtain, the use of
rigorous lithography process simulation has proven to be invaluable in studying this effect. Using rigorous simulation,
data for OPC model development has been generated that allows the specific study of 3D mask effect calibration. This
study began with Kirchhoff based simulations of 32 nm node features which were calibrated into Hopkin's based OPC
process models. Once the standard Kirchhoff effects were working in the OPC model, 3D mask effects were included
for the same data by performing fully rigorous electromagnetic field (EMF) simulations on the mask.
OPC verification on cell level using fully rigorous mask topography simulation
Author(s):
Vitaly Domnenko;
Thomas Klimpel;
Georg Viehoever;
Hans Koop;
Lawrence S. Melvin III;
Thomas Schmoeller
Show Abstract
Starting with the 45nm node, the minimum feature size on the mask has reached sub-wavelength dimension. In this
regime the electromagnetic field induced in the mask is significantly impacted by the mask topography. These so called
mask topography effects play an important role in the image formation process and need to be compensated for in the
optical proximity correction (OPC) model. Looking ahead to the 32nm process node, mask topography effects will
become even more pronounced. So, including these effects into the OPC model has become a must for advanced process
nodes. Modern OPC engines start to apply electromagnetic field (EMF) compensation techniques to take these effects
into account. Of course, due to the severe run time constrains for OPC models most EMF aware OPC models need to
rely on approximate methods. A reliable OPC verification process needs to include a fully rigorous treatment of the mask
topography effects with taking into account oblique light incidence and polarization of light. In this paper we investigate
the impact of rigorous mask topography simulation on the reliability of OPC verification and determine the influence of
EMF aware OPC models on OPC quality. We use lithography simulations on OPCed layout cells where we apply a fully
rigorous parallelized EMF solver to the mask model. Two different OPC models are used in this study; one based on the
conventional approach and another one using EMF compensation techniques. The results of the rigorous lithography
simulations are used to verify both OPC models. The impact of the EMF simulation on OPC verification quality is
illustrated by direct comparison with the corresponding Kirchhoff simulations for both OPC models.
A study of haze generation as thin film materials
Author(s):
Ju-Hyun Kang;
Han-Sun Cha;
Sin-Ju Yang;
Chul-Kyu Yang;
Jin-Ho Ahn;
Kee-Soo Nam;
Jong-Min Kim;
Manish Patil;
Ik-Bum Hur;
Sang-Soo Choi
Show Abstract
For high quality products in the semiconductor and photomask industries, exposure wavelength has been shortening
from i-line to ArF to embody the high resolution as critical dimension (CD) shrinkage and the specifications have been
restricted. However, a new defect issue called haze has appeared that is shortening the wavelength. This defect is caused
by the photoreaction of chemical residues exposed to SO4
2-, NH4
+ and other chemicals. Accordingly, in this paper we
investigated the generation of haze in thin film materials.
For fabrication of various thin films, the materials which were metal, compound material without nitrogen, and
compound material with nitrogen, were deposited on a quartz substrate using sputtering. Then, we chemically treated the
thin film materials using various conditions including sulfuric peroxide mixture (SPM) and standard cleaning (SC-1).
First, the concentration of ions on the thin film materials was measured using ion chromatography (IC) analysis. Second,
haze defects were inspected after exposure in order to evaluate the difference in haze generation on the thin film
materials. Also, we investigated the numbers and shape of the occurrences of haze.
A method to determine the origin of remaining particles after mask blank cleaning
Author(s):
Vivek Kapila;
Sean Eichenlaub;
Abbas Rastegar;
Arun John;
Pat Marmillion
Show Abstract
Extreme ultraviolet lithography (EUVL) is a strong contender for the 32 nm generation and beyond. A defect-free mask
substrate is an absolute necessity for manufacturing EUV mask blanks. The mask blank substrates are, therefore,
cleaned with different cleaning processes to remove all defects down to 30 nm. However, cleaning suffers from the
defects added by various sources such as the fab environment, chemicals, ultra pure water, and the cleaning process
itself. The charge state of the substrate during and after cleaning also contributes to the number of adder defects on the
substrate. The zeta potentials on the substrate surface and the defect particles generated during the cleaning process
determine whether the particles get deposited on the surface. The zeta potential of particle or substrate surfaces depends
on the pH of the cleaning fluids. Therefore, in this work, pH-zeta potential maps are generated for quartz substrates
during the various steps of mask cleaning processes. The pH-zeta potential maps for defect particles commonly seen on
mask substrates are measured separately. The zeta potential maps of substrate and contaminant particle surfaces are
used to determine whether particles are attracted to or repulsed from the substrate. In practice, this technique is
especially powerful for deriving information about the origin of particles added during a cleaning process. For example,
for a known adder with a negative zeta potential, all cleaning steps with a positive zeta potential substrate could be the
source of added particles.
Haze generation effect by pellicle and packing box on photomask
Author(s):
Jong-Min Kim;
Manish Patil;
Woo-Gun Jeong;
Ik-Boum Hur;
Cheol Shin;
Sung-Mo Jung;
Moon-Hwan Choi;
Sang-Soo Choi
Show Abstract
ArF exposure tool have been implementing as a main work force of lithography. And haze generation by high actinic
wavelength energy is big issue to be resolved. Many studies have been reported to remove or minimized ion residual on
photomask surface and PKL developed haze free process. Even though the surface of photomask is free from ions
generating haze defect by haze free process, but the ions from environment like pellicle and packing box make worsen to
keep cleanness of photomask. The evaluation of environment effect like outgas from pellicle and packing box have been
reported, but it was hard to know pure environmental effect because the surface of photomask was not enough clean to
test it.
Several pellicles and boxes with different material from supplies were tested in terms of outgas, contamination of ion and
threshold energy generating haze. Some material of packing box and pellicle showed very sensitive to keep haze free
photomask surface.
Laser shockwave cleaning of EUV reticles
Author(s):
N. A. Lammers;
A. Bleeker
Show Abstract
Particles on the surface of the EUV reticle can cause serious imaging errors during exposure. Laser shockwave
cleaning is a novel cleaning method, that shows great potential to remove these particles, without destroying
the delicate surface of the reticle. In an effort to assess the cleaning performance of this method, a number of
cleaning experiments were performed on wafers contaminated with glass spheres. These experiments showed that
with the current setup, it was possible to remove particles as small as 500 nm from the surface of the wafer, at
gap distances of 0.5 and 1.0 mm. Furthermore, the transient behaviour of the shockwave was studied with laser
flash shadowgraphy. This showed that the shockwave is initially elliptical in shape, and that it can be described
by the Taylor and Sedov solution for a point explosion.
Mask protection from a haze during shipping and storage
Author(s):
T. Umeda;
H. Kawashima D.V.M.;
T. Miho;
K. Moriya
Show Abstract
We searched for low-outgassing and electroconductive polymer, found that polycarbonate with carbon fiber
(PC+CF) was good material as mask case. The amount of gas generation from PC+CF was less than 1/10 of the
conventional PMMA material. We also measured the performance of chemical absorbent (PureAID®) too. This
absorbent was effective in removing generated carbon gas from the case and penetrated acid, base and carbon (ABC)
gasses into it. The PureAID® mainteined clean condition in the case while shipping and storage. Functional filter
was designed for mask shipping by air plane. The functional filter removed more than 90% ABC gasses. We
recommend that the case for mask protection from a haze should adopt low-outgassing polymer composition,
chemical absorbent and functional filter. RSP6025-A mask shipper and new concept of RSP150 are adopted these
items.
CD-signature evaluation using scatterometry
Author(s):
Jan Richter;
Phillipp Laube;
John Lam
Show Abstract
The current abilities for active feedback loops to correct for various parameters challenge metrology groups to
provide exact input data for these correction cycles. One of the most important feedback loops is the one that
deals with the improvement of the CD (critical dimension) uniformity of structures. Here, several processes
rely on exact metrology data to tackle systematic effects that either have to be overcome by finding better
process conditions or compensated actively, for instance, by tuning the writer data.
Right now most of these processes tackle long range effects on the order of millimetres and do not vary a lot
on the micrometer scale. On the other hand, CD measurements are usually performed with instruments that
measure single points with dimensions of a couple of micrometers (such as the conventional CD-SEM). Thus
noise from the micrometer scale is introduced in the global mapping of the uniformity.
Recently, numerical methods, such as the exponentially weighted penalty approach called TPS (thin plate
splines) have been developed that separate between the true signatures on the millimetre scale from the noise
of the micrometer measurements. In this paper, we will take one step further by showing that the acquired
statistically stable CD signature of a CD-SEM measurement matches the CD data measured by a
scatterometer. Furthermore, we will show that the residual of the CD data of the scatterometer measurement
compared to the found TPS fit has a noise level of about 0.1 nm (3σ), which essentially equals the short-term
reproducibility of the tool. This is of high importance since both methods do essentially the same - they
average out micrometer noise with the only difference being that TPS does it theoretically and a scatterometer
does experimentally. Thus, we have the extremely fortunate situation in which theory and experiment give the
same results. Hence, two separate conclusions can be drawn: the scatterometer measures indeed stable
macroscopic CD signatures and TPS is indeed the right method to extract these signatures from any given CD
data.
Parameter sensitive patterns for scatterometry monitoring
Author(s):
Jing Xue;
Yu Ben;
Chaohao Wang;
Marshal Miller;
Costas J. Spanos;
Andrew R. Neureuther
Show Abstract
This paper proposes a new highly sensitive scatterometry based Probe-Pattern Grating Focus Monitor. The high
sensitivity is achieved by placing transparent lines spaced at the strong focus spillover distance of around 0.6λ/NA from
the centerline of a 90 degree phase-shifted probe line that functions as an interferometer detector. The monitor translates
the focus error into the probe line trench depth, which can be measured by scatterometry techniques. Simulations of
optical imaging, resist development and Optical Digital Profilometry measurements are used to evaluate the expected
practical performance. A linear model is developed to estimate focus error based on the measured probe trench depth.
The results indicate that the ODP measurement from a single wafer focus setting can detect both the defocus direction
and the defocus distance to well under 0.1 Rayleigh unit of defocus.
Long-term critical dimension measurement performance for a new mask CD-SEM, S-9380M
Author(s):
Zhigang Wang;
Kock Khuen Seet;
Ritsuo Fukaya;
Yasuhiro Kadowaki;
Noriaki Arai;
Makoto Ezumi;
Hidetoshi Satoh
Show Abstract
To realize good repeatability in CD measurements, many issues have to be addressed including system stability, sample
charging and contamination, measurement conditions, and image processing. The S-9380M is a mask CD-SEM (Critical
Dimension Scanning Electron Microscope) system developed for measurement and inspection of 45 nm node photomask.
The S-9380M has several innovations like a newly designed optical system to minimize sample charge-up and drift
effects, ultra-high resolution (3nm) imaging to enable measurements at high magnification, and an integrated ultra-violet
(UV) unit for pre-treatment of the mask to rid the surface of organic contaminants. This paper presents measurements
carried out using the S-9380M system, and showed that superior performance is achieved with short-term dynamic
repeatability of 3σ less than 0.6 nm (for line patterns), and long-term dynamic repeatability of 3σ less than 1.0 nm
without trend modification.
The study for close correlation of mask and wafer to optimize wafer field CD uniformity
Author(s):
Munsik Kim;
Jaesung Kang;
Shinchul Kang;
Goomin Jeong;
Yongkyoo Choi;
Oscar Han
Show Abstract
As device pattern size is shrinking to below 65nm on wafer, the small amount of CD variation on wafer field determine the wafer yield. Most of the wafer field CD variations come from mask CD variations across mask field. By correction of dose and transmittance on mask using wafer field CD variation, wafer CD uniformity can be extremely enhanced. To get fine correction of wafer field CD uniformity, we have developed various methods to get close correlation of mask and wafer field CD uniformity by SEM, scatterometry and area CD methods. Especially, area CD from CD-SEM and optical CD measurement tools are developed to represent each area of masks. By optimizing measurement methods, repeatability and correlation of CD uniformity between masks and wafers are enhanced to get more than 0.7 of correlation between mask and wafer. And these give us the correction method to compensate field CD variation of maskCD on wafer. More than mask CD uniformity requirement on 65nm tech of DRAM memory device has been achieved.
Development of a captured image simulator for the differential interference contrast microscopes aiming to design 199 nm mask inspection tools
Author(s):
Masataka Shiratsuchi;
Yoshinori Honguh;
Ryoichi Hirano D.D.S.;
Riki Ogawa;
Masatoshi Hirono;
Takehiko Nomura
Show Abstract
Recently, technologies of ArF laser exposure tools and alternating phase shifting masks (Alt-PSM) are expected to be
used in actual production. To utilize such newly developed technologies, it is inevitable to develop a mask inspection
technology to check them properly. But it is currently difficult to check them precisely because sufficient image contrast
is hard to obtain with any conventional mask inspection tools. Among many observation methods, the differential
interference contrast (DIC) is one of a few methods that can be used to observe a differentiated phase shift of transmitted
light of an object with high resolution. To study precisely the performance of this optical configuration, we built a new
captured image simulator in which Wollaston prisms were modeled as a kind of phase modulation plates. We built this
simulator as an extension of the captured image simulator we reported formerly), which is based on Rigorous Coupled-
Wave Analysis (RCWA) to calculate diffractions; this enables us to properly treat effects of polarization, high NA,
and 3-dimensional mask structures. We applied this simulator to see sensitivities of DIC against bumps and divots with
various sizes. We found that the image contrast for small phase defects 20 to 50 nm in sizes is much higher in DIC
microscopes than in conventional optical setup with coherence factor less than 1. We also found the dependence of
captured images on polarizations and optical axis directions. We expect our simulator to be a useful tool for studying,
designing, and developing mask inspection tools.
Mask CD control (CDC) with ultrafast laser for improving mask CDU using AIMS as the CD metrology data source
Author(s):
Guy Ben-Zvi;
Eitan Zait;
Vladimir Dmitriev;
Erez Graitzer;
Gidi Gottlieb;
Lior Leibovich;
Robert Birkner;
Klaus Boehm;
Thomas Scheruebl
Show Abstract
CD uniformity control by ultrafast laser system writing inside the bulk of photomasks has previously been shown to be
an effective method for local CD Control (CDC) [1].
Intra-field CD variations correction has been implemented effectively in mask-shops and fabs based on CDC SEM [2, 3]
and OCD as the CD data source. Using wafer CD data allows correction of all wafer field CD contributors at once, but
does not allow correcting for mask CD signature alone. In case of a mask shop attempting to improve CDU of the mask
regardless of a particular exposure tool, it is a better practice to use mask CD data by itself as the CD data source.
We propose using an aerial imaging system AIMSTM45-193i as the mask CD data source for the CDC process.
In this study we created a programmed CD mask (65nm dense L/S) with relatively large CD errors. The programmed CD
mask was then measured by AIMSTM45-193i (AIMS45) which defined the CDU map of the programmed CD mask. The
CDU data from AIMSTM45-193i was then used by Pixer CDC101 to correct the CDU and bring it back to a flat almost
ideal CDU.
Improvements in model-based assist feature placement algorithms
Author(s):
Benjamin Painter;
Levi D. Barnes;
Jeffrey P. Mayhew;
Yongdong Wang
Show Abstract
Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.
An approach of auto-fix post OPC hot spots
Author(s):
Ching-Heng Wang;
Qingwei Liu;
Liguo Zhang
Show Abstract
With the design rule shrinks rapidly, full chip robust Optical Proximity Correction (OPC) will definitely need longer
time due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more
difficult. For, the critical dimension of the design features is deeply sub exposure wavelength, and there is only
limited room for the OPC correction. Usually very complicated fragment commands need to be developed to handle
the shrinking designs, which can be infinitely complicated. So when you finished debug a sophisticated fragment
scripts, you still cannot promise that the script is universal for all kinds of design. So when you find some hot spot
after you apply OPC correction for certain design. The only thing you can do is to modify your fragmentation script
and try to re-apply OPC on this design. But considering the increasing time that is needed for applying full chip OPC
nowadays, re-apply OPC will definitely prolong the tape-out time. We here demonstrate an approach, through which
we can automatically fix some simple hotspots like pinch, bridging. And re-run OPC for the full chip is not necessary
now. However, this work is only the early study of the auto-fix of post OPC hot spots. There is still a long way need
to go to provide a perfect solution of this issue.
3D mask modeling with oblique incidence and mask corner rounding effects for the 32nm node
Author(s):
Mazen Saied;
Franck Foussadier;
Jérôme Belledent;
Yorick Trouiller;
Isabelle Schanen;
Emek Yesilada;
Christian Gardin;
Jean Christophe Urbani;
Frank Sundermann;
Frédéric Robert;
Christophe Couderc;
Florent Vautrin;
Laurent LeCam;
Gurwan Kerrien;
Jonathan Planchot;
Catherine Martinelli;
Bill Wilkinson;
Yves Rody;
Amandine Borjon;
Nicolo Morgana;
Jean-Luc Di-Maria;
Vincent Farys
Show Abstract
The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
Model-based mask verification
Author(s):
Frank Foussadier;
Frank Sundermann;
Anthony Vacca;
Jim Wiley;
George Chen;
Tadahiro Takigawa;
Katsuya Hayano;
Syougo Narukawa;
Satoshi Kawashima;
Hiroshi Mohri;
Naoya Hayashi;
Hiroyuki Miyashita;
Y. Trouiller;
F. Robert;
F. Vautrin;
G. Kerrien;
J. Planchot;
C. Martinelli;
J.L. Di-Maria;
Vincent Farys
Show Abstract
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.
Inverse lithography technology (ILT): keep the balance between SRAF and MRC at 45 and 32 nm
Author(s):
Linyong Pang;
Yong Liu;
Thuc Dam;
Kresimir Mihic;
Thomas Cecil;
Dan Abrams
Show Abstract
In this paper, we present the Luminescent's ILT approach that can rapidly solve for the optimal photomask design. We
will discuss the latest development of ILT at Luminescent in the areas of sub-resolution assist feature (SRAF) generation
and optimization to improve process window, and mask rule compliance (MRC). Results collected internally and from
customers demonstrate that ILT is not only an R&D tool, but also a tool quickly maturing for production qualification at
advanced technology nodes. By enforcing the proper constraints while optimizing the masks, ILT can improve process
windows while maintaining mask costs at a reasonable level.
More robust model built using SEM calibration
Author(s):
Ching-Heng Wang;
Qingwei Liu;
Liguo Zhang
Show Abstract
More robust Optical Proximity Correction (OPC) model is highly required with integrated circuits' CD (Critical
Dimension) being smaller. Generally a lot of wafer data of line-end features need to be collected for modeling.
Scanning Electron Microscope (SEM) images are sources that include vast 2D information. Adding SEM images
calibration into current model flow will be preferred. This paper presents a method using Mentor Graphics' Calibre
SEMcal and ContourCal to integrated SEM calibration into model flow. Firstly simulated contour is generated and
aligned with SEM image automatically. Secondly contour is edited by fixing the gap etc. CD measurement spots are
applied also to get a more accurate contour. Lastly the final contour is extracted and inputted to the model flow. EPE
will be calculated from SEM image contour. Thus a more stable and robust OPC model is generated. SEM calibration
can accommodate structures such as asymmetrical CDs, line end pullbacks and corner rounding etc and save a lot of
time on measuring line end wafer CD.
Safe interpolation distance for VT5 resist model
Author(s):
Walid Tawfic;
Mohamed Al-Imam;
George E. Bailey
Show Abstract
As the technology shrinks toward 65nm technology and beyond, Optical Proximity Correction (OPC) becomes more
important to insure proper printability of high-performance integrated circuits. This correction involves some
geometrical modifications to the mask polygons to account for light diffraction and etch biasing. Model-based OPC has
proven to be a convenient, accurate, and efficient methodology. In this method, raw calibration data are measured from
the process. These data are used to build a VT5 resist model [1] that accounts for all proximity effects that attendant to
the lithography process. To ensure the reliability of the calibrated VT5 model, these data must be broad in the image
parameter space (IPS) to account for different one-dimensional and two-dimensional features for the design intent.
Failure to provide sufficient IPS (i.e. mimic the design intent) coverage during model calibration could result in
marginalizing the VT5 model during OPC, but is difficult to judge when there is enough data volume to safely
interpolate and extrapolate design intent. In this paper we introduce a new metric called Safe Interpolation Distance
(SID). This metric is a multi-dimensional metric which can be used to automatically detect the portions of the target
design that are not covered well by the desired VT5 model.
The effect of the OPC parameters on the performance of the OPC model
Author(s):
Amr Abdo;
Ahmed Seoud;
Alexander Wei;
Ian Stobert;
Alan Leslie
Show Abstract
Model based optical proximity correction (MB-OPC) is essential for the production of advanced integrated circuits
(ICs). As the speed and functionality requirements of IC production necessitate continual reduction of the critical
dimension (CD), there is a heightened demand for more accurate and sophisticated OPC models.
The OPC is applied to the design data through a rule deck. The parameters in this rule deck, which we will call
"setup parameters", describe the fundamental way in which the OPC engine will distinguish which edges to move,
their restrictions to movement, and how the targets for the OPC are chosen. The optimization of these setup
parameters, by customizing how the OPC engine should treat specific designs, is an essential step that is performed
in order to maximize the benefit of the OPC model. Improper or deficient selection of the setup parameters strongly
affects the success or failure of the OPC model and engine to achieve the desired design shapes.
In this paper, the ability of setup parameter optimization to compensate for a weak OPC model, or conversely, how
inadequately selected setup parameters can cause a very good OPC model to function poorly is investigated. Our
approach is to use two OPC models: a good OPC model and a weak OPC model. The setup parameters will be
optimized for the weak OPC model to investigate any improvements in the overall OPC performance. Alternatively,
setup parameters chosen poorly will be used with the good OPC model to see how this will adversely affect the OPC
performance. A comparative study will be carried out in order to fully understand the effect of setup file parameters
on the overall OPC performance.
The general goal of this study is to help the OPC modelers and setup parameters optimizers to improve the quality
and performance of the OPC solution and weigh the tradeoffs associated with different OPC solution choices.
Modeling scanner signatures in the context of OPC
Author(s):
Qiaolin Zhang;
Jacek K. Tyminski;
Kevin Lucas
Show Abstract
The requirement for OPC modeling accuracy becomes increasingly stringent as the semiconductor industry enters sub-
0.1um regime. Targeting at capturing the IC pattern printing characteristics through the lithography process, an OPC
model is usually in the form of the first principle optical imaging component, refined by some phenomenological
components such as resist and etch. The phenomenological components can be adjusted appropriately in order to fit the
OPC model to the silicon measurement data. The optical imaging component is the backbone for the OPC model, and it
is the key to a stable and physics-centric OPC model.
Scanner systematic signatures such as illuminator pupil-fill, illuminator polarization, lens aberration, lens apodization,
flare, etc., previously ignored without significant accuracy sacrifice at previous technology nodes, but are playing non-negligible
roles at 45nm node and beyond. In order to ensure that the OPC modeling tool can accurately model these
important scanner systematic signatures, the core engine (i.e. the optical imaging simulator) of OPC simulator must be
able to model these signatures with sufficient accuracy.
In this paper, we study the impact on optical proximity effect (OPE) of the aforementioned scanner systematic signatures
on several 1D (simple line space, doublet line and doublet space) and 2D (dense line end pullback, isolated line end
pullback and T-bar line end pullback) OPC test patterns. We demonstrate that the scanner systematic signatures have
significant OPE impact on the level of several nanometers. The predicted OPEs and impact from our OPC simulator
matches well with results from an industry standard lithography simulator, and this has laid the foundation of accurate
and physics-centric OPC model with the systematic scanner signatures incorporated.
Modeling polarized illumination for OPC/RET
Author(s):
Hua Song;
Qiaolin Zhang;
James Shiely
Show Abstract
Recent research has shown that properly polarized light source enhances image contrast in photolithography for
manufacturing integrated circuit (IC) devices, thus improves the effectiveness of optical proximity correction (OPC) and
other resolution enhancement techniques (RET). However, current OPC/RET modeling software can only model the
light source polarization of simple types, such as TE, TM, X, Y, or sector polarization with relatively simple
configuration. Realistic polarized light used in scanners is more complex than the aforementioned simple ones. As a
result, simulation accuracy and quality of the OPC result will be compromised by the simplification of the light source
polarization modeling in the traditional approach. With ever shrinking CD error budget in the manufacturing of IC's at
advanced technology nodes, more accurate and comprehensive light source modeling for lithography simulations and
OPC/RET is needed.
In this paper, we present a modeling framework that takes arbitrarily polarized light source. Based on polarization state
vector descriptions of the light source, it unifies optical simulations of unpolarized, partially polarized, and completely
polarized illuminations. We built this framework into Synopsys' OPC modeling tool ProGen. Combined with ProGen's
existing capability to handle vectorial aberration by the projection lens, large angle effects due to high NA, and thin film
effects, this framework represents a general vectorial model for optical imaging with the state-of-the-art scanners.
Numerical experiments were performed to study CD impact of various illumination polarization modeling schemes in
the context of OPC/RET.
Fundamental study on the error factor for sub 90nm OPC modeling
Author(s):
Hyesung Lee;
Sang-Uk Lee;
Jeahee Kim;
Keeho Kim
Show Abstract
In low-k1 imaging lithography process it is difficult to make the accurate OPC model not only because of factors caused
by unstable process such as large CD (Critical Dimension) variation, large MEEF (Mask Error Enhancement Factor) and very poor process window but also because of potential error factors induced during OPC model fitting. In order to minimize those issues it is important to reduce the errors during OPC modeling. In this study, we have investigated the most influencing error factors in OPC modeling. At first, through comparing influence of optical parameters and illumination systems on OPC runtime and model accuracy, we observe main error factor. Secondly, in the case of resist modeling, OPC runtime and model accuracy were also analyzed by various model forms.
OPC development in action for advanced technology nodes
Author(s):
Anthony Chunqing Wang;
Masashi Fujimoto;
Paul J. M. van Adrichem;
Ingo Bork;
Hiroshi Yamashita
Show Abstract
In leading edge technologies, Optical Proximity Correction (OPC) plays a critical role in the total imaging flow. Large
investments in terms of time and engineering resources are made to obtain the required models and recipes to get the OPC
job done. In the model building area, the metrology component is becoming more and more critical. Questions like which
structures to put in a calibration pattern, how to measure, where to measure them, and how often has a serious impact on
the calibration dataset, and thus on the final model.
Corner rounding starts to become an increasingly important factor in imaging and device performance. Because of
this, the model 2D behavior needs to be verified as the least, using reliable metric. In this paper two techniques are
described.
Finally the cost of model building is discussed. When the number of measurements for a model calibration is
considered, available machine time almost always plays a key role. In this paper, a slightly different approach is made on
this problem by looking at the cost of the different components of model calibration, and how that is going to progress in
the process generations to come.
Industry survey of wafer fab reticle quality control strategies in the 90nm-45nm design-rule age
Author(s):
Russell Dover
Show Abstract
Reticle quality control in wafer fabs is
different from quality control in mask shops. Mask
shop requirements are typically inspectability of
mask-type, resolution and sensitivity, with the latter
usually being the most important. Mask shop
sensitivity requirements are also fairly absolute. All
defects or imperfections of a certain specification
have to be found 100 percent of the time, every time.
Wafer fab requirements are an interplay between
inspectability, sensitivity, and the economic cost of
inspection versus the economic risk of not
inspecting. Early warning and defect signatures
versus absolute capture of all defects is a key
distinction between wafer fabs and mask shops. In
order to better understand the different strategies and
approaches taken by wafer fabs for reticle quality
control an industry-wide benchmark survey of
leading wafer fabs was undertaken. This paper
summarizes the results while retaining the different
wafer fabs' anonymity and confidentiality. The
approach taken for the survey was specifically
designed to be impartial and independent of any
tools, solutions or applications available from KLA-Tencor.
Shuttle fabrication for designs with lifted I/Os
Author(s):
Rung-Bin Lin;
Meng-Chiou Wu;
Shih-Cheng Tsai
Show Abstract
The mask set for a shuttle run (multi-project wafer) may contain designs using different number of metal layers. Wafers
fabricated with k metal layers can only yield dice for the designs using only k metal layers. This results in considerable
waste of wafers. In this paper we propose a simple concept called Lifted-I/O (LIO) to address this problem. LIO elevates
the I/Os of all designs to the highest metal layer possibly used in a shuttle run. Our study shows that a shuttle run with
LIO for low-volume production is marginally better than that without LIO. However, the margin increases as production
volume increases. For a production volume up to a few ten thousand dice per design, a shuttle run with LIO could pay up
to 11% less, which corresponds to about 400 thousand dollars.
Development status of EUVL mask blanks in AGC
Author(s):
Kazuyuki Hayashi
Show Abstract
Extreme ultraviolet lithography (EUVL) is a leading candidate for lithographic technology to fabricate the next
generation devices with a 32 nm feature size or smaller. The production of the defect-free mask blanks is one of the key
technologies to realize the EUVL. The EUV mask blanks requires various kinds of properties such as a low thermal
expansion coefficient and an ultra-low flatness of the substrate, a high and uniform reflectivity at EUV wavelength and a
ultra-low defectivity down to 30 nm in the reflective multilayer film, and so on. Asahi Glass Company (AGC) has
employed its own high quality glass synthetic technology, the glass polishing technology, the glass cleaning technology
and film-coating technology acquired for electronic and optical devices to develop the EUV mask blanks. In this paper,
we report on the current status of the EUVL mask blank development in AGC. We demonstrated <50 nm flatness on both
sides and ~10 defects >60 nm on low thermal expansion material (LTEM) substrate. We also demonstrated a Mo/Si
multilayer and a Ru capping layer-coated mask blanks with ~10defects >83 nm and ~65% reflectivity at EUV
wavelength. New Ta-based absorber materials and antireflective layers were also developed. Their superior optical
properties at the wavelength of the mask pattern inspection light were shown in comparison with the current
conventional TaN absorber layer and TaON AR layer. AGC can provide full-stack EUVL mask with this new absorber
material for the process developments with the alpha-demo EUV exposure tools.
Performance of actinic EUVL mask imaging using a zoneplate microscope
Author(s):
Kenneth A. Goldberg;
Patrick P Naulleau;
Anton Barty;
Senajith B. Rekawa;
Charles D. Kemp;
Robert F Gunion;
Farhad Salmassi;
Eric M. Gullikson;
Erik H. Anderson;
Hak-Seung Han M.D.
Show Abstract
The SEMATECH Berkeley Actinic Inspection Tool (AIT) is a dual-mode, scanning and imaging extreme-ultraviolet (EUV) microscope designed for pre-commercial EUV mask research. Dramatic improvements in image quality have been made by the replacement of several critical optical elements, and the introduction of scanning illumination to im-prove uniformity and contrast. We report high quality actinic EUV mask imaging with resolutions as low as 100-nm half-pitch, (20-nm, 5× wafer equivalent size), and an assessment of the imaging performance based on several metrics. Modulation transfer function (MTF) measurements show high contrast imaging for features sizes close to the diffraction-limit. An investigation of the illumination coherence shows that AIT imaging is much more coherent than previously anticipated, with σ below 0.2. Flare measurements with several line-widths show a flare contribution on the order of 2-3% relative intensity in dark regions above the 1.3% absorber reflectivity on the test mask used for these experiments. Astigmatism coupled with focal plane tilt are the dominant aberrations we have observed. The AIT routinely records 250-350 high-quality images in numerous through-focus series per 8-hour shift. Typical exposure times range from 0.5 seconds during alignment, to approximately 20 seconds for high-resolution images.
The effect of size and shape of sub-50 nm defects on their detectability
Author(s):
Abbas Rastegar;
Wonil Cho;
Eric Gullikson;
Sean Eichenlaub
Show Abstract
The capability of SEMATECH's Lasertec M7360 inspection tool to detect particles of different sizes and composition was studied on the surface of fused silica and MoSi multilayers (MLs) with a Si cap layer. Particles of Au, Ag, SnO2, Fe2O3, and Al2O3 were deposited and inspected 10 times with the M7360. Tool pixel size histograms were used to calculate the average pixel size per particle category. The calibration curves of pixel size for polystyrene latex (PSL) spheres were used to convert the average pixel size to the optical size of the defects as detected by the M7360. Selective sets of each category of particles then were reviewed by atomic force microscope (AFM) to calculate the sphere equivalent volume diameter (SEVD) of the particles. The contribution of the surface on which particles were deposited and defect composition and shape were studied. Our results indicate that for Fe2 O3 and SnO particles, size distribution on the surface of fused silica and MLs is similar and no effect of the substrate was observed. The AFM-measured SEVD size of particles were close to the nominal size of particles specified by the particle supplier. Optical size of particles were found to be larger or smaller than SEVD size for the different particles. In the case of the Au particles, the PSL equivalent optical size was found to be larger than the SEVD in good agreement with the modeling. By using prefabricated rectangular defects on a fused silica surface, we showed that the M7360 differentiates between the PSL and SEVD size of prefabricated defects. The PSL size is smaller than the SEVD size of prefabricated defects for particle sizes below 100 nm.
Techniques to measure force uniformity of electrostatic chucks for EUV mask clamping
Author(s):
Sathish Veeraraghavan;
Jaewoong Sohn;
Kevin T. Turner
Show Abstract
Extreme ultraviolet lithography (EUVL) has stringent requirements on image placement (IP) errors in order to allow for
the patterning of devices with critical dimensions (CD) in the sub-32 nm regime. A major contributor to IP error in
EUVL is non-flatness of the mask. Electrostatic chucks are used to support and flatten masks in EUVL scanners.
Proper operation requires that the electrostatic forces generated by the chuck be of sufficient magnitude and be uniform
over the entire chucking area. Hence, there is a need to measure the clamping pressure distribution to properly
characterize performance of electrostatic chucks. This paper discusses two methods to measure electrostatic pressure
magnitude and uniformity by examining the distortion of thin substrates (wafers) during chucking. In the first method, a
wafer with lithographically defined mesas is chucked with the mesas located at the interface between the wafer and the
chuck and thus results in a void near the mesa after chucking. Analytical and finite element models were used to relate
the resulting void radius to the electrostatic pressure and used to assess the feasibility of the technique. Measurements of
pressure on a slab chuck were conducted to demonstrate the mesa measurement approach. The second measurement
method examines the deflection of a wafer between pins on a pin chuck in order to estimate the local pressure. A 3D FE
model was developed to predict the deformation of the wafer between the pins as a function of applied pressure. The
model was used to assess the feasibility of the approach and provide guidance on selecting appropriate substrates for use
in such experiments.
A study of precision performance and scan damage of EUV masks with the LWM9000 SEM
Author(s):
Isao Yonekura;
Hidemitsu Hakii;
Takashi Yoshii;
Yoshiyuki Negishi;
Katsumi Oohira;
Koichirou Kanayama;
Masashi Kawashita;
Yo Sakata;
Keishi Tanaka
Show Abstract
EUV mask is a reflection-type-mask, of which film and structure are very different from those of existing masks (e.g.
Cr and MoSi). LWM9000 SEM of Vistec/Advantest was used for measurement of EUV masks. Two types of EUV
masks were used to investigate static and dynamic measurement precision and the impact of charge-up by e-beam
irradiation during measurement. An optional function of LWM9000 SEM was used to improve static precision.
Because the LWM9000 SEM uses ozone for in-situ cleaning of the work chamber, the interaction between the electron
beam and ozone presence was also investigated. The EUV mask was evaluated at the EUV wavelength before and after
e-beam scanning and measurements to determine any changes in reflectance.
EUV mask substrate flatness improvement by laser irradiation
Author(s):
Kiwamu Takehisa;
Jun Kodama;
Haruhiko Kusunose
Show Abstract
We demonstrate a new technique for improvement of the flatness of the EUV mask substrate by using a pulsed laser.
Laser pulses from an ArF excimer laser were focused inside a quartz mask substrate to make spots. Experiments
showed that the substrate surface was locally swelled out where spots were formed just beneath the surface without
making any damages on the surface. This surface shape control technique can be applied to the final adjustment of the
substrate flatness control since no cleaning process is necessary afterward.
Evaluation of EUVL-mask pattern defect inspection using 199-nm inspection optics
Author(s):
Tsuyoshi Amano;
Yasushi Nishiyama;
Hiroyuki Shigemura;
Tsuneo Terasawa;
Osamu Suga;
Hideaki Hashimoto;
Norio Kameya;
Shingo Murakami;
Nobutaka Kikuiri
Show Abstract
In this paper, we will report two evaluation results. One is the relationship between EUVL mask structure and image
contrast values captured by 199nm inspection optics. The other is the influence of mask structure on defect inspection
sensitivity.
We utilized a commercially available DUV inspection system that has the shortest inspection wavelength at 199nm.
Using the 199nm inspection optics, enough image contrast values on hp32nm 1:1 lines and spaces using ArF-half tone
(HT) mask were obtained. On the other hand, image contrast values were not sufficient for conventional EUVL mask
that have a 70nm absorber layer thickness. To improve the contrast values of mask pattern image, we evaluated the
effect of absorber layer thickness on inspection image contrasts. As a result, reducing the thickness of the absorber layer
to 44nm, enough image contrast values of hp32nm 1:1 lines and spaces patterns were obtained.
In this paper, the influence of the thickness of absorber layer on inspection sensitivities for opaque and clear extension
defects are also discussed.
Study of impacts of mask structure on hole pattern in EUVL
Author(s):
Nobuyuki Iriki;
Yukiyasu Arisawa;
Hajime Aoyama;
Toshihiko Tanaka
Show Abstract
In this paper we focus exclusively on hole process. The motivation here is to investigate on the
performance of EUVL for hole patterning in relation to contributions from mask, exposure tool, and resist
process. For this purpose we use a waveguide simulation package that is capable of computing 3-D mask
structure at very fast speed. We investigated the patterning characteristics of arrayed holes influenced by mask
structure that involve absorber thickness and sidewall angle. Regarding the absorber thickness, we found in
our preliminary process window evaluation that thinner absorber mask requires lower dose than thick absorber
mask does. As lowering of dose is important for the development of cost effective EUVL technology, we have
intensively investigated impacts of thin mask on printability. As it turned out that thin absorber mask
evaluated in this paper required not only reduced dose but also exhibited improved process window. At the
same time we confirmed that top CD of mask pattern is sensitive to required dose even though bottom
reflection area of hole pattern happen to remain constant. The contributing parameters in shaping the side wall
are top CD, bottom CD, and thickness of the absorber. In this paper we studied the combined behavior of these
parameters that we call 3-D mask error impact. In Selete infrastructure, the technologies of EUVL for
realizing full field exposure system are developed using a small field exposure tool (SFET). Using this tool,
experimental hole formation was carried out. We also introduce simulations based on experiments.
Repair specification study for half-pitch 32-nm patterns for EUVL
Author(s):
Hajime Aoyama;
Tsuyoshi Amano;
Yasushi Nishiyama;
Hiroyuki Shigemura;
Osamu Suga
Show Abstract
One of the key issues in extreme ultraviolet lithography (EUVL) is the influence of defects on a mask because of the
high printing resolution of EUVL. In order to address this issue, it is necessary to estimate the critical size of an absorber
pattern defect and that of a repaired defect. The repair of an opaque defect by milling or of a clear defect by deposition
might not be perfect; so the area, height, and optical constant of the repair material must be taken into consideration. By
estimating the threshold of calculated aerial images, the critical dimension (CD) that can be printed was found to equal
the square root of the defect area. For the repair of opaque defects, residual Ta was found to be more likely to cause poor
printing than the etching of the multilayer by excessive milling. Since a clear defect is repaired with Ta with the same
optical properties as the absorber material, the CD error in printing is mainly caused by the repair of a CD error and is
not caused by an error in height that is less than ±25% of the height of the Ta absorber. The optimal optical constant of
the repair material was estimated by varying the refraction coefficient from 0.9199 to 0.9999 and the extinction
coefficient form 0.0001 to -0.0451. We found that carbon is a useful repair material that provides a CD error of at most
±0.5 nm around a defect with an area of 64 nm because the maximum refraction should be below 0.97.
EUV mask process development using DUV inspection system
Author(s):
David Kim;
Venu Vellanki;
William Huang;
Andrew Cao;
Chunlin Chen;
Aditya Dayal;
Paul Yu;
Ki Hun Park;
Yumiko Maenaka;
Kazuko Jochi;
Gregg Inderhees
Show Abstract
As the design rule continues to shrink towards 3x nm and below, lithographers are searching for new and
advanced methods of mask lithography such as immersion, double patterning and extreme ultraviolet
lithography (EUVL). EUV lithography is one of the leading candidates for the next generation lithography
technologies after 193 nm immersion and many mask makers and equipment makers have focused on
stabilizing the process. With EUV lithography just around the corner, it is crucial for advanced mask makers
to develop and stabilize EUV mask processes. As a result, an inspection tool is required to monitor and
provide quick feedback to each process step.
Development of EUV mask fabrication process using Ru capping blank
Author(s):
Tsukasa Abe;
Takashi Adachi;
Shiho Sasaki;
Hiroshi Mohri;
Naoya Hayashi;
Kosuke Ishikiriyama
Show Abstract
Extreme Ultra Violet Lithography (EUVL) is considered to be a major candidate for the Next Generation
Lithography. To achieve reflective optics, EUV mask consists of absorber layer, reflective multilayer (ML) with
protection capping layer. Buffer layer can be used for silicon capped EUV blanks to enhance the etch selectivity
against absorber etching.
It has been reported that Ruthenium (Ru) material has better property on oxidation resistance
compared to standard silicon (Si) capping layer. Ru capping layers have advantage for its high etch selectivity, which
enables buffer layer free EUV mask structure. However, thin Ru layers should be designed due to high EUV
absorption property.
This paper includes the evaluation of current process performance of Ta-based absorber process on Ru capped ML
blanks. It also includes resist patterning by EB writing, Ru capping layer etch effect as well as absorber patterning
with CD uniformity, linearity, Line Edge Roughness (LER) and selectivity between absorber and resist or Ru capping
layer. Inspection result is also included as a recent result.
Metrology for templates of UV nano imprint lithography
Author(s):
Kouji Yoshida;
Kouichirou Kojima;
Makoto Abe;
Shiho Sasaki;
Masaaki Kurihara;
Hiroshi Mohri;
Naoya Hayashi
Show Abstract
Templates for UV-Nano-imprint lithography (NIL) have developed aggressively. Feature sizes of the templates have
come to less than 30 nm. Therefore metrology is also one of challenging items to fabricate templates for UV-NIL.
However, there are many issues in metrology for the templates, for instance, necessity of the further resolution for
measurement tools, charging issues without conductive layers for a SEM.
In this paper, we will focus on metrology of the templates for UV-NIL. And also some measurement techniques are
described about detail results using scanning probe microscope, CD-SEM, scattermetry and so on.
UV-NIL templates for the 22nm node and beyond
Author(s):
Takaaki Hiraka;
Satoshi Yusa;
Akiko Fujii;
Shiho Sasaki;
Kimio Itoh;
Nobuhito Toyama;
Masaaki Kurihara;
Hiroshi Mohri;
Naoya Hayashi
Show Abstract
NIL (nano-imprint lithography) is expected as one of the lithographic candidates for 32nm node and beyond.
Recently, the small line edge roughness (LER) as well as the potentially high resolution that will ensure no-OPC mask
feature is attracting many researchers. However, the NIL needs 1X patterns on template and a transit from 4X to 1X is a
big and hard technology jump for the mask industry. The fine resolution pattern making on the template is one of the
most critical issues for the realization of NIL.
In this paper, as a continuation of our previous works1-5, we have achieved further resolution by optimizing
the materials, their thicknesses, the developing and the etching processes, as well as the writing parameters of the
100keV SB (spot beam) writer. At the best resolved point on the template, resolutions down to hp (half pitch) 18nm on
dense line patterns, hp20nm on dense hole patterns, and hp26nm on dense dot patterns were confirmed. Concerning
stable pattern resolution over a certain field area, we evaluated pattern resolution through over a 250um square area,
which we think would be adequate for initial imprint tests. For the 250μm square area, we confirmed pattern resolution
of hp24nm for dense line patterns and hp32nm for dense hole patterns.
In addition, we have studied resolution limit of the 50keV VSB (variable shaped beam) photomask
production writing tools, which have been commonly used tools in the 4X photomask manufacturing for larger field size
patterning. Materials, process conditions and parameters acquired through the 100keV SB process were implanted, and
we could fabricate templates with hp32nm dense line patterns, with acceptable full chip uniformity and writing time.
We also studied the imprint capability, and fabricated a template with fine features and imprinted it onto a
wafer. As a result, we could transfer hp24nm dense line patterns, hp24nm dense hole patterns, and hp32nm dense dot
patterns onto the wafer.
A study of template cleaning for nano-imprint lithography
Author(s):
James E. Ellenson;
Lloyd C. Litt;
Abbas Rastegar
Show Abstract
Nanoimprinting lithography (NIL) is being evaluated as a possible method for meeting lithography requirements for
semiconductor imaging at 32nm half-pitch nodes and below. NIL is included in the International Technology Roadmap
for Semiconductors (ITRS) as a potential choice for advanced lithography. In this technology, the template, or mold, is a
critical component in achieving the requirements for feature size and defectivity. Since NIL is a contact imaging
technique, one of the issues is the high probability of defects while imprinting. Since the template is in contact with a
fluid during the imaging process, maintaining the required template cleanliness needed to met the ITRS requirements
without damaging or changing critical dimensions is an important process. In this paper we discuss the results obtained
from several different NIL template cleaning methods using SEMATECH's Mask Blank Development Center facilities.
The effectiveness of different operating conditions as well as several different chemistries is compared.