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Design and Process Integration for Microelectronic Manufacturing III
Editor(s): Lars W. Liebmann

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Volume Details

Volume Number: 5756
Date Published: 5 May 2005

Table of Contents
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Integrating DfM components into a cohesive design-to-silicon solution
Author(s): Lars Liebmann; Dan Maynard; Kevin McCullen; Nakgeuon Seong; Ed Buturla; Mark Lavin; Jason Hibbeler
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Using yield-focused design methodologies to speed time-to-market
Author(s): Marc Levitt
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Design process optimization, virtual prototyping of manufacturing, and foundry-portable DFM
Author(s): James Hogan; Christopher Progler; Ahmad Chatila; Bert Bruggeman; Mitchell Heins; Robert Pack; Victor Boksha
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Integrated circuit DFM framework for deep sub-wavelength processes
Author(s): J. A. Torres; C. N. Berglund
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Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era
Author(s): Mary Jane Brodsky; Scott Halle; Vickie Jophlin-Gut; Lars Liebmann; Don Samuels; Gary Crispo; Kourosh Nafisi; Vijay Ramani; Ingrid Peterson
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Inspection of integrated circuit databases through reticle and wafer simulation: an integrated approach to design for manufacturing (DFM)
Author(s): William Howard; Jaione Tirapu Azpiroz; Yalin Xiong; Chris Mack; Gaurav Verma; William Volk; Harold Lehon; Yunfei Deng; Rui-fang Shi; James Culp; Scott Mansfield
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Introduction of a die-to-database verification tool for the entire printed geometry of a die: geometry verification system NGR2100 for DFM
Author(s): Tadashi Kitamura; Kazufumi Kubota; Toshiaki Hasebe; Futoshi Sakai; Shinichi Nakazawa; Neeti Vohra; Masahiro Yamamoto; Masahiro Inoue
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Investigation of model-based physical design restrictions
Author(s): Kevin Lucas; Stanislas Baron; Jerome Belledent; Robert Boone; Amandine Borjon; Christophe Couderc; Kyle Patterson; Lionel Riviere-Cazaux; Yves Rody; Frank Sundermann; Olivier Toublan; Yorick Trouiller; Jean-Christophe Urbani; Karl Wimmer
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MAID: manufacturing aware IC design
Author(s): Louis K. Scheffer
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Design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization
Author(s): Lei He; Andrew B. Kahng; King Ho Tam; Jinjun Xiong
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Optical extensions integration for a 0.314-µm2 45-nm node 6-transistor SRAM cell
Author(s): Staf Verhaegen; Axel Nackaerts; Vincent Wiaux; Eric Hendrickx; Geert Vandenberghe
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Manufacturing-aware design methodology for assist feature correctness
Author(s): Puneet Gupta; Andrew B. Kahng; Chul-Hong Park
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Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches
Author(s): Nishrin Kachwala; Walter Iandolo; Travis Brist; Rick Farnbach
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Geometrical analysis of product layout as a powerful tool for DFM
Author(s): Thomas Roessler; Joerg Thiele
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Toward through-process layout quality metrics
Author(s): Fook-Luen Heng; Jin-Fuw Lee; Puneet Gupta
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Correlation analysis of CD-variation and circuit performance under multiple sources of variability
Author(s): Amir Borna; Chris Progler; David Blaauw
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Modeling within-field gate length spatial variation for process-design co-optimization
Author(s): Paul Friedberg; Yu Cao; Jason Cain; Ruth Wang; Jan Rabaey; Costas Spanos
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Advanced timing analysis based on post-OPC patterning process simulations
Author(s): Jie Yang; Luigi Capodieci; Dennis Sylvester
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Model-based verification for first time right manufacturing
Author(s): James A. Bruce; Edward W. Conrad; Gregory J. Dick; D. John Nickel; Jacek G. Smolinski
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Building an infrastructure for parametric yield analysis: concept and implementation of a DFM platform
Author(s): John Gookassian; Bob Pack; Mitch Heins; John Garcia; Hitendra Divecha; Brian Gordon; Dean Frazier; Dan White; Gurgen Lachinyan; Brian Dillon; Christophe Suzor; Anthony Adamov; Kyung-Youl Min; Sergei Bakarian; Rafik Marutyan; Victor Boksha
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Lithography simulation system for total CD control from design to manufacturing
Author(s): Toshiya Kotani; Hirotaka Ichikawa; Sachiko Kobayashi; Shigeki Nojima; Kyoko Izuha; Satoshi Tanaka; Soichi Inoue
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Design and process limited yield at the 65-nm node and beyond
Author(s): Kevin Monahan; Brian Trafas
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Assessing the impact of real world manufacturing lithography variations on post-OPC CD control
Author(s): John L. Sturtevant; J. Word; P. LaCour; J. W. Park; D. Smith
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Detecting focus-sensitive configurations during OPC
Author(s): Lawrence S. Melvin III; James P. Shiely; Qiliang Yan
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DFM in practice: results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90-nm FPGA chip
Author(s): Chun-Chi Yu; Ming-Feng Shieh; Erick Liu; Benjamin Lin; Henry Lin; Manoj Chacko; Xiaoyang Li; Wen-Kang Lei; Jonathan Ho; Xin Wu
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Design rule considerations for 65-nm node contact using off axis illumination
Author(s): Scott Jessen; Mark Mason; Sean O'Brien; Mark Terry; Robert Soper; Thomas Wolf
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Lithography yield check for IC design
Author(s): Lynn Cai; Ting Chen
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Improving model-based OPC performance for the 65-nm node through calibration set optimization
Author(s): Kyle Patterson; Yorick Trouiller; Kevin Lucas; Jerome Belledent; Amandine Borjon; Yves Rody; Christophe Couderc; Frank Sundermann; Jean-Christophe Urbani; Stanislas Baron
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New OPC methods to increase process margin for sub-70nm devices
Author(s): Ji-Suk Hong; Dong-Hyun Kim; Sang-Wook Kim; Moon-Hyun Yoo; Jeong-Taek Kong
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Mask cost analysis via write time estimation
Author(s): Yuan Zhang; Rick Gray; Seurien Chou; Barry Rockwell; Guangming Xiao; Henry Kamberian; Rand Cottle; Alex Wolleben; Chris Progler
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Device and lithography contextual mask rule generation
Author(s): Young Mog Ham; Brian Dillon; Chris Progler; Kory Goldammer; Zhiziang Jin; Gary Green; R. Scott Mackay; Hitendra Divecha; Victor Boksha; Pat Martin; Mitch Heins; Yuan Zhang; Kurt Davis; Rafik Marutyan; Karen Martirosyan; Sergei Bakarian
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Process centering OPC using design intent to improve yield
Author(s): Michel Cote; Alexander Miloslavsky; Robert Lugg; Michael L. Rieger; Philippe Hurat
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Evaluating design for manufacturing with process capability analysis
Author(s): Johannes van Wingerden; Laurent Le Cam; Manish Garg; Yuri Aksenov; Peter Dirksen
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The prospects for hierarchical data processing with growing complexity of the post-tapeout flow
Author(s): Steffen Schulze; Emile Sahouria
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Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration
Author(s): Xin Wang; Mark Pillof; Hongbo Tang; Clive Wu
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Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes
Author(s): Song Li; Ting Chen; Santosh Shah; Ketan Joshi; Kalyan Thumaty; Narain Arora
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65nm OPC and design optimization by using simple electrical transistor simulation
Author(s): Yorick Trouiller; Thierry Devoivre; Jerome Belledent; Franck Foussadier; Amandine Borjon; Kyle Patterson; Kevin Lucas; Christophe Couderc; Frank Sundermann; Jean-Christophe Urbani; Stanislas Baron; Yves Rody; Jean-Damien Chapon; Franck Arnaud; Jorge Entradas
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Mask cost reduction and yield optimization using design intent
Author(s): Michel Cote; Alexander Miloslavsky; Philippe Hurat; Michael L. Rieger; Denis Goinard
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Full chip gate CD error prediction for model-based OPC
Author(s): Vincent Yongsheng Shu; Byoung Il Choi; Shyue-Fong Quek
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WAMA: a method of optimizing reticle/die placement to increase litho cell productivity
Author(s): Amos Dor; Yoram Schwarz
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Line end design intent estimation using curves
Author(s): Chi-Yuan Hung; Gensheng Gao; Steven Zhang; Ze-Xi Deng; Christopher Cork; Lawrence S. Melvin III; Yan Jiang
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A novel design-process optimization technique based on self-consistent electrical performance evaluation
Author(s): Valery Axelrad; Andrei Shibkov; Gene Hill; Hung-Jen Lin; Cyrus Tabery; Dan White; Victor Boksha; Randy Thilmany
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Considerations for the use of defocus models for OPC
Author(s): John L. Sturtevant; J. A. Torres; J. Word; Y. Granik; P. LaCour
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