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Design and Process Integration for Microelectronic Manufacturing II
Editor(s): Lars W. Liebmann

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Volume Details

Volume Number: 5379
Date Published: 3 May 2004

Table of Contents
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DFM: magic bullet or marketing hype?
Author(s): Joseph D. Sawicki
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The rising cost and complexity of RETs
Author(s): Mark E. Mason
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High-performance circuit design for the RET-enabled 65-nm technology node
Author(s): Lars W. Liebmann; Arnold E. Barish; Zachary Baum; Henry A. Bonges; Scott J. Bukofsky; Carlos A. Fonseca; Scott D. Halle; Gregory A. Northrop; Steven L. Runyon; Leon Sigal
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Minimizing mask complexity for advanced optical lithography
Author(s): Michael Fritze; Brian Tyrrell
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Manufacturability of the X Architecture at the 90-nm technology node
Author(s): Michael C. Smayling; Robin C. Sarma; Toshiyuki Nagata; Narain Arora; Michael P. Duane; Shiany Oemardani; Santosh Shah
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Taking the X Architecture to the 65-nm technology node
Author(s): Robin C. Sarma; Michael C. Smayling; Narain Arora; Toshiyuki Nagata; Michael P. Duane; Santosh Shah; Harris J. Keston; Shiany Oemardani
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Standard cell design with regularly placed contacts and gates
Author(s): Jun Wang; Alfred K. K. Wong; Edmund Y. Lam
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Forbidden-area avoidance with spacing technique for layout optimization
Author(s): Shi Chang Shi; Alfred K. Wong; Tung-Sang Ng
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Feature level test patterns for characterizing residual process effects
Author(s): Andrew R. Neureuther; Gregory R. McIntyre; Frank E. Gennari; Michael Lam; Jason P. Cain; Garth C. Robins; Edward Huang; Jihong Choi; Ling Wang; Lei Yuan; Hideaki Oshima
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A methodology to analyze circuit impact of process-related MOSFET geometry
Author(s): Artur Balasinski
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DFM through correct process construction
Author(s): Qi-De Qian
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Impact of lithography variability on statistical timing behavior
Author(s): Christopher J. Progler; Amir Borna; David Blaauw; Pierre Sixt
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Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology
Author(s): K. Honda; K. Peter; Y. Zhang; B. Yu; K. Park; Xiaolei Li; K. Michaels; Shinichi Yamada; T. Noguchi
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Manufacturing-aware design methodologies for mixed-signal communication circuits
Author(s): Juan Antonio Carballo; Sani Nassif
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Yield-enhanced layout generation by new design for manufacturability (DfM) flow
Author(s): Toshiya Kotani; Satoshi Tanaka; Shigeki Nojima; Koji Hashimoto; Soichi Inoue; Ichiro Mori
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Taming pattern and focus variation in VLSI design
Author(s): Fook-Luen Heng; Puneet Gupta; Kafai Lai; Ronald L. Gordon; Jin-Fuw Lee
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OASIS-based data preparation flows: progress report on containing data size explosion
Author(s): Steffen F. Schulze; Pat LaCour; Laurence Grodd
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Combining OPC and design for printability into 65-nm logic designs
Author(s): Kevin D. Lucas; Chi-Min Yuan; Robert Boone; Kirk Strozewski; Jason Porter; Ruiqi Tian; Karl Wimmer; Jonathan Cobb; Bill Wilkinson; Olivier Toublan
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Interaction of RET and MDP: optimization for reducing the mask writing time
Author(s): James Word; Steffen F. Schulze
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Merits of cellwise model-based OPC
Author(s): Puneet Gupta; Fook-Luen Heng; Mark A. Lavin
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Extending aggressive low-k1 design rule requirements for 90-nm and 65-nm nodes via simultaneous optimization of NA, illumination, and OPC
Author(s): Sabita Roy; Douglas J. Van Den Broeke; J. Fung Chen; Armin Liebchen; Ting Chen; Stephen D. Hsu; Xuelong Shi; Robert John Socha
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Image fidelity verification: contourIFV
Author(s): Ioana Graur; Rama N. Singh; Donald J Samuels
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Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent
Author(s): Christopher M. Cork; Pratheep Balasingam; Sonya Sandvik; Bill Kielhorn; Michael L. Rieger
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A 65-nm node SRAM solution using alt-PSM with ArF lithography
Author(s): Frank A.J.M. Driessen; Mary T. Zawadzki; Prakash R. Krishnan; Artur Balasinski; Geert Vandenberghe
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Optimization of interconnection layout for multitransistor cell shrinkability
Author(s): Bartosz Banachowicz; Oliver Pohland; Artur Balasinski
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Designing high-performance cost-efficient embedded SRAM in deep-submicron era
Author(s): Olga Kobozeva; Ramnath Venkatraman; Ruggero Castagnetti; Franklin Duan; Arvind Kamath; Shiva Ramesh
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Layout modification for library cell Alt-PSM composability
Author(s): Ke Cao; Jiang Hu; Mosong Cheng
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Patterning sub-50-nm Fin-FET using KrF lithography tool
Author(s): Navab Singh; S. Jagar; Sohan Singh Mehta; Moitreyee Mukherjee Roy; Rakesh Kumar; N. Balasubramanian
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CMP dummy pattern insertion with reduction in power supply voltage drops
Author(s): Kiyohito Mukai; Junichi Shimada; Mitsumi Ito; Masanori Hirofuji; Hiroyuki Tsujikawa
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Statistical analysis of poly line printability affected by sPSM manufacturing errors
Author(s): Nadya Belova; John V. Jensen; Saied Khodabandeh; Ebo H. Croffie
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Hybrid AAPSM compliance methodology to ensure design for manufacturing
Author(s): Vishnu G. Kamat; Alexander Miloslavsky; Vinod K. Malhotra; Jeffrey P. Mayhew; Michel L. Cote
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