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Microelectronic Yield, Reliability, and Advanced Packaging
Editor(s): Cher Ming Tan; Yeng-Kaung Peng; Mali Mahalingam; Krishnamachar Prasad

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Volume Details

Volume Number: 4229
Date Published: 23 October 2000

Table of Contents
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Electromigration failure modes and Blech effect in single-inlaid Cu interconnects
Author(s): Stacye R. Thrasher; Cristiano Capasso; Larry Zhao; Richard Hernandez; Peggy Mulski; Stewart Rose; Timothy Nguyen; Hisao Kawasaki
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Resistance degradation in early stage of electromigration of Al(Cu) metal lines
Author(s): Qiang Guo; Keng Foo Lo; Indrajit Manna; Xu Zeng; Bin Bin Jie
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Dependence of EM performance on linewidth for Cu dual-inlaid structures
Author(s): Larry Zhao; Cristiano Capasso; Amit P. Marathe; Stacye R. Thrasher; Richard Hernandez; Peggy Mulski; Stewart Rose; Timothy Nguyen; Martin Gall; Hisao Kawasaki
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Novel algorithm for hot-carrier lifetime projection on thick gate PMOSFETs fabricated by 0.18-um CMOS technology
Author(s): Bin Bin Jie; Indrajit Manna; Xu Zeng; Qiang Guo; Keng Foo Lo
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Finite element analysis and experiments of ultrafine-pitch wire bonding
Author(s): Zhaowei Zhong; Kay Soon Goh
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Use of Rbd to distinguish different failure modes
Author(s): Wei-Ting Kary Chien; Jun Chen Huang; Charles H. J. Huang
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Novel resource optimization approach for yield learning
Author(s): Ramakrishna Akella
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Comprehensive methodology for integrated circuit in-line defect classification
Author(s): Richard L. Guldi; Douglas E. Paradis; Nagarajan Sridhar; Jesse B. Hightower
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Projecting wafer probe yields for products fabricated in new technologies
Author(s): Ron Ross; Nick Atchison
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Yield implications of wafer edge engineering
Author(s): Kenneth Roy Harris; Boon Yong Ang
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Comprehensive study of indium-implantation-induced damages in 0.25-um MOSFETs
Author(s): Hong Liao; Louis Lim; Anthony Lowrie; Chock Hing Gan; Mark Redford
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Fast yield learning using e-beam wafer inspection
Author(s): James F. Garvin Jr.; Richard L. Guldi; Nagarajan Sridhar; Mark Tinker; Robert Cappel; Thomas Cass; Jake Roberts
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Analysis of serious bit-line failure on 0.19-um 64M DRAM with STI technology
Author(s): Chung Lee; Chih-Tung Tang
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Effect of annealing after metal etch on analog device and its impact on yield performance
Author(s): Madhusudan Mukhopadhyay; Teo Yeow Meng; Lim Sieng Ye; Rajan Rajgopal
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Reliability data analysis software development
Author(s): Zhang Guan; Cher Ming Tan
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Test and reliability analysis of PBGA assemblies under random vibration
Author(s): Qingjin Yang; Zhiping Wang; Geok Hian Lim; Hock Lye John Pang; Fook Fah Yap; Rongming Lin
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FEA evaluation on solder joint reliability of CCGA
Author(s): Tim Fai Lam
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Measurement of thermal deformation of IC packages using the AFM scanning moire technique
Author(s): Zhaowei Zhong; Yunguang Lu; Huimin Xie; Bryan Kok Ann Ngoi; Jin Yu; Gin Boay Chai; Anand Krishna Asundi
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Burn-in strategy based on Weibull failures
Author(s): Wei-Ting Kary Chien; Charles H. J. Huang
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New quality control parameter in wafer fabrication for wire-bonding integrity
Author(s): Cher Ming Tan; Zhang Guan
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Estimation of the area of voids in deep-submicron aluminium interconnects using resistance-noise measurements
Author(s): Lip Wei Chu; Kin Leong Pey; Wai Kin Chim; S. K. Loh; E. Er
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Chemical imaging of microvias in flip chip pin grid array packages using time-of-flight secondary ion mass spectroscopy
Author(s): Yoon Loong Khong; Hooi Ling Lee
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CVD Cu/IMP Cu/TaN/SiO2/Si structures
Author(s): Seow Wee Loh; Dao Hua Zhang; Chao Yong Li; Rong Liu; Andrew Thye Shen Wee
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Low-cost wafer level packaging process
Author(s): Rahul Kapoor; Swee Yong Khim; Goh Hin Hwa
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Fracture mechanics approach for flip chip BGA design
Author(s): Jiang-Bo Han
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Thermal characterization of tape BGA package by modeling
Author(s): Jiang-Bo Han
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Crosstalk in packaging array-based optical interconnects and processors
Author(s): Anjan K. Ghosh
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System-level I/O power modeling
Author(s): William P. Pinello; P. R. Patel; Yuang-Liang Li
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