This work demonstrates that we can prevent electro migration failures in single-inlaid copper during DC electro migration testing by taking advantage of the Blech effect. This effect, also known as stres-induced backflow, was coined after IA Blech, who first reported this phenomenon for aluminum metal lines. As the metal ions move toward the anode end of the line, as stress build-up occurs opposing the electron wind, thus constrain the void growth. Therefore, a critical length exists for which no electro migration occurs for a specific current density in metal lines. This Blech effect is evident in lines short enough for the stress to fully inhibit the ovoid evolution. We performed electro migration testing of single-inlaid copper metal lines ranging from 5 to 250 micrometers in length. The testing was performed at 300 degrees C with a stress current density of 1.4 X 10⁶ A/cm². The shorter lines did not show any resistance increase even after hundreds of hours of testing, while the longer lines failed at the same time, independent of the line length. The critical product, was calculated to be between 2800 and 3500 A/cm at 300 degrees C for single-inlaid copper.

Resistance degradation in the early stage of electro migration of Al(Cu) metal lines has been investigated by using high resolution resistance measurement. The resistance variation due to Cu diffusion along the line was separated form that due to the thermal stress in the electro migration test. It was found that Cu diffusion along the line strongly depends on the metal line structure. In a wide line with polycrystalline structure, the resistance drop due to Cu diffusion is linearly increased with the test time. However, as the linewidth is reduced and the line becomes bamboo structure, most of resistance drop is ascribed to the thermal stress and Cu diffusion along the line is almost negligible. This finding indicates that the role of Cu in the electro migration reliability strongly depends on the line structure, and previous theory on the role of Cu in improvement of electro migration reliability can not simply apply to the metal line with bamboo structure.

EM is a diffusion phenomenon under the influence of driving forces. The major diffusion paths for Cu dual inlaid structures are believed to be interfaces and grain boundaries. Cu dual inlaid structures usually have a refractory metal barrier layer and are capped with a dielectric layer. The fastest diffusion path in such a structure is believed to be the Cu-dielectric interface. We studied the relationship between EM behavior and metal line- width for two types of EM test structures. It was found that the median time to failure (MTTF) increased significantly as the metal line-width increased for each type of structures when tested under the same current density. In one case, the MTTF increased by 200 percent as the metal line-width was doubled. Microstructure analysis on the metal lines showed that the wider lines had almost a bamboo structure while the narrower lines consisted of small grains. Therefore, the dramatic decrease in MTTF in the narrower line structure was most likely due to a significant increase in grain boundary diffusion. Mathematical treatment has been performed on the experimental data based on the assumption that the MTTF is reciprocally proportional to the drift velocity or the diffusivity, in this case, of Cu. It has been concluded that grain boundaries can be the fastest diffusion path in Cu dual inlaid structures when the grain size is small.

It is critical how to project hot-carrier lifetime form wafer level hot-carrier injection (HCl) test data, due to the limited stress time. It is well known that both oxide charge formation and interface trap generation affect the degradation of thick gate PMOSFETs fabricated by 0.18 micrometers technology. Based on it, a new fitting mode and the corresponding fitting algorithm were proposed. Form only one experimental curve of any degradation versus stress time under any HCl stress condition, the corresponding fitting curve can be obtained using this model. Form the fitting curve, the hot-carrier lifetime under the corresponding stress condition can be extracted. It is shown here that the model is quite accurate. This algorithm is quite robust to extract HCl lifetime as well.

The demand for increased computing power and more complex IC devices with increased functions per chip results in higher I/O count packaging. With the shrinkage in IC size and the decrease in pad pitch, the trend is moving from the current fine-pitch, such as the 50micrometers and 40micrometers . Given the tight constraint, the bonding process and bonding tool design become more complex, which produces smaller bond deformation in a repeatable manner. Those problems associated with open wire, bond liftoff, surface contamination, etc., have now become more sensitive and difficult to control.

Gate oxide integrity plays an important role in device reliability especially for modern products where high speed and memory capacities are in demand. There are many test methods to ensure gate oxide reliability. After the tests, we usually analyze data by a Weibull or lognormal plot to identify failure mechanisms and to ensure the failures are within the acceptable range. However, in recent years, more and more S-shaped curves are observed especially from a Weibull plot. The S-shaped curve in the Weibull plot may be derived due to more than one failure mode. It is crucial in practice to estimate the lifetime, the percentage, and the failure behavior of Mode A and B, the early and random failures, respectively. In this paper, a methodology to distinguish different failure modes is introduced using the post-breakdown resistance, Rbd, and the extreme-value distributions. The Rbd used in this analysis is defined as 0.5V/Ibd where Ibd is the gate current measured under Vg equals 0.5V after oxide breakdown. By doing so, the percentage of each group can be estimated and failure analysis on samples from different groups can be expedited as the samples with low Rbd are hard breakdowns and the ones with high Rbd are defect-related. By the curve fitting using Weibull and the extreme-value distributions, simple models are proposed for lifetime estimation.

In this paper, we describe a new integrated framework for yield learning, based on linking traditional inspection sampling, and current ADC classification procedures. The elements of a yield learning cycle, and the drivers, are identified. We then review results concerning integrated inspection-classification/review procedures that reduce yield loss detection; these incorporate new optimized control charts that incorporate killer and non-killer defect types, with classification errors, as well as integrated queuing-hypothesis testing approaches combining resource management and excursion detection. We briefly touch upon tactical approaches for achieving source isolation and prioritizing source isolation and root cause analysis.

The earliest attempts by human inspectors to classify defects found during in-line inspection of integrated circuits were fraught with difficulties in clarifying defect definitions and in training a diverse and changing inspector staff. These deficiencies were exacerbated by the challenges of expanding classification categories as new defects were discovered. Our diversified product mix had accumulated a knowledge base of approximately seventy defect types, posing a formidable learning challenge for even the most knowledgeable inspector. Not surprisingly, the average accuracy of the group in classifying defects was approximately 55 percent, and even the best inspector scored around 70 percent. To address these issues, we developed a comprehensive methodology for classifying defects. This methodology includes both word descriptions of the physical appearance of defects and a hierarchical questionnaire leading to precise defect classification. After adopting this methodology and implementing strong training programs, our team significantly improved its defect review process, ultimately reaching approximately 80 percent classification accuracy. With this degree of accuracy, we were able to implement defect specific statistical process control charts, together with formalized 'decision tree' procedures for correcting defect excursions. These formalisms then became an effective part of the fab's yield improvement program. Today, as technology advances into the realm of automatic defect classification (ADC), the lessons learned from human defect inspection form a strong foundation by establishing a comprehensive set of defect categories uniquely related to causality and supporting defect identification standards that can be used by the entire community of ADC training engineers.

It is desirable to be able to forecast wafer probe yields for new products to be fabricated using the next generation technology. This is advantageous to assess the cost effectiveness of developing new technologies as well as to be able to plan wafer starts for these products.

Many uncharacterized phenomena occur at the edge of the wafer. Interactions between film stresses, tool clamp rings, lithography edge exclusions, etch non-uniformities, and CMP non-uniformities are some of the factors that influence the properties of the film stack close to the edge of the wafer. This paper discusses and provides examples of factors that should be considered when characterizing the film stack at the edge of the wafer. Tool interactions, edge exclusions, process non-uniformities, and other porcess variations are presented in this context. A relevant edge-engineering problem is then presented, where a delaminating film at the edge of the wafer contaminated the interior of the wafer. The solution to this problem involved a thorough characterization and redesign of the wafer edge film stacks. The discussion, analysis, and solution of this problem encompass and demonstrate the concepts reviewed in the paper.

In this paper, an investigation of the DC characteristics of 0.25 micrometers indium-implanted MOSFETs concerning on indium implantation induced damages is presented. The experimental data indicates that the devices with indium-implanted channel tend to show increases in device leakage current, which could be attributed the indium implantation induced damages. The impact of the indium implantation on the degradation of device performance was investigated through detailed studies of device I-V characteristics, and the measurement results are found to correlate well with the variations in the process conditions. Our findings indicate that the elimination of the implantation-induced damages by post implantation annealing is particularly important for deep sub-micron MOSFETs using indium implantation.

We report examples of the use of automated e-beam inspection to detect yield or reliability limiting defects which were not seen using conventional optical inspection. In SEM-mode, e-beam inspection affords high resolution and large depth- of-focus to defect detection, making it well suited to inspect sub-0.15 micrometers geometries, even in high aspect ratio structures. This technology can find defects smaller than 0.10micrometers , even on densely packed, high aspect ratio, multi- layer geometries. Moreover, with the high signal-to-noise ratio inherent in SEMSpec technology, defects that are difficult to inspect optically later in the fabrication process due to grainy polysilicon, grainy metal, underlying structural variations, or dielectric thickness non- uniformity causing color changes, etc are easily observed. Another advantage of SEMSpec inspection is the voltage contrast operating mode, which detects electrical failures/defects not visible by optical techniques.

When 0.19um 64M DRAM was been developing that suffered very serious bit line failure. Because it is the first product with shallow trench isolation (STI) technology in VIS, obviously some previous FA experiences in LOCOS is not applicable to this case. After took much effort, finally, cross section/plane view TEM and Wright etching analysis shown there were two root causes. 1) Stress induced dislocation in silicon is the major problem witch always occurs at special layout and induced most of the bit line fail (especially long bit line fail). 2) Poly plug residue from improper IPO1 CMP induced bit line fail.

This paper demonstrates the importance of annealing in presence of forming gas after first layer metal etch in analog devices. A drop of 3 mA analog power supply current has been observed. DC-offset value has also reduced from 40 mV-14mV. Yield performance of the device has improved dramatically. All these lead to the improvement of the device performance and demonstrate the degradation of MOSFET matching circuits and analog capacitors during metal etch.

Reliability is one of the major keys in product development. While reliability test are conducted in almost every manufacturing plant, the analysis of reliability test data is hardly rigorous, and engineers mainly rely on the softwares that come with the reliability test equipment to perform the test data analysis. Although this is usually sufficient, the underlying assumptions of the analysis are seldom known, and misleading conclusions might be resulted. Also, the sample size for a reliability test is generally determined from an engineering specification, and variation cannot be made when special circumstances arise. Furthermore, confidence interval estimation of MTTF and T₅₀, outlier points identification from test data are usually not given. This could make the test data are usually not given. This could make the test analysis meaningful since point estimate can lead to erroneous decision, and so are the outlier points. In addition, a specified distribution, in particular, the exponential distribution is usually assumed in the data analysis. However, in practical problem, reliability test may be affected by other failure mechanisms. Thus, test data could be from mixture of distributions, and different models need to be identified and analyzed separately. Therefore, to ensure that the reliability test data can be analyzed accurately, the analysis must include sample size determination, parameter and confidence interval estimations, outlier point identification, and failure mode identification. Sample size determination is required so that desirable confidence level can be obtai4ned from test data with acceptable confidence interval. Outlier point identification is required so that undesirable data points can be eliminated and correct analysis for the remaining desirable test dat can be done. Failure mode identification is required so that each failure mode can be analyzed separately as they tend to have different life distributions. In this paper, reliability data analysis software developed by us will be presented that take into account of the above-mentioned, and hence an accurate and complete reliability test data analysis can be performed.

To understand the high-cycle reliability of plastic ball grid array (PBGA) interconnections under external random vibration loading, a series of vibration test of PBGA assemblies were conducted. The test vehicle has four PBGA modules assembled on a printed circuit board. The assembly was clamped at two opposite sides on a fixture, which was bolted to a vibration excitation. Firstly, the dynamic properties of the assembly under external random vibration excitation were characterized. The resonant frequencies of the assembly were identified, and the maximum dynamic deflection was estimated. Then the reliability test were carried out. In the reliability tests, the electrical resistance of PBGA modules was continuously monitored, so that any failure could be detected. This paper describes the test procedures, and shows the typical vibration fatigue failures in the PBGA interconnections. Test results will be analyzed in detail.

3D diagonal sliced models for seven combinations of CCGA packages were built. The FEA results show that, the board level reliability of package A with interposer is more than two times better than Package B without interposer. But the improvement should be mainly attributed to the bigger and longer columns used by Package A, instead of the interposer. Bigger and longer column and thicker eutectic joint improve the reliability significantly.

The scanning moire method was suggested in 1980s. A scanning moire method using optical method was proposed in 1993. The scanning lines in the SEM monitor or CCD video camera were utilized as the reference grating to form a scanning moire pattern. The available results are limited to the deformation measurement by using a grating with a frequency less than 250 lines/mm. Thus it is impossible to apply this method to measure deformation in nanometer scale. With the development of micro-mechanics and the appearance of nanometer mechanics, new techniques for deformation measurement form micrometer to nanometer scales are in urgent need.

Burn-in is crucial for ICs, especially for DRAM. To meet the target failure rate after releasing the products to customers, the manufacturers have to burn-in the chips after assembly and FT for a certain period of time to weed-out the weaker parts. It is important to determine the burn-in time and to set-up a re-burn-in strategy to meet required failure rate and to maintain cost-effective at the same time. This paper introduces an innovative approach to achieve these two objectives along with some practical concerns on burn-in at field applications. The proposed methodology can be applied on versatile statistical distributions. In this presentation, the selected failure mechanisms follows Weibull distribution to illustrate our approaches.

The integrity of bondpads is of utmost importance for the functionality and reliability of an IC. It has been found recently that a factor called the localization factor of the underlying poly-silicon surface can affect the bonding integrity. In this work, a quantitative study on the effect of the factor on the wire pull test strength is performed, and quantitative relationship between the distribution of the factor and the distribution of the wire pull test strength is obtained. From the experimental data, it is found that the distribution of the wire pull test strength follows a three-parameter Weibull distribution. The quantitative relationship between the two distributions enables us to deduce the yield loss of the wire pull test strength if the distribution of the factor is known .With this relationship, the distribution of the factor can also be determined from the distribution of the wire pull test, and the reliability of chip due to thermal effect can then be estimated form the distribution of the factor.

Voids can form in aluminium (Al) interconnects as a result of electro migration, stress migration and process-related problems. Such voids can give rise to reliability issues such as an increase in interconnect resistance that increases the RC delay, and localized stress and heating effects, which further enhance electro migration. In this paper, a novel technique to estimate the effective voids area in deep sub-micron Al lines using combined measurements of resistance fluctuation and low-frequency noise is presented. In the proposed mode, fluctuations in voltage at low frequencies, related to resistance-noise fluctuations in the presence of voids in Al lines, were measured under constant-current biasing condition. The noise measurement is known to be more sensitive to device defects and the presence of voids as compared to the conventional technique of resistance measurement alone. A theoretical model that considers the thermal coefficient of resistance in calculating the change in Al line resistance due to the presence of voids and temperature has been developed to extract the effective void area form the experimental data comprising both 1/f noise and resistance variations.

Distribution of chemical species in cross sectioned micro- via were observed using the Time-of-Flight-Secondary-Ion- Mass-Spectroscopy (TOF-SIMS). The TOF-SIMS combines high molecular and elemental detection sensitivities and good lateral resolution for detection of molecular and elemental content in the micro-via and surrounding structures of the flip-chip-pin-grid array packages fabricated from several sources. The data obtained indicate that it is feasible to compare and monitor organic package fabrication processes using TOF-SIMS chemical images.

We report the properties of the copper films deposited by metal-organic chemical vapor deposition (MOCVD) and the interaction between the copper film and its neighbor layer in the Cu/TaN/SiO₂/Si structures upon annealing in a furnace in a nitrogen environment. It is found that the sheet resistance of the copper film slightly decreases as the annealing temperature increases up to 500 degrees C and the increases drastically with the further increase of the annealing temperature. From x-ray diffraction, both CuTa₁₀O₂₆ and TaSi₂ can be observed in the MOCVD Cu/TaN/SiO₂/Si structures at an annealing temperature of 600 degrees C, indicating an interact between the Cu film and the layer underneath. For the structures which have a deposited flash Cu layer between the CVD Cu film and TaN barrier, however, the TaSi₂ cannot be observed. SIMS analysis indicates that the addition of the flash Cu layer also impacts Cu diffusion across the barrier metal due likely to the change in the crystallographic plane of the Cu films.

Today, semiconductors are being connected to other components of the system through three main interconnect technologies - Wirebond, TAB and Solder bump. Of the three technologies, use of solder bump provides the lowest impedance electrical path and a high er I/O density as compared to wirebond and TAB. Wafer bumping is often accompanied by a need for redistribution of the current carrying pads on the silicon in order to reduce the substrate cost and better manufacturing yields, Besides, there is a need to deposit a metallic layer underneath the bump for good reliability of the packaged system. The two widely used processes used for depositing a thin metal film, either for redistribution or UBM are Physical Vapor Deposition and evaporation. These processes are significant contributors to the cost of the bumped wafer. In the packaging industry, there is also a drive for going towards wafers level packaging solutions in order to minimize the packaging cost and giving high production rates.

Die cracking and interfacial delamination are of major failure modes in IC packages. To these crack-related problems, design approaches based on traditional strength theories, are inadequate and insufficient. To achieve a more reliable and robust design, a fracture mechanics approach is needed. In this paper, fracture mechanics is applied to flip chip BGA design, assumed that the major potential failure mode is cracking of die from its backside. Fracture mechanics is integrated with the finite element analysis (FEA) and design of virtual experiments to analyze the effects of location and length of a die crack, and the effects of some key material properties and package dimensions on flip chip BGA reliability in terms of die cracking. The stress intensity factor and the strain energy release rate, are used as the design indices. The FEA is used as a numerical tool to calculate the fracture parameters. And the virtual DOE is employed to determine contributions of each design parameters to die cracking and their acceptable design windows. The investigation consists of three parts. The first is relations of length and location of a die crack with the fracture parameters. The relations are established through sweeping along crack length for a crack located in the center of die backside, and along the die backside surface. The critical crack length is determined. The second is the virtual DOE based on fracture mechanics. Several key material properties and cracking are calculated. From it, some generic design guidelines are made. The third part compares the virtual DOE design results between using the maximum normal stress (MNS) theory and using the fracture mechanics approach. The comparison gives a clear picture of the applicable range of the MNS theory. It is concluded that design optimization be a must in order to achieve a robust package design. Substrate and die thicknesses are the two most significant factors to die cracking of flip chip BGA. Increasing substrate thickness and reducing die thickness are the most effective measures to design a package with high resistance to die cracking. The fracture mechanics approach will produce more accurate design result than the MNS theory.

In microelectronic industry, numerical modeling is an effective way to predict thermal performance of IC packages in the initial development stage. Moreover, thermal simulation can provide a greater understanding of the physics of the problem, allowing design to be optimized quickly and cheaply, thereby shortening packaging development cycle time and keeping expensive experimental measurements to a minimum. In this study, 3D finite element analysis (FEA) thermal models capturing the details of the solder ball and internal structure of the tap BGA package are developed. Accuracy of the developed FEA models is validated by bench marking with the measurement for 35mm by 35mm 352 TBGA package. Numerical results of the thermal performance of the TBGA package under various die size and heat-spreader remaining thickness are presented. The thermal metrics, Theta-JA, Psi-JT, and Psi-JB, of the package are characterized numerically. Relationships between these three thermal metrics are established. These relationships are useful to correlate one thermal parameter of the package to another.

Parallel optical interconnections which replace metallic transmission lines with optical fibers or free space channels provide high throughput, easy system integration, and low latency. Such interconnects are used in the design of multiprocessors and telecommunication central office switches and routers. In all parallel optical interconnects we need to couple a set of laser beams coming out of an array of sources or passing through an array of optical devices to another array of optical devices. Owing to diffraction laser beams spread spatially. So some optical devices in the path of laser beam may receive power from adjacent channels. The power form adjacent channels gives rise to crosstalk noise. In this paper we quantify the amount of optical crosstalk that can corrupt a channel in 2D rectangular arrays of parallel optical interconnects. The worst case signal to crosstalk power ratio in an array of interconnects is calculated as a function of the sizes of the array elements, inter-element spacing and distances. From the analytical results in this paper it is possible to determine guidelines on packaging optical interconnects, free-space or optical fiber-based. The effects of built-in offsets on the crosstalk power can be quantified. The results of this paper are also useful in optimizing the design of various types of extrinsic optical sensors in which cross-coupling or crosstalk is the basis of the sensing process.

A methodology is proposed for the electrical characterization of electronic packages in a system-level environment. Modeling and simulation results show the capability of the method by demonstrating both power delivery and I/O signal integrity analysis in a unified environment. In addition to flexibility, the proposed method is capable of achieving accurate results in a fraction of the time as was previously required.