Share Email Print


Multilevel Interconnect Technology III
Editor(s): Mart Graef; Divyesh N. Patel

*This item is only available on the SPIE Digital Library.

Volume Details

Volume Number: 3883
Date Published: 11 August 1999

Table of Contents
show all abstracts | hide all abstracts
Copper contamination effect on the reliability of devices in the BiCMOS technology
Author(s): Kia Seng Low; Markus Schwerd; Heinrich Koerner; Hans-Joachim Barth; Anthony O'Neil
Show Abstract
Challenges of damascene etching for copper interconnect
Author(s): Paul Kwok Keung Ho; Mei-Sheng Zhou; Subhash Gupta; Ramasamy Chockalingam; Jianxun Li; Ming Hui Fan
Show Abstract
IMP copper seed layer formation with TaN barrier for deep submicron
Author(s): Babu Narayanan; Chao Yong Li; Kangsoo Lee; Bo Yu; Jun Jie Wu; Pang Dow Foo; Joseph Xie
Show Abstract
Influence of IMP copper flash layer on the properties of copper films deposited by metal organic chemical vapor deposition
Author(s): Chao Yong Li; Dao Hua Zhang; Yin Qian; Babu Narayanan; Jun Jie Wu; Bo Yu; Z. X. Jiang; Pang Dow Foo; Joseph Xie; Qinyuan Zhang; Soon Fatt Yoon
Show Abstract
Polymer residue formation in vias caused by plasma etching of underlying titanium-rich films
Author(s): Gus J. Colovos; John F. DiGregorio; Ralph N. Wall
Show Abstract
ILD thermal stability in deep-submicron technologies: from thin to ultrathin dielectric films
Author(s): David T. Hsu; Hyungkun Kim; Frank G. Shi; Bin Zhao; Maureen R. Brongo; P. Schilling; Shi-Qing Wang
Show Abstract
Integration of a high-Q spiral inductor into an existing digital CMOS backend
Author(s): John D. Butler; Clay Crouch
Show Abstract
Integration of Flowfill and Forcefill for cost-effective via applications
Author(s): Werner K. Robl; Juergen Foerster; Uwe Hoeckele; Manfred Frank; David Butler; Paul Rich; K. Beekmann
Show Abstract
Capping layers, cleaning method, and rapid thermal processing temperature on cobalt silicide formation
Author(s): Dinesh Saigal; Gigi Lai; Lisa Yang; Jingang Su; Ken Ngan; Murali K. Narasimhan; Fusen E. Chen; Ajay Singhal; Dave Lopes; Sean Lian; Wanqing Cao; Kevin Tsai; Patrick Lo; Shih-Ked Lee; James Shih
Show Abstract
Defect reduction methodologies for damascene interconnect process development
Author(s): Andrew Skumanich; Man-Ping Cai
Show Abstract
Development and integration of a new metal structuring process for 256 MDRAMs
Author(s): Wolfgang Leiberg; E. Lueken; Sven Schmidbauer; Mirko Vogt; Lothar Bauch; P. Moll; V. Polei; J. Bachmann
Show Abstract
Lithographic CD variation in contact, via, local interconnect, and damascene levels
Author(s): Yorick Trouiller; Anne Didiergeorges; Gilles L. Fanget; Cyrille Laviron; Corinne Comboroure; Yves Quere
Show Abstract
Ultrathin integrated ion metal plasma titanium and metallorganic titanium nitride liners for sub 0.18 um W based metallization schemes for >500 MHz microprocessors
Author(s): Nitin Khurana; Vikram Pavate; Michael Jackson; T. Mandrekar; Z. Fang; Anish Tolia; H. Luo; Jason Li; Rod Mosely; Murali K. Narasimhan; Mei Chang; Fusen E. Chen
Show Abstract
Integrated IMP Ti and MOCVD TiN for 300-mm W barrier and liner for sub-0.18-um IC processing
Author(s): Anish Tolia; Marlon Menezes; Jason Li; Michael Jackson; Vikram Pavate; Nitin Khurana; Rod Mosely; Murali K. Narasimhan; Mei Chang; Fusen E. Chen
Show Abstract
Enabling and cost-effective TiCl4-based PECVD Ti and CVD TiN processes for gigabit DRAM technology
Author(s): Sri Srinivas; Ming Xi; Brian Metzger; Zvi Lando; Murali K. Narasimhan; Fusen E. Chen
Show Abstract
Novel metallization scheme using nitrogen passivated Ti liner for AlCu-based metallization
Author(s): Sven Schmidbauer; Stefan Spinler; M. U. Lehr; J. Klotzsche; J. Hahn
Show Abstract
Comparing the electrical characteristics and reliabilities of BJTs and MOSFETs between Pt and Ti contact silicide processes
Author(s): Kaiping Liu; Ling Shang
Show Abstract

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?