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Microelectronic Device Technology III
Editor(s): David Burnett; Toshiaki Tsuchiya

*This item is only available on the SPIE Digital Library.

Volume Details

Volume Number: 3881
Date Published: 1 September 1999

Table of Contents
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High-K gate dielectrics
Author(s): Wen-Jie Qi; Byoung Hun Lee; Renee Nieh; LaeGu Kang; YongJoo Jeon; Katsu Onishi; Jack C. Lee
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CVD Si1-xGex epitaxial growth and its applications to MOS devices
Author(s): Junichi Murota; Masao Sakuraba; Takashi Matsuura
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Metal gates for advanced CMOS technology
Author(s): Bikas Maiti; Phil J. Tobin
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Characterization of tungsten silicide (WSix) film grown by chemical vapor deposition (CVD)
Author(s): Fazla Rabbi M.B. Hossain; Satheesh Ambadi; Richard Winer; Ken Kitt; Carlos Garcia; Jeff Pearse
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Suppression of floating body effect by controlling potential profile in the lower body region of SOI MOSFETs
Author(s): Yasuhiro Sato; Toshiaki Tsuchiya
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Sub-0.1-um vertical MOS transistor
Author(s): Kiyoshi Mori
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Fabrication of nanometer Schottky-tunneling MOSFETs by a novel silicide nanopatterning method
Author(s): Qing Tai Zhao; L. Kappius; S. Mesters; Siegfried Mantl
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UHF2: a 0.6-um 25-GHz BiCMOS technology for mixed-signal wireless communications applications
Author(s): Don Hemmenway; Frank Baldwin; John D. Butler; Clay Crouch; Jose Delgado; Mike Jayne; Jeffrey M. Johnston; Rex Lowther; Michael Netzer; Susan Richmond; Anthony Rivoli; George Rouse; Ron Santi; Yun Yue
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New high-performance complementary bipolar technology featuring 45-GHz NPN and 20-GHz PNP devices
Author(s): Martin C. Wilson; Peter H. Osborne; Simon Thomas; Trevor Cook
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Hybrid Cu and Al interconnects for high-performance system LSI
Author(s): Hiroshi Kawashima; Motoshige Igarashi; Akihiko Harada; Hiroyuki Amishiro; Noboru Morimoto; Akihiko Ohsaki; Keiichi Higasitani; Hideaki Arima
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Effects of high-density plasma processing on MOSFET matching, noise, and hot carrier reliability
Author(s): Sidhartha Sen; Edward B. Harris; Richard W. Gregor; Samuel Martin; Mahjoub A. Abdelgadir; Rafael N. Barba; Sundar Chetlur; K. Steiner
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Mismatch characterization and modelization of deep-submicron CMOS transistors
Author(s): Helene Thibieroz; Alain Duvallet
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Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-um surface-channel PMOS devices
Author(s): Gregory S. Scott; Samar K. Saha; Christopher S. Olsen; Faran Nouri; Jeffrey Lutze; Mark E. Rubin; Martin Manley
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Improved p-ch MOS transistor performance with an arsenic supersteep retrograde channel profile
Author(s): James F. Buller; Jon Cheek; Dirk Wristers; Daniel Kadoch; Michael Duane
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Performance of submicron CMOS device and logic gates with substrate biasing
Author(s): Xiaomei Liu; Samiha Mourad
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Degradation of PMOS series resistance due to Si implantation for Ti-salicide process
Author(s): Eng-Hua Lim; Soh Yun Siah; Chong Wee Lim; Yong Meng Lee; Jia Zhen Zheng; Ravi Sundaresan; Kin Leong Pey
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Influence of laser annealing conditions on the performance of 0.6-um polysilicon TFTs
Author(s): Mitsuru Chida; Katsuyuki Suga; Yasuyoshi Mishima; Nobuo Sasaki
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Estimation of quantum mechanical and polysilicon depletion effects for ultrathin silicon dioxide gate dielectric
Author(s): G. Srinivasan; Samar K. Saha; G. A. Rezvani
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Gate-length- and threshold-voltage-dependent nonlinearity in the hot carrier DC lifetime extrapolation for sub-100-nm NMOS devices
Author(s): Sejal N. Chheda; Navakanta Bhat; Paul Tsui; Suzanne Gonzales; Nigel Cave; Chong-Cheng Fu; Fred Huang; Amit Nangia; Philip Sung-Joon Choi; Sean Collins
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Effects of indium implant and post-RTA on performance and reliability of sub-100-nm retrograde channel NMOSFETs
Author(s): Qi Xiang; Bin Yu; Geffrey C. F. Yeap; Ming-Ren Lin
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Drain profile engineering for MOSFET devices with channel lengths below 100 nm
Author(s): Samar K. Saha
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Quantitative analysis of SILCs (stress-induced leakage currents) based on the inelastic trap-assisted tunneling model
Author(s): Shiro Kamohara; Yutaka Okuyama; Yukiko Manabe; Kosuke Okuyama; Katsuhiko Kubota; Donggun Park; Chenming Hu
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Stress minimization of corner rounding process during STI
Author(s): Christopher S. Olsen; Faran Nouri; Mark E. Rubin; Olivier Laparra; Gregory S. Scott
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Stress-induced leakage currents of CMOS ULSI devices with shallow trench isolation
Author(s): Ravi Sundaresan; Chock Hing Gan; Igor V. Peidous
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Improvement of ultrathin gate oxide by a novel rapid thermal oxidation process with in-situ steam generation
Author(s): Mo-Chium Yu; Syun-Ming Jang; C. H. Diaz; C. H. Yu; S. C. Sun; M. S. Liang
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Integrated simulation of the plasma-assisted gate oxide nitridation
Author(s): Valeriy Sukharev; Sheldon Aronowitz; Vladimir Zubkov; Helmut Puchner; John Haywood; James P. Kimball
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Deep discrete trenches filled by in-situ doped polysilicon: an alternative method for junction insulating box
Author(s): Fabien Pierre; Said Aachboun; Olivier Bonnaud; H. Lhermite; Pierre Ranson; Christine Anceau; L. Cornibert
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Effect of hydrogenation on the electrophysical properties of ion-doped GaAs
Author(s): Valerii A. Kagadei; Yu V. Lilenko; Dmitrii I. Proskurovsky; L. S. Shirokova
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Optimization of a wet-patterning bottom antireflective i-line coating for both poly gate and metal lithography processes
Author(s): Hubert Enichlmair; Oliver Stelmaszyk; Paul Williams
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Formation of heavily boron-doped nanolayer in silicon by powerful ion irradiation
Author(s): Andrej P. Kokhanenko; Aleksander G. Korotaev; Aleksander V. Voitsekhovskii; Ivan Grushin; Mikhail S. Opekunov; Gennady E. Remnev
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Photoelectric characteristics of inhomogeneous MOS silicon-based structures
Author(s): Aleksander V. Voitsekhovskii; Sergey N. Nesmelov
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Impact of active dimension on junction leakages of a Ti-salicide process integrated with shallow-trench isolation
Author(s): Soh Yun Siah; Eng-Hua Lim; Ming-Jr Shiu; Kong Hean Lee; Jia Zhen Zheng
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Scaling the gate dielectric
Author(s): David J. Eaglesham
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Integration challenges at 0.15-um technology node
Author(s): Farhad Moghadam
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Mainstreaming SOI CMOS technology
Author(s): Ghavam G. Shahidi
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