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Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV
Editor(s): Sharad Prasad; Hans-Dieter Hartmann; Tohru Tsujide

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Volume Details

Volume Number: 3510
Date Published: 28 August 1998

Table of Contents
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Shorter failure analysis using a new application of IDDQ for defect localization in ICs
Author(s): Romain Desplats; Bertrand Fougnie; Philippe Perdu; Jamel Benbrik; Francois Marc; Yves Danto
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Fault diagnosis of CMOS LSI with various leakage current state using abnormal IDDQ phenomenon
Author(s): Masaru Sanada; Hiromu Fujioka
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Improving yield and reliability of FIB modifications using electrical testing
Author(s): Romain Desplats; Jamel Benbrik; Bruno Benteo; Philippe Perdu
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Recognition of defects of the surfscan installation TENCOR 7600 depending on the situation and size of the defect
Author(s): Sven-Olaf Schellenberg; Uwe Herdickerhoff
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Characterization of snap-back breakdown and its temperature dependence up to 300 degrees C including circuit-level model and simulation
Author(s): Dirk Uffmann
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Photolithography expert system for improved estimation of IC critical area
Author(s): Mark P.C. Chia; Gerard A. Allan; Anthony J. Walton
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Proximity effect correction for clock-rate maximization
Author(s): Li Chen; Linda Milor; Charles Ouyang; Wojciech P. Maly; Yeng-Kaung Peng
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Reliability, electrical performance, and properties of solder (63/37)-bumped flip-chip components
Author(s): Petteri Palm; Aulis Tuominen; Jarmo Maeaettaenen; Liisu Uusitalo
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Industrial use of conductive adhesives for SMT assemblies
Author(s): M. G. Perichaud; Helene Fremont; M. Salagoity; C. Faure; Yves Danto
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Implementation of a standardized 0.35-um WLR test vehicle
Author(s): Ehren Achee; Greg Petter; James Reedholm
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Yield improvement via automatic analysis of wafer-processing order
Author(s): Miguel Alonso Merino; Miguel Recio; Julian Moreno; Victorino Martin Santamaria; Almudena Fernandez; Gerardo Gonzalez; Enrique Borrego; Luis J. Barrios; Maria D. del Castillo; Lissette Lemus; Angel L. Gonzalez
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SPRT for Weibull distributed integrated circuit failures
Author(s): Rajarathnam Chandramouli; N. Vijaykrishnan; N. Ranganathan
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Influence of silicon surface integrity on device yield
Author(s): Yasuhiro Kimura; Hideki Naruoka; Morihiko Kume; Toshiharu Katayama; Hidekazu Yamamoto; Yoji Mashiko
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Yield issues with local interconnect
Author(s): Neil Bryan Henis; Scott Bolton; Ruben Montez; James Legg; Sung Kim; Quong Vuong
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Metal-induced oxide degradation studied by surface photovoltage and mercury-probe measurements
Author(s): Antonio Cacciato; S. Evseev; S. Vleeshouwers; I. Rink
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Yield-modeling accuracy requirements for 300-mm processing
Author(s): Daren L. Dance; Christopher W. Long
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Bad vias are the cause for electrical test yield losses after plastic chip assembly
Author(s): Heinz Reiter; Othmar Leitner
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Accurate determination of the hydrogen concentration of silicon nitride layers by Fourier transform spectroscopy
Author(s): Ingrid Jonak-Auer; Friedemar Kuchar
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Failure modes in microelectronic packages
Author(s): Xun Qing Shi; Wei Zhou; Hock Lye John Pang; Zhenfeng P. Wang
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Probe microloading effect of in-situ etch in EPROM stack-gate process
Author(s): Jang Ming Chiou; Sheng Liang Pan; Kai Ming Ching; Bi-Jiang Chang; Kuo-Liang Lu
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Enhanced hot-carrier-induced degradation of 0.25-um P-MOSFETs with oxide/nitride composite spacer compared to those with oxide spacer
Author(s): Vijay Janapaty; Jiunn-Yann Tsai; Sharad Prasad
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Influence of the material properties on the thermal behavior of a package
Author(s): Kirsten Weide; Christian Keck; Xiaoying Yu
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Simulation of charging voltages on a wafer during plasma etch
Author(s): M. Oner; Bharat L. Bhuva; P. Sisterhen; H. Hasan; Sherra E. Kerns
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Effect of different barrier materials on antifuse performance
Author(s): Ting Cheong Ang; Man Siu Tse; Lap Hung Chan; John L. Sudijono
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Microprocessor technology challenges through the next decade
Author(s): George E. Sery
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Copper chip technology
Author(s): Daniel C. Edelstein
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Foundry technology trend
Author(s): Jack Y. C. Sun
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Equipment challenges for a total material system change: enabling device manufacturing at 130 nm and below
Author(s): Alain S. Harrus; John Kelly; Ronald A. Powell
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