Although it is generally accepted that in-line and off-line electrical characterization measurements have value in a semiconductor fab, their actual value to a specific fab depends heavily on a wide variety of parameters such as: the fab's end product and throughput; the sensitivity of the measurements to various process deviations and the implementation cost; etc. This paper will detail some of these dependencies and develop an economic method for the justification of various in-line electrical tests.

Device charging due to ion implantation is studied, using the in-line Plasma Damage Monitor (PDM) and end-of-line measurements by means of in-house processed electrically erasable-programmable memory cells (EEPROM). PDM in-line charging monitoring is a non-contact technique to map the surface potential of a charge dielectric surface. EEPROM end-of-line measurements detect the magnitude of surface potential that has been present on the wafer during ion implantation. Both methods record the same trends in charging experiments in ion implantation processing. Good correlation is found between PDM values and Vt-shifts of EEPROM cells. These results are confirmed by measurements using the well-established technique CHARM-2. The effect of charging induced by ion implantation has been evaluated. Both PDM and EEPROMs can monitor the charging control by a plasma flood system in an ion implanter. The novel in-line technique PDM is found to be a reliable and fast turn-around method for charging control. Also, the EEPROM measurements give a realistic response of the amount of charging that devices experience. Unfortunately, both methods are not accurate enough to fine-tune the PFS settings during ion implantation.

The current trend in the semiconductor industries is to move the reliability tests usually performed at he end of the process flow, towards in the in line monitors. This need opens a new strategic direction for the scanning probe microscopy, permitting to avoid dedicated sample preparation. Among the examples of SPM-scanning tunneling microscope, near-field scanning optical microscope, atomic force microscope, scanning thermal microscope and scanning capacitance microscope - some of them are still under investigation. In this paper a new scanning capacitance microscope able to perform quantitative local in-situ monitor of the silicon oxide properties is being established. The test samples used in this work, were p- doped silicon wafers with a 10 nm oxide layer thermally grown. The tip of the microscope, brought into contact with the sample surface, is biased with a voltage stairs, so local frequency-voltage (F-V) measurements can be performed. Another configuration of the equipment, which allows to measure the flat band voltage of the MOS capacitor as the peak of the derivative F-V curves, is also presented. The measurements methods described above have been compared with standard C-V measurements showing an alternative way to investigate on the presence of defects inside SiO₂ without requiring any sample preparation.

Scanning Auger Microscopy has been applied to study two typical problems in microelectronic features: depth profile analysis and defects. We have performed Auger depth profiles with and without the sample rotation during the sputtering and we have compared the results in terms of interface width and uniformity of the sputtered surface. Atomic Force Microscopy has been used to characterize the surface morphology and its results have been correlated to Auger map data. Microelectronics structures with a sizes of about 400 nm have been studied by means of Auger high resolution maps before and after electrical tests, in order to determine the effects of the tests on their structure.

Engineering analysis and in-line monitoring common employ either a brightfield TDI imaging or a laser-based darkfield optical approach to defect detection on patterned wafers. Brightfield imaging techniques are commonly used for engineering analysis because of their sensitivity and ability to capture pattern defects, especially in high contrast areas. Laser-based darkfield detection is used because of capture capability on rough deposited layers requiring a good signal to noise ratio. The WF-73X is a laser-based detection system that utilizes a combination of brightfield and darkfield optical configurations. The system offers 0.1 micrometers sensitivity for engineering analysis and 30+ wafer per hour throughput for line monitoring. It combines two propriety technologies employing a five PMT detector configuration.

Chemomechanical mirror polishing damages in a subsurface of silicon wafers have been revealed by photoconductivity amplitude with blue-laser/microwave photoconductivity technique and also revealed by photoconductivity technique and also revealed by photoconductivity amplitude and initial carrier lifetime with UV/millimeter photoconductivity decay technique. These noncontact techniques also have revealed subsurface damages as to be drastically influential on gate- oxide layer breakdown in MOSFET.

The perception of FTIR spectroscopy as an expensive, non- compact and vibration sensitive analytical technique, is rapidly changing with the recent introduction of small, robust and fast FTIR spectrometers dedicated to in-line and in-situ process control. FTIR Reflectance Spectroscopy has become a powerful in-line characterization technique delivering information on epi-thickness, doping concentration, dielectric film composition, molecular bond density, thickness of thick semiconductor films, deep trenches, etc., inaccessible in the visible range. The metrology capabilities of the technique will be outlined, including a discussion of process integration and semiconductor yield enchantment issues. The new instrument employs a vibrationally isolated FTIR interferometer and a high-speed digitizer. This combination allows a significantly faster scan rate, and a subsequently superior signal-to-noise ratio. The sensor is designed to be mounted on a process chamber equipped with normal or oblique ports, and provides normal or oblique incidence measuring modes. Outstanding vibration suppression, thermal stability, and high S/N makes it possible to achieve process control with monolayer thickness resolution. Particular examples on ULSI thin film/wafer-state FTIR metrology is presented.

This paper describes the experimental setup, test procedure and data-processing of the new profilometer based on an optical fiber displacement sensor. For performing test procedure this sensor is mounted on a high precision linear stage. The optical fiber probe consists of a bundle of optical fibers in a a star configuration. The linear displacement system is mounted on hydrostatic bearings, the guideways are made from zerodur with a planeity better than 0,25 micrometers . The stage is moved by a friction drive over a distance of 220 mm and controlled by an optical encoder with a resolution of 4 nm. The surface profile of a piece from standard polished stainless steel measured by our profilometer is presented.

X-ray based metrology and inspection can be used for various applications: composition analysis, thin-film thickness measurement, and the determination of crystallographic structure and surface roughness. High resolution imaging is also theoretically possible for defects detection and analysis. In this work we focus on x-ray fluorescence (XRF). We discuss its principles, the system requirements, and its applications for x-ray metrology. Such systems can be installed in an in-line or at-line configuration for the monitoring of interconnects systems, both aluminum na copper based. The measurement can be done over special test sites on the chip itself or on the scribe-lanes. Measurement over active devices is also possible but electron-hole creation in the gate and field oxide limits the maximum allowed irradiation per unit are. In this work we discuss the guidelines for critical dose and minimum measured area that allow proper and fast metrology. It is concluded that both high-speed and damage free XRF metrology is possible.

An ac surface photovoltage, which is excited by a chopped photon beam in a semiconductor, is successfully applied for nondestructive detection of metallic contaminants on silicon wafer surfaces. In this report, the charge-induced phenomena at Si wafer surfaces due to various impurities and the mechanism are summarized. Metal (trivalent Al and Fe)- induced negative charges have been proposed at the top region of thermal oxide on the basis of the generally accepted oxide charge model.

Contamination levels in chemical cleaning equipment and wafer cleanliness in general are very critical to semiconductor manufacturers. In this work, a Keithley Instruments non contact electrical tester (Quantox) is used to measure the mobile ion (Qm) contamination in a variety of cleaning processes. Results show that photoresist strip cleaning process has a higher mobile ion concentration than standard pre-diffusion cleaning process. RCA1, RCA2 and HF solutions mapping measured by the Quantox indicates some negative static charges on the surface after cleaning. This negative field appears to assist Qm removal during wet chemical cleaning. The dependence of flatband voltage and other oxide charges on various cleaning processes has also been investigated using the Quantox. The data suggests that a dipole layer has been formed by a surface reaction during chemical cleaning.

In this paper, we investigate the possibility of using non- contact surface potential measurements (SPM) to study charging during plasma enhanced CVD TEOS deposition and high current ion implantation. It is found that SPM can be used for a first order and fast-feedback assessment of new recipes and tools as well as for routine monitoring of plasma damaging processes.

We present fundamentals and representative examples of fast non-contact full wafer characterization of oxide and silicon defects induced by plasma and thermal processing steps. Parametric and distribution results are obtained using the recently introduced 'COCOS' and surface doping methodologies that enhance contact potential difference and surface photovoltage methods. The measured parameters include flatband voltage, interface trap density, soft breakdown, oxide surface potential and recovery lifetime. We studied the effects of plasma metal etching and ashing, thermal oxidation, anneal ambients and nitridation methods.

A comparison study was conducted between three different techniques used to resolve iron contamination in silicon. Fourteen 8-inch type Si wafers were implanted with iron at seven doses ranging from 1 by 10⁸ to 1 by 10¹² cm^-2. All 14 wafers including monitors were processed through an RTP chamber at 1100 degrees C for 6 min. Oxide thickness was measured on an ellipsometer. The wafers were measured by optical and thermal activation SPV, then the wafers were split in two sets. One set of seven wafers was measured by ELYMAT and the other set was measured by (mu) -PCD. Two different passivation techniques were used for (mu) -PCD, oxide and ethanol-iodine passivation. At low implant dose all three techniques have limitations. However (mu) -PCD shows the highest lifetime. At high Fe concentrations all three techniques tend to agree.

A study was conducted to monitor plasma induced charging during a plasma enhanced chemical vapor deposition (PECVD) process. A contact potential difference (CPD) technique was used for the charge measurement on non-device blank wafers. In two TEOS based PECVD SiO₂ deposition processes, one phosphorous doped and one undoped (USG), the plasma induced charging behavior was monitored while deposition conditions were varied. It was found that the process deposition pressure had a large effect on the plasma induced charging behavior. For both the PSG and the USG deposition processes, higher pressure process regimes offered significantly improved plasma charging performance than the conventional low pressure regimes. The CPD was reduced from -13.5V to 1.5V for the PSG process, and the CPD uniformity was reduced from 8.17V to 2.39V for the USG process. The improved deposition process conditions were tested on thin gate antenna test structures and correlated to significant improved device yield. Additionally, a plasma assisted de- chucking process was analyzed using the CPD technique and found to be an important source of plasma induced charging. When test were performed on thin gate antenna test structures the CPD again correlated well yield trends. In summary, the study demonstrated that CPD is a powerful, inexpensive, and rapid technique suitable for developing processes with improved gate oxide yield and for in-line monitoring of chamber performance.

Electrical parameters such as threshold voltage (Vt), breakdown voltage (BVdss), source-drain current (Idss), and leakage (Igss) for surface p-channel MOSFETs are dependent upon channel doping. It was found that phosphorous out-gassing during anneal from doped ILDO could redope the channel and cause unexpected increases in both Vt and Vt variation. It is believed that the Vt variation results from two separate phosphorous out-gassing related mechanisms. One mechanism is the transport of phosphorous by the ambient gas through the furnace with a gradient from source to load. SCA results have shown that the phosphorous concentration was two orders of magnitude higher at the load end than at the source end, which was also confirmed by SIMS analysis. The other mechanism is diffusion oflocalized phosphorous from the TEOS, which does not difftise into the furnace ambient, but rather lingers between wafers. The corresponding Vt variation within a wafer, mostly caused by the latter localized effect,was measured to be 50 to 200 mV depending on poly implant dose. Lot to lot variations caused by both localized and furnace phosphorous have been found to be even larger. Two process modifications, undoped TEOS and a sandwich process, were made to eliminate the phosphorous out-gassing problem. While undoped TEOS does have the drawback of being unable to getter sodium, it was found that across waferuniformity and across flirnaceuniformity for both processes were substantially improved. Almost no phosphorous was detected by the SCA.

Key words: threshold voltage, phosphorous, anneal, outgassing, and sandwich

A common challenge faced in many photolithographic processes is the patterning of photoresist on reflective substrates such as aluminum. One effect of the reflectivity of such substrates is linewidth variation known as reflective notching which severely impacts process latitude and device reliability. In recent years, strongly absorbing intermediate layers or ARCs, both organic and inorganic, have seen widespread implementation to control reflective notching. However, a more cost effective and immediate solution to reflective notching would be the application of a fast, high resolution dyed version of an i-line resist optimized for linewidth control over reflective topography. AMD's Fab solution to reflective notching was the implementation of Shipley's 3617M photoresist for all non- ARC metal layers. The process was qualified, implementation and monitored for two weeks at which time in-line data indicated: 1) a downward shift in the metal linewidths, 2) increased critical dimension variation, and 3) a critical dimension distribution statistically different from the previous photoresist process. This paper will present the methods used for handling, interpreting and reacting to in- line metal critical dimension data. Actual production data will be compared to PROLITH/2 simulated results, and corrective actions identified as well as lessons-learned summarized.

We have studied optimization of in-line inspection in terms of Cost of Ownership. We have defined that Cost of Yield Loss of in-line inspection steps is 'the potential cost of products lost by unfitness of in-line inspection' and cleared that optimized of in-line inspection is 'the cost reduction of yield loss brought by missing the occurrence of process or process tool excursions'. From this point of view, we have studied and proposed a method for in-line inspection optimization.

Defects inherent in fab processes limit achievable yields. To improve defect limited yield, it is necessary to identify which defect types contribute most to yield loss and focus resources on reducing those defect types. For memory processes, the standard approach is to utilize the bitmap ability of the products in conjunction with in-line defect data to identify which defects are contributing most to yield los. For wafer fabs producing analog circuitry, in the absence of a suitable bitmapable memory product, an alternative method of quantifying defect limited yield loss mechanisms is required. This paper describes the development and verification of such a method on a mixed mode analog/digital 0.6um CMOS process. This is based on a 'smart' in-line defect classification system in which the likelihood of a defect presence causing a failure is coded. The approach is developed and verified using a mixed mode product that has a section of bitmapable memory. The 'yield prediction' ability of the in-line classification system alone is investigated.

This article deals with the development of a defect density monitoring strategy for semiconductor mass production. We present an empirically justified defect density monitoring method which combines two complementary approaches. One approach works with statistical means and needs a high wafer and lot sampling rate and a systematic defect analysis and classification by review. The second approach fits more to the needs of immature production line in the development phase. The first is more conform to mature mass production. Our goal is to combine tool and product/process monitoring as well as to restrict the number of inspection gates to yield relevant levels, without losing reaction time for problems on intermediate process levels. At the same time the combination allows us to change the emphasis from monitoring with engineering character at the beginning of the lifetime of a production line towards a defect density control for mass production.

Small-probe analytical tools (SEM/EDX, AFM, AES, TOF-SIMMS, XPS...) are essential for failure analysis in the semiconductor industry. One of the major challenges in this area is in locating the defect within the analytical tool so the defect can be analyzed. The problem is especially difficult for analysis of particles/defects on unpatterned wafers. We have eliminated this problem by developing a new technique called Mark-Assisted Defect Analysis (MADA). The instrument we developed to perform MADA has a robust defect locating capability, and the ability to place micro-sized laser marks in the vicinity of the defect. The marks serve as in-situ landmarks that direct subsequent analysis efforts to the defects location. MADA has enabled numerous analytical techniques to be employed which were previously not possible due to the difficulty in locating the defect within the analytical tool. Examples include the use of multiple analytical techniques for analysis of the same defect, AFM analysis of sub-half-micron particles on bare wafers, SEM/EDX analysis on defects that provide optical contrast but are nearly imperceptible by the SEM, and particle/defect analysis on unpatterned wafers using analytical tools that cannot accept full-wafer samples. In this paper we present an overveiw of the MADA technique and provide several examples of how the technique was employed to solve challenging defect analysis problems on unpatterned wafers.

Reflow soldering using laser beam radiation is an attractive joining technique for fine-pitch components used in electronics. It allows contactless and force-free processing of all optically accessible areas with limited and easily controllable heat supply. The analysis of pyrometer signals during laser micro soldering can be seen as the basis of process control. Therefore, the timedependent courses of the thermal radiation of the joints during soldering were determined. They show characteristic arrests, turning points and changes in slope respectively. These changes permit a simplified classification of the soldering process in three phases: "reflow of the solder deposit", "wetting of the joining partners" and "cooling of the joint". In former research projects concerned with the characterization of the reflow behaviour and the wettability, only the actual solder deposit or the soldering of passive components were investigated. The tests were performed on fine-pitch structures made of FeNi42 and CuFe2P, typical materials used in electronics, and with solid solder deposits (SSD). The characteristic signal courses and the temperature of the joint were recorded with the aid of a PbSe pyrometer and with thermoelectric couples, the time of reflow was additionally determined by analyzing the structure-borne noise emission and the complete soldering process was visualized with a high-speed camera for the verification of the findings. The process windows were determined on the basis of optimum laser power and corresponding pulse duration. The use of pulse durations longer than e.g. 40 ms allowed clear recognition of characteristic features to be used as a basis of control strategies (CuFe2P, pitch: 300 rim). Very short process durations (TH < 10 ms) could also be realized with good soldering joints. However, control during this process is not possible because of the wetting process taking place with a time delay over the laser pulse. Also the process window, which lies between non-wetting and destruction of the joining partners, is very small.

Keywords: laser micro soldering, solid solder deposits (SSD), process characterization, melting process, wetting process, cooling process, pyrometry

A review ofthe applications of Time OfFlight-Secondary Ion Mass Spectroscopy (TOF-SIMS) to control various processes currenfly used in the manufacturing of semiconductor devices with the purpose of their improvement and the consequent enhancement ofthe wafer fab process yield and the IC's performance, is here reported. The fields explored by TOF-SIMS as a surface analysis technique were: diffusion, plasma etch and ash, ion implantation. As concerns diffusion, a work showing the detection of alkaly metals and the consequent, abnormal increase of the silicon oxide growth rate is reported. Another investigation demonstrates the presence of Aluminium contamination and the presence of a uniform, ultra-thin layer of fluorinated polymeric residues left on silicon wafers by a plasma etch process, not detected by the commonly used in-line techniques. In implant, analyses done before and after the ion implantation on the same wafer showed the contamination of Aluminium induced by the implanter itself Another work demonstrates the TOF-SIMS capability to control the implanters performance in separating the different isotopes of the implanted species, in the case ofboron implantation. Finally, in area, the analyses done to control the effectiveness of adhesion promoter for photoresist on Silicon wafer show that poor coverage of the resist adhesion promoter, which can cause the photoresist peeling, can be monitored by characteristic fragments detection by TOF-SIMS. 3

Keywords: TOF-SIMS, diffusion, plasma etch, implant, photo, polymers

Determining the roughness of a wafer surface inside a wafer fabrication plant would be advantageous in solving process problems in semiconductor device manufacturing. Currently, there is not a technique in the fab that will measure the large area surface roughness accurately and non-destructively. Traditionally Atomic Force Microscopy (AFM)1 has been the method of choice for surface roughness analysis. However, AFM typically measures roughness in a micro-area (e.g. 5 μm x 5μm). We have developed a new technique with Total Reflection X-ray Fluorescence (TXRF)2 for the determination of surface roughness using a large area scan. TXRF is used primarily to find trace metal contamination on the surface of a wafer. 3 In the TXRF measurement a secondary fluorescence signal is obtained following irradiation with a primary x-ray beam. We have found that plotting the primary scatter beam (e.g. Au L13 counts per second) versus the secondary fluorescent x-rays (e.g. Si counts per second), a trend is obtained that is linear and specific for a particular wafer. The slope of this linear trend is strongly dependent on the roughness of the wafer surface as determined by AFM. By comparing the slopes of these lines we have found that an increase in slope relates to an increase in roughness. The data has shown that this relationship is independent of the surface type. Polysilicon, oxide and metal stack wafers with varying surface roughness (e.g. AFM) have been studied with the TXRF.

A unique defect type was detected by routine KLA inspection. The shape of the defect was rod like, about 1/2 micron in width with length varying from 1 to several microns. The defects were located in the notch area with defect counts often exceeding one thousand per wafer. Through the analysis of bitmap/visual defect overlay, it was shown these rod-like defects are yield killers. This was confirmed by cumulative probe yield maps which showed lower yields for dice located near the notch. In this paper, the mechanism for the rod- like defect formation will be described in detail. The techniques used to investigate the mechanism, defect characteristics, and yield impact will be discussed. The implementation of the solution to eliminate the rod defects will also be discussed.

Historical microprocessor product trends show an increase in product frequency of 1.25x per year and a transistor count increase of 1.4x per year since the early 70's. This trend is forecast to continue over the next decade to the 0.07 micrometers generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge, will require successful implementation of 157nm optical or next generation lithography. The transistor solution will require integration of sub 2.0nm gate oxides with improved gate electrode materials, improved low resistance shallow source- drain technology, advanced channel dopant engineering, and operation at or below 1.0v. Interconnect challenges will require support of 10 or more interconnect layers using low resistivity metallization and reduce epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrated at higher technology complexity, while maintaining lowest possible cost.

Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al to Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips'. Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, nose and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

This paper gives an overview of the foundry model and foundry technology trend in the future. The foundry model is a part of the natural trend toward the vertical disintegration of the semiconductor industry. Foundry technology is already in the leading pack, and will be on the leading edge from now on. Foundry technology will be market driven toward low voltage, low power, high performance, high density, and system on chip. Examples of leading-edge 0.25um logic and 0.18um and beyond process features will be used to illustrate this trend.

ULSI circuit performance is constantly increasing, in sped, functionality and device density. This performance increase is supported by the constant development of new processes and new equipment platforms, which support the demand for improved defect density and throughput. A key challenge for equipment infrastructure to continue to support this performance acceleration is the shortening of cycle time for equipment development and new material acceptance.