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Microelectronic Device and Multilevel Interconnection Technology II
Editor(s): Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit

*This item is only available on the SPIE Digital Library.

Volume Details

Volume Number: 2875
Date Published: 13 September 1996

Table of Contents
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Stability and reliability of fully depleted SOI MOSFETs
Author(s): Toshiaki Tsuchiya
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High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies
Author(s): Takeo Ushiki; Yuichi Hirano; Hisayuki Shimada; Tadahiro Ohmi
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Study of integration issues in shallow trench isolation for deep submicron CMOS technologies
Author(s): Amitava Chatterjee; Mark E. Mason; K. Joyner; Daty Rogers; Doug Mercer; John Kuehne; A. L. Esquivel; P. Mei; Suhail S. Murtaza; Kelly J. Taylor; Iqbal Ali; S. Nag; Sean C. O'Brien; S. Ashburn; Ih-Chin Chen
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Trench isolation technology for high-performance complementary bipolar devices
Author(s): Kevin C. Brown; Chris Bracken; Rashid Bashir; Kulwant Egan; Joe DeSantis; Abul Ehsanul Kabir; Wipawan Yindeepol; Joel McGregor; S. J. Prasad; Reda Razouk; Victor V. Boksha; Juan C. Rey
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Key issues in evaluating hot-carrier reliability
Author(s): James E. Chung
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Effect of the pLDD implantation dose on pMOS transistor characteristics
Author(s): Eitan N. Shauly; Richard M. Fastow; Yigal Komem; Itzhak Edrei
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Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C
Author(s): Dirk Uffmann; Christina Ibrom; Joerg Ackermann; Jens Stemmer; Jochen Aderhold
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Digital standard cells and operational amplifiers for operation up to 250 degrees C using low-cost CMOS technology
Author(s): Jens Stemmer; Joerg Ackermann; Dirk Uffmann; Jochen Aderhold
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Reliability scaling in deep submicron MOSFETs
Author(s): Tadahiko Horiuchi; Hiroshi Ito; Naohiko Kimizuka
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Optimizing a manufacturing submicron CMOS process for low-voltage applications
Author(s): Jun Ma; Sunny Cheng; Bob Pryor; Kevin Klein
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Device and process integration for a 0.55-um channel length CMOS device
Author(s): Whitson G. Waldo; Ibrahim Turkman; Rickey Brownson
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Manufacturing sensitivity analysis of a 0.18-micron NMOSFET
Author(s): Darryl Angelo; Scott A. Hareland; Shamsul A. Khan; Khaled Hasnat; Al F. Tasch Jr.; Peter Zeitzoff
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High-performance 0.25-um CMOS technology for fast SRAMs
Author(s): James D. Hayden; T. F. McNelly; Asanga H. Perera; Jim R. Pfiester; C. K. Subramanian; Matthew A. Thompson
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Lg=0.25-um CMOS devices with N+-polycide gate for 3.3-V application
Author(s): Jeong Yeol Choi; Zhijian Ma
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Shadowing of lightly doped drain implants due to gate etch profiles and implanter configurations
Author(s): Neil Bryan Henis; David Abercrombie; Rickey Brownson
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Use of elevated source/drain structure in sub-0.1 um NMOSFETs
Author(s): Jay J. Sun; Jiunn-Yann Tsai; Kam F. Yee; Carlton M. Osburn
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Materials and processing issues in the development of N2O/NO-based ultrathin oxynitride gate dielectrics for CMOS ULSI applications
Author(s): Byeong Y. Kim; Dirk Wristers; Dim-Lee Kwong
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Scaling considerations of interpoly oxide-nitride-oxide dielectric for high-density DRAM applications
Author(s): Zhijian Ma; Jeong Yeol Choi; Chuen-Der Lien
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Influence of carbon contamination on ultrathin gate oxide reliability
Author(s): Toshiyuki Iwamoto; Toshiki Miyake; Tadahiro Ohmi
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Computer-aided optimization of ion-implanted charge bump parameters for rf silicon SDR
Author(s): Shankar P. Pati; A. K. Panda
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Gate oxide field design in the sub-10-nm region
Author(s): Katsuhiko Kubota; C. Suzuki; Kosuke Okuyama; N. Suzuki
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Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation
Author(s): Mark Rodder; Jeong-Mo Hwang; Ih-Chin Chen
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Pass transistor and isolation design methodology and its implementation for improved manufacturability for 256-Mbit DRAM and beyond
Author(s): Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
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Reflow of Al-Cu by low-temperature germane reactions
Author(s): R. V. Joshi
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Characterization of W CMP processes for 200-mm applications
Author(s): David A. Hansen; J. Sam Luo; John Nguyen; Gregory Fawley; Sue B. Davis; Lucky F. Marty; Fermion Yang
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Integration of ICP high-density plasma CVD with CMP and its effects on planarity for sub-0.5-um CMOS technology
Author(s): Jiro Yota; Maureen R. Brongo; Thomas W. Dyer; Kenneth P. Rafftesaeth; James A. Bondur
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Comparison of spin-on materials in IMD planarization
Author(s): Simon Y. M. Chooi; Chew-Hoe Ang; Jia Zhen Zheng; Lap Hung Chan
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SOG etch-back process induced surface roughness
Author(s): Po-Tao Chu; Sen-Fu Chen; Jie-Shin Wu; Chih-Chien Hung; Ting-Huang Lin; Ying-Chen Chao
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Process integration of TDEAT-based MOCVD TiN as diffusion barrier for advanced metallization
Author(s): Fang Hong Gn; Qiong Li; Lap Hung Chan; Simon Y. M. Chooi
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Submicron metal etch integration study
Author(s): Simon Gonzales; Jesus Quijada; Gordon Grivna
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Effects of process parameters on microloading in subhalf-micron aluminum etching
Author(s): Jongweon Youn; Ki-Soo Shin; Hee Kook Park; Daehee Kim
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Comparison of the Ti/TiN/AlCu/TiN stack with TiN/AlCu/Ti/TiN stack for application in ULSI metallization
Author(s): Satish S. Menon; Ratan K. Choudhury
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Intermetallic compound formation in hot aluminum metallization and its effect on etching and electromigration
Author(s): Lianjun Liu; Dong Lu; Pang Dow Foo; Way Tat Tan; Kurt Kowk; Gang Zou; Man Siu Tse
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Copper metallization for on-chip interconnects
Author(s): A. V. Gelatos; Bich-Yen Nguyen; Kathleen A. Perry; R. Marsh; J. Peschke; Stanley M. Filipiak; Edward O. Travis; Matthew A. Thompson; T. Saaranen; Phil J. Tobin; C. J. Mogab
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Interconnection schemes for parasitics optimization
Author(s): Nicolas Delorme; Marc Belleville; Sylvette Bisotto; Jean Chilo
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Tungsten plug contact and via integration for subhalf-micron technology
Author(s): Harianto Wong; Chetlur S. Sreekanth; Lap Hung Chan
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Structured CVD-silicon carbonitride coatings
Author(s): Alexey G. Varlamov
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Productivity improvement through industrial engineering in the semiconductor industry
Author(s): Doron Meyersdorf
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