Stability and hot carrier reliability of fully-developed (FD) MOSFET's are investigated using quarter-micron level CMOS/SIMOX devices. It is shown that FD devices are more dynamically stable than partially-depleted (PD) devices in terms of floating body effects related to impact-ionization, and majority carrier redistribution in the body region due to on and off gate voltage. Parasitic bipolar action in FD devices is remarkably suppressed by introducing recombination centers near the source junction, and the source-to-drain breakdown voltage is improved. The hot- carrier-injected oxide regions in the front and back interfaces are investigated, and how the hot-carrier-induced damage affects the device characteristics is shown. A new hot-carrier degradation mode peculiar to SOI MOSFET's is described which greatly reduces the device's lifetime. The new mode can be avoided by introducing recombination centers near the source junction, and it is shown that FD devices have high hot-carrier reliability.

The threshold voltages of thin-film fully-depleted Si-on- insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta), one of the high-refractory metals, for the gate material. For the low-power application in deep quarter-micron regime, when the supply voltage becomes around 1.0 V, it is necessary that the threshold voltages of SOI MOSFETs, are controlled by the work function of the gate material: Work Function Engineering. It is clear that the mid-gap material instead of the poly-crystalline silicon (poly-Si) for the gate material is effective to control the threshold voltage. The use of the mid-gap material leads to the simplicity for CMOS processes because the same gate material is available for both nMOS and pMOS. Ta, one of the mid-gap material, has low resistivity and excellent durability to wet chemical cleaning. The ultraclean, low- temperature process makes it possible to suppress the reaction between Ta and the gate oxide. The results have shown that Ta-gate FDSOI MOSFET exhibits excellent threshold voltage adjustment in 1.0 V application, even if the gate length is reduced to 0.15 micrometers .

This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.

A trench isolation architecture for a low voltage (< 15 V), high frequency, complementary bipolar process technology has been developed. This technology features shallow and deep trench isolation with a minimum design rule of 1.0 (mu) , along with a zero encroachment deposited field oxide. Trench etch process results suggest a mechanism whereby, depending on the amount of exposed silicon, the plasma can either be considered `silicon deficient' or `oxygen deficient.' Black silicon formation during trench etching has been eliminated with an in-situ removal of the photoresist after the hardmask oxide has been defined. Terrain isolation process simulation results are shown to be more accurate in depicting actual wafer processing structures than Tsuprem-4. Initial bipolar device characteristics are reported that illustrate the integration of the introduced PlaTOx device isolation architecture. Realized f_t/f_max are 6.3/9.5 GHz for NPN, and 3.8/8.2 GHz for PNP transistors.

Two key issues in evaluating the hot-carrier reliability of CMOS device technologies will be examined. First, the basis for establishing hot-carrier reliability criteria will be analyzed. The case will be made for incorporating information about circuit performance requirements and operating conditions into future hot-carrier reliability criteria rather than relying on more ambiguous criteria defined by device-performance requirements alone. Second, the impact of lower operating voltages on hot-carrier reliability criteria and models will be analyzed. An assessment will be made of the future significance and impact of hot-carrier degradation for future scaled CMOS technologies.

pMOS transistors having lightly doped drain (pLDD) structures were fabricated with varying channel lengths and pLDD implantation doses. The effect of the implantation dose on the saturation current, peak substrate current, effective channel length, and threshold voltage was studied. It was found that above a critical pLDD dose (approximately 5 X 10¹² B/cm²) the effective channel length was reduced, resulting in an increase in the saturation current and a decrease in the threshold voltage. The peak substrate current, however, decreased with the pLDD implantation does up until a value of 5 X 10¹³ B/cm². An empirical relationship between the saturation current and the peak substrate current for transistors of varying channel lengths was derived, and is given as: Ibp equals 1.068 +/- 0.15 * Idp^{2.232+/- 0.12}.

Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250 degree(s)C using silicided LDD-MOS transistors with gate lengths of 0.8 micrometers and 1.0 micrometers as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of 0.8 micrometers NMOS transistors decreases from 14.3 V at room temperature to 10.6 V at 250 degree(s)C and the triggering voltage for second breakdown from approximately 9.4 V at RT to 6.2 V at 250 degree(s)C. For PMOS transistors no snap-back was observed up to 20 V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5 V. To consider shrinking effects were performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor (beta) > 1 at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under bias conditions even at temperatures up to 250 degree(s)C.

There is an increasing demand from automotive, aircraft and space industry for reliable high temperature resistant electronics. Circuits with reliable functionality up to temperatures of 250 degree(s)C would be sufficient for most of these applications. Digital standard cells and operational amplifiers are the basic building blocks of these circuits. Commercially available digital standard cell libraries and operational amplifiers are normally specified for operation up to a maximum temperature of 125 degree(s)C. Hence, the purpose of this work was the design and characterization of digital standard cells and operational amplifiers for operation up to 250 degree(s)C using a low-cost 1.0 micrometers epi-CMOS process. Several design measures were applied to the cells in order to further improve latch-up resistivity and to limit leakage currents, respectively. The transfer curves of all digital cells for all input signal combinations have been recorded in the temperature range from 30 to 250 degree(s)C. Significant results are very low temperature shifts of the noise margins and of the switching point, respectively. Furthermore, the low (0 V) and high (5 V) levels are reached exactly over the entire temperature range. Outstanding characteristics of the operational amplifier comprise low open-loop gain temperature drift as well as low offset and offset temperature drift, respectively. The open-loop gain was greater than 83 dB at room temperature with a drift of less than 0.02 dB/ degree(s)C. The offset voltage amounted to -1 mV at room temperature and 1 mV at 250 degree(s)C, respectively. The long-term behavior of these cells is currently under investigation.

This paper reviews scaled reliability of deep sub-micron MOSFETs, including hot-carrier effects and oxide-breakdown. On the point of practical device design, the former constrains the maximum applicable voltage with the scaling factor of k^-1/2. The latter give that with the scaling fact of k^-1. It is shown that the limiting factor of operating voltage switches from hot-carrier effects to thin oxide reliability at a 0.25 micrometers device.

A low threshold voltage (Vt) is desired to improve a CMOS circuit performance when operating at reduced supply voltages to save power. In this paper, a practical approach to reduce Vt for a conventional, manufacturing submicron CMOS process is presented. This `evolutionary' approach to reduce Vt is taken so as the ensure manufacturability and to reduce process cost. This is found to be useful especially before a deep-submicron or a sophisticated process targeted for low voltage application becomes available and manufacturable. Vt reduction is achieved by the integration of a thinner, in the case presented here a 105 angstroms, gate oxide into a 0.65 micrometers process. The process is then optimized to provide the device with highest current-drive while obtaining lowest Vt with acceptable subthreshold leakage with conventional front-end and back-end process. It is shown that, with the minimal changes to the 0.65 micrometers conventional manufacturing process, the Vt's for nominal n- and p-channel devices can be reduced by 20% - 30%, with more than 1.5X improvement in current drive at 3.3 V compared to devices with 150 angstroms gate oxide. The enhancement of circuit performance is demonstrated with measurements of benchmark circuits including CPU, ROM, and FSRAM, where successful operation has been obtained near IV and operating frequencies are nearly doubled at supply voltage near 1.6 V compared to conventional 0.65 micrometers process.

The device and process integration for a 5 V 0.55 micron effective channel length double layer poly, triple layer metal CMOS device is presented. The n-well doping has been optimized to minimize punchthrough currents on PMOS devices. Surface and bulk leakage current components have been analyzed for p-channel L_eff and n-well doping variation to evaluate the process latitude. A comparison is made with the n-channel transistor leakage due to drain induced barrier lowering. Yield dependence on threshold voltage is discussed by reviewing the results of a threshold voltage matrix. W_eff is recovered with LOCOS isolation using a pre-sacrificial oxide etch and the etch time effect on field threshold voltage is presented. The backend development has stressed process simplicity for low cost manufacturing. Scaling in z has enabled via aspect ratios to stay fixed after the shrink. The effect on sidewall coverage by the via angular geometry is discussed. The metallization process has been improved to aid in better sidewall coverage by the sputtered Al alloy. The consequences of interconnect delay are discussed.

The control over the random variations in manufacturing processes and equipment has become increasingly critical for deep submicron MOS IC technology. This analysis involves correlating the sensitivity of eight key device electrical characteristics (responses) of a 0.18 micrometers NMOSFET to the anticipated manufacturing variations in its structural and doping parameters (inputs). Using TCAD software, a 0.18 micrometers NMOSFET has been designed and optimized to be as representative as possible of a device intended for use by industry, and has then been used as the nominal structure for the sensitivity analysis. Nine input parameters such as gate length, gate oxide, etc. were varied in accordance with a three-level Box-Behnken design, and model equations were generated. A Monte Carlo simulator was also developed to extract the statistical distribution of each response and compare it to a normal distribution that best fit the data. These models allow a quick assessment of the sensitivity of the key device electrical parameters to manufacturing variations in the NMOSFET structural and doping parameters.

A high performance 0.25 micrometers CMOS process has been developed for fast static RAMs. This technology features retrograde wells, shallow trench isolation scalable to a 0.45 micrometers active pitch, surface channel 0.25 micrometers NMOS and PMOS transistors with a 55 angstroms nitrided gate oxide providing drive currents of 630 and 300 (mu) A/micrometers respectively at off-leakages of 10 pA/micrometers , overgated TFTs with an on/off ratio greater than 6(DOT)10⁵, stacked capacitors for improved SER protection, five levels of polysilicon planarized by chemical-mechanical polishing with two self-aligned interpoly contacts, 0.35 micrometers contacts and a 0.625 metal pitch. In this technology, a triple well structure was used for SER protection. High energy retrograde wells were integrated with shallow trench isolation and epi providing excellent interwell isolation for both leakage and latch-up down to n+/p+ spaces of 0.60 micrometers . PMOS transistors were scaled to a physical gate length of 0.1 micrometers while maintaining excellent short channel characteristics. A split word-line bitcell was scaled to 1.425 micrometers X 2.625 micrometers equals 3.74 micrometers ² using 0.25 micrometers rules. A tungsten interpoly plug was used to connect the PMOS TFT loads to the underlying NMOS latch gates without a parasitic diode or dopant interdiffusion, connecting 3 polysilicon layers with self-aligned isolation from an intervening polysilicon layer used as a local interconnect. With this plug, TFT drive currents were greatly improved, particularly at low voltages and the memory nodes pulled to the fully supply voltage. Functional 0.25 micrometers bitcells were demonstrated and with an LDD resistor it was possible to double the cell stability. Bitcell simulation was used to demonstrate that a 4T bitcell will be stable at 2.5 V but that a word-line boost will be required for 1.8 V operation.

A single N+ polycide gate CMOS process in 0.25 micrometers gate-length regime for 3.3 V application is presented with emphasis on process control, reliability and manufacturability. Key process steps include super-steep retrograde twin N/P wells, 70 angstroms gate oxide, shallow LDD implants, 1000 angstroms spacer, and 800 degree(s)C/60 minute furnace annealing. Process parameters such as implant energy and oxide thickness were chosen for good control and manufacturability. Devices show excellent I-V characteristics, subthreshold slopes and good suppression of short-channel effects such as punch-through, VT roll-off, DIBL and high-field effects for 3.3 V applications. The devices are optimized with a trade-off between performance and reliability by adjusting physical dimension and doping concentration in the LDD region. A gate delay of 27 ps/stage at 3.3 V has been realized for 0.25 micrometers N+-polycide gate CMOS technology.

Shadowing of lightly doped drain (LDD) implants at the gate edge can cause shifts in effective electrical channel length (Leff), drive current (Ids) and transistor asymmetry. Process integration of gate etch and LDD implant processing and equipment in Motorola has led to the discovery of a unique type of implant shadowing. The increased vertical profile of the gate etch on modern single wafer etch systems obviously increases the potential to shadow implants and some amount of shadowing is not detrimental to the devices. In LDD processes which both the N-type and P-type LDD implants are masked separately, the gate etch profile and implant angle and rotation will determine the amount of shadowing for each transistor orientation. In processes that use a blanket N-LDD and a masked P-LDD adjusted to compensate for the N-dopant in the P-channel devices, an interaction between different implanter rotations has been shown to drastically increase the shadowing affects and leave uncompensated N-LDD dopant. It is necessary to carefully match the implant angles and rotations for proper performance of these LDD structures.

As MOSFET feature sizes are scaled down to 0.1 micrometers and below, new techniques are required to develop and fabricate shallow, low contact resistance, and low leakage S/D junctions. In this study, 2D device simulations have been performed to compare conventional drain/source extension and elevated source/drain structure approaches for sub-0.1 micrometers MOSFETs. With a relatively deep n+ junction (approximately 0.1 micrometers ) in the D/S extension structure, the sidewall spacer needs to be wide enough such that the n+ front is away from the gate edge in order not to contribute significantly to short-channel effects due to additional charge sharing and drain-induced-barrier-lowering (DIBL). However this requires increased device layout area and results in increased parasitic resistance due to the long and shallow D/S extensions. Elevated S/D structures offer an alternative solution by providing a sacrificial layer for silicidation and a shallow n+ junction in the substrate to minimize the impact of n+ junctions on short-channel effects in sub-0.1 micrometers devices. The use of elevated S/D structure allows scaling down of the spacer width and relaxing the subsurface doping requirement to achieve a specified DIBL level. These lead to a significant increase in the drive current and a reduction in the junction capacitance. The gate-to-S/D capacitance associated with elevated S/D MOSFET can be controlled by proper scaling of the elevated layer thickness along with other pertinent design parameters.

This paper reviews recent developments in N₂O- and NO- based oxynitride gate dielectrics for CMOS ULSI applications. The motivations and significant advantages of N₂O/NO-based ultrathin oxynitride gate dielectrics for dual-gate CMOS ULSI are reviewed. Results will be presented to demonstrate the superior device reliability of ultra thin N₂O/NO oxides over the control oxides, with particular focus on boron diffusion barrier properties, TDDB, and MOSFET hot carrier immunity.

Highly reliable thin oxide-nitride-oxide (ONO) stacked dielectrics with oxide-equivalent thickness T_ox,eq in the range of 34 - 68 angstroms were fabricated using conventional furnaces and an RTA machine. Rapid Thermal Nitridation (RTN) in NH₃ ambient of smooth poly-Si prior to Si₂N₄ deposition is found to be critical for improving dielectric integrity and low-field leakage current of the ONO stacked dielectrics. This RTN process also significantly improves oxygen diffusion resistance of ultra- thin Si₂N₄ film. As a result, 22 angstroms LPCVD Si₂N₄ is adequate to sustain wet oxidation at 800 degree(s)C without any oxygen diffusion through it, which results in a manufacturable and reliable T_ox,eq equals 45 angstroms ONO stacked dielectric. By using rugged poly-Si as a bottom electrode plus RTN process, ONO stacked dielectric can be scaled down to about T_ox,eq equals 34 angstroms without any leakage or reliability problems.

When Si wafer is transported after gate oxidation process, the gate oxide surface is exposed to the clean room air and hydro-carbons in the clean room air adhere to the gate oxide surface. In this paper, we have demonstrated that the carbon contamination caused by the wafer exposure to the clean room air induces the degradation of the gate oxide reliability, and we have improved the gate oxide performance by using a closed system, where the oxidation is followed by in-situ phosphorous-doped polysilicon gate formation. Carbon contamination is serious problem for gate oxide film used under high electricfield condition such as a tunnel oxide for flush memories.

IMPATT diodes can produce high power RF oscillation between a wide range of frequencies and excel some other solid state devices. The device technology for fabrication of silicon SDR diode is now very much advanced. The device efficiency and RF power output register sharp fall when the frequency of operation is enhanced to high values. Introduction of charge bump near the junction leading to formation of low- high-low profile by using ion implantation technique can be used to restore high efficiency and high power. The purpose of this paper is to study the ion implantation profiles of a low-high-low structure SDR and to suggest the optimized ion implantation parameters by using a computer simulation method developed by us. The method gives the best ion- implantation parameters of the charge bump suitable for use in fabrication of IMPATT diodes. The method is a generalized one and can be used to design high efficiency and high power silicon SDR for any frequency band. This can add to microelectronic manufacturing technologies.

This paper discusses the gate oxide fields for MOS LSI design in the sub-10 nm gate oxide region for the nearest next few generations. Since practical determination of allowable gate oxide fields for scaled gate oxides strongly depends on oxide defect density levels, we measured defect densities for gate oxide thicknesses down to 3 nm. The defect-related breakdown failures affecting reliability were found to decrease with decreasing gate oxide thickness. The allowable gate oxide fields were calculated as a function of the gate oxide thickness and gate area to meet reliability criteria. The discussion also includes recent key issues such as the contribution of high-quality wafer substrates to allowable electric fields, and design guidelines for dual power supply voltages. Since the defect density levels depend on process, we generalized our discussion by showing the results for various gate areas.

LOCOS technology is being investigated for applicability to 256 Mbit DRAM applications in the memory array (with active region pitch < 0.6 micrometers ) as well as the periphery. In this paper, LOCOS isolation is demonstrated for array n^--n^- spacing < 0.2 micrometers for 256 Mbit DRAM array and for n⁺-n⁺ (and p⁺-p⁺) spacing < 0.35 micrometers for DRAM periphery. Array nMOSFETs with small active width of 0.2 micrometers are demonstrated with I_off < lfA/micrometers (V_B equals IV) at L_o equals 0.2 micrometers while maintaining low V_T (<V_T^spec equals 1.5 V at V_B equals 4 V) at L_o equals 0.3 micrometers in accordance with DRAM pass transistor design. These key results are obtained with appropriate LDD dose and energy, sidewall sealed LOCOS isolation, and 1100 degree(s)C field oxidation to reduce both field oxide thinning and active width encroachment. MOSFETs with sidewall sealed LOCOS show small narrow width effect, (Delta) V_T/(Delta) W, and no sub-V_T `double-hump'. In contrast, conventional LOCOS results in high (Delta) V<sub>T</sub>/(Delta) W for MOSFETs with active width < 0.4 micrometers while recessed LOCOS causes sub- V<sub>T</sub> `double-hump' for large active width MOSFETs.

With the active area pitch being pushed to the limit of LOCOS isolation, manufacturability of the array transistor is increasingly affected by the isolation design. In this paper we have enhanced our design for manufacturability methodology to include the effects of isolation design in addition to those of transistor design. We apply this methodology to 256 Mbit DRAM and demonstrate a margin of 0.06 micrometers for both nitride width (W) and poly gate length (L_g) variations for an isolation pitch of 0.6 micrometers and target L_g of 0.25 micrometers . This margin is obtained with Sidewall-Sealed MSL SSMSL process without edge oxide and using a heavy dose of channel stop implant. The diode leakage and gate oxide integrity are shown to be within acceptable limits. In terms of transistor design, pocket implanted transistors are shown to be marginally better than conventional transistors due to larger margin for L_g variation and comparable diode leakage.

This paper describes a low temperature reflow of Al-Cu using GeH₄ reactions. The Al-alloy reflow occurs due to formation of low melting point eutectic with Germanium. This technique results in a low cost process for filling high aspect ratio vias/lines with Al-based alloys with improved damascene capability. This is achieved at temperatures below 400 degree(s)C by reacting Germane (GeH₄) with Al-Cu alloys deposited by conventional techniques which result in voids, gaps and poor filling. Using such a process it is demonstrated that high aspect ratio vias with large undercuts can also be filled without voids. The low temperature provides capability to form multilevel homogeneous Al-alloy via/line structure without degrading the resistance of underlying interconnects. The reliability data shows that Al-Cu-Ge via/interconnect structure deposited by this method is at least `1.5X' better electromigration life time (t<sub>50</sub>) to that of hot sputtered Al-Cu (deposited at 535 degree(s)C) and almost `2X' to that of conventionally used CVD W stud/Al-Cu interconnect structure. The improvement in the reliability may be attributed to filling without voids high aspect ratio sub- half micron vias with low resistivity metal such as Al-Cu-Ge at temperatures well below 400 degree(s)C. Since this technique does not rely on the wetting layer or diffusion barrier a lower sheet resistance of Al-Cu-Ge line is achieved compared to high temperature reflow processes. Also the reaction between Al and GeH₄ takes place uniformly resulting in reproducible contact resistance. Most importantly it is possible to achieve `high open-short yields' of comb- serpentine structures, and via chains of difficult to polish materials like Al-Cu using `damascene' process.

This paper presents Design Of Experiment (DOE) experimental methodology used to determine W CMP process windows for 200 mm wafers using a multi-head polish system, Cybeq Systems IP 8000 polisher. A colloidal dispersed alumina nonferric nitrate slurry and concentric grooved polyurethane pad with a closed cell foam base layer, both from Rodel, were used to examine response matrices for W CMP. Removal rates, non- uniformity and metal: oxide selectivity as a function of polish head pressure and linear velocity were examined. Removal rate trends of W and PECVD oxide, non-uniformity and selectivity as a function of head pressure indicate removal rates > 2000 angstroms/minute, non-uniformity's < 5% and selectivity of W:PE-TEOS of > 10 are achievable. The optimized process obtained through DOE methodology was applied to a device wafer. The corresponding results were a non-uniformity < 2.5%, with no observable dishing, and no observable oxide erosion.

The planarity and gap-fill requirements for interlevel dielectrics become increasingly stringent as design rules shrink below 0.5 micrometers . In this study, we investigated the resulting gap-fill and planarity (both before and after CMP) for an interlevel dielectric stack consisting of inductively coupled high density plasma (HDP) CVD oxide and a standard PECVD SiH₄ oxide. Results show that the etch- to-deposition ratio and the thickness of the HDP CVD oxide will influence the final topography (both profiles and step height) before CMP. An optimum HDP oxide thickness was identified in order to achieve void-free deposition of the PECVD SiH₄ oxide, minimize time to planarize, and maximize tool throughputs for HDP and CMP. It was also seen that the resulting planarity after CMP is significantly dependent upon the underlying feature and feature dimension. This paper provides information on the integration of HDP CVD oxide with CMP For a sub-0.5 micrometers CMOS technology, and on the optimum HDP CVD oxide deposition conditions and thickness necessary to achieve a cost-effective, production- worthy process.

This paper describes the characterization of an etchback process for the new AlliedSignal's Accuspin 418 and Hitachi Chemical's HSG R7-13 low dielectric constant silsesquioxane spin-on polymers and the application to the inter-metal dielectric scheme of a 0.35 micrometers device. A comparison with a conventional polysiloxane spin-on glass (AlliedSignal's Accuglass 214) is also briefly discussed. The predominant factor affecting the selectivity of PECVD oxide to spin-on polymer is the CHF₃CF₄ flow. A low selectivity in which the spin-on polymer etches faster was found to rid of spin-on polymer on top of large metal features where vias may be cut while simultaneously leaving behind sufficient oxide on top of metal lines and the spin-on polymer in the metal spaces. After etchback, a thick PECVD oxide is deposited and planarized by chemical mechanical polishing.

SOG film surface roughness had been observed after SOG etch- back process. The etching recipes' total pressure and the CF₄/CHF₃ etchant gas ratio had been identified to be the two dominant factors which will determine the degree of surface roughness after etch-back. The high total gas pressure and high gas ratio etch-back recipe can minimize the roughness. However, the high pressure and gas ratio trends will result in poor global planarization. In this study, the optimal SOG etch-back recipe had been determined based on the degree of SOG roughness and global planarization. The degree of roughness was measured by the Atomic Force Microscopy.

Decreasing contact geometry imposes stringent requirements on barrier metals in providing good barrier against Al-Si interdiffusion. The challenge for the barrier metal technologies is to develop a process to give conformal and thermally stable barrier metal film at low enough temperature, so as to be applicable to multilevel interconnect metallization. Collimated Ti/TiN process results in overhanging at the top of the contact and conformality is no way possible. CVD (Chemical Vapor Deposition) process has been demonstrated to provide excellent conformality and is definitely an attractive option for sub-half micron technology. Process integration of Metalorganic CVD (MOCVD) TiN using TDEAT (Tetrakis(diethylamido) Titanium) precursor and NH₃ as co-reactant, together with PVD Ti has been demonstrated as diffusion barrier at contact level for advanced metallization. Two process pressure and temperature regimes of deposition were evaluated. The 30 Torr, 300 degree(s)C higher step coverage process and the 10 Torr, 425 degree(s)C lower resistivity were under study. All barrier stacks went through vacuum break before CVD TiN deposition. RTP was carried out either right after PVD Ti deposition or after CVD TiN deposition. Its impact on contact resistances and junction leakages upon thermal stress were investigated. In addition, the impact of Ti wetting layer on electrical parameters and barrier integrity, which is essential for Al planarization on small geometry contacts, was also studied.

Recent progression toward low pressure metal etching has been driven primarily by the reduction in spacing between features and the corresponding increase in aspect ratio of the areas to be etched. Key limitations of etching small feature spaces (< 0.6 micrometers ) include the aspect ratio (> 2:1) and pattern density variations between isolated and dense lines. This paper addresses the development and integration of a production worthy sub-micron metal etch process. The work performed focused on statistical design of experiments to determine the critical factors controlling the etching of small metal line spaces along with the overall characteristics of the final post metal etch process. Full integration included analysis of photo resist strip, passivation and corrosion control. The process as designed, contrary to common practice, cleared small space geometries first followed by the clearing of open field metal. This approach eliminates the common pattern density dependency of metal etch and provided a simplified process for implementation into manufacturing.

Microloading effect is one of the challenging phenomena in sub-halfmicron aluminum etching, which represents the decreasing etch rate with shrinking pattern size and open area. Process parameters should be optimized to control etch rate difference in different feature sizes. In this experiment, it is found that pressure and BCl₃/Cl₂ gas flow ratio are two major factors to affect on etch rate microloading. Under the standard BCl₃/Cl₂ chemistry, optimizing process parameters is not enough to reduce microloading sufficiently. Therefore, additional gas is introduced to suppress microloading effect less than 10%. N₂ or CHF₃ gas addition is not effective to improve microloading effect through polymerization mechanism. It is observed that CF₄ gas addition is the most successful to minimize microloading effect by enhancing ion assisted chemical reaction in small feature size.

The relative advantages and disadvantages of the two ULSI metallization stacks viz., Ti/TiN/AlCu/TiN and TiN/AlCu/Ti/TiN are described. The electromigration and thermal stability characteristics are compared using grain size of the Al metal, the XRD rocking curve peak and FWHM of the Al (111) orientation, SWEAT lifetime and electrical characteristics before and after thermal cycling of the test structures. In the literature, there exists work that report an improvement in the electromigration lifetime in the situation where Ti is in direct contact with Al due to the formation of TiAl₃. The results for submicron dimensions presented in this paper clearly point to very important requirements for those results to hold and highlight the danger in assuming its validity for submicron lines. The W- plug via schemes resulting from use of both these metallization stacks will be compared from both the electrical and reliability standpoint. The conflict arising between the functionality and reliability of the vias with the reliability of the metallization lines is discussed.

Application of hot aluminum (or aluminum plug) in deep submicron VLSI metallization has attracted much attention. Studies have shown that introduction of a titanium wetting layer prior to aluminum deposition improves the capability to fill deep submicron contacts/vias with vertical sidewalls in hot aluminum process. In this paper, we report that the introduction of this titanium wetting layer can also greatly improve the aluminum etching process window. Transmission Electron Microscope (TEM) analysis indicates that a continuous layer of TiAl₃ intermetallic compound has formed at the AlSi(1%)Cu(0.5%)/Ti interface during hot aluminum deposition. In the case of without titanium wetting layer, TiAl₃ compound can also form at AlSiCu/TiN interface but it is not a continuous layer. The formation of the continuous TiAl₃ layer is believed to be responsible for the improvement of etching process window. Electromigration lifetime test is also performed on samples with and without titanium wetting layer. While results show that the introduction of titanium wetting layer increases the electromigration lifetime of the hot aluminum metallization, too much TiAl₃ formation may degrade the electromigration performance due to its higher resistivity.

Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.l8piri [1], while microprocessors will pack more than 15 million transistors over an area of '-700mm2. To conserve area, interconnects will continue to be stacked at an increasing number of levels (6 by the year 2000, vs 4 in todays leading microprocessors) and the minimum spacing and width within an interconnect layer will shrink to 0.3.tm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures [2]. Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused n means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations [3], or by the development of complicated multimetal stacks [4. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7.tW-cm for Cu vs. 3.0iW-cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (.-1100°C vs. -600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration [5]. However, as with any new process trying to break into the mainstream, significant improvement in reliability and performance over that achievable with aluminum alloys must be demonstrated first. Towards this purpose, processes need to be developed that deposit conformal copper films of high purity with acceptable throughput, and integration schemes need to be developed which produce interconnects and multilevel metal structures with reliability significantly better than that of aluminum. This article describes our efforts to integrate copper in the backend of integrated circuits. The first part deals with the chemical vapor deposition (CVD) of copper films. The second describes the integration of copper into the last metal level of a 2-level metal 0.5um BiCMOS SRAM circuit.

A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist in: increasing the inter-metal dielectric thicknesses, using SiOF instead of SiO₂, embedding the interconnects in a low-permittivity dielectric and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures, for delay, crosstalk, and consumption in standard circuit routings, and for a 32 bits adder worst case delay and consumption.

Tungsten plug technology has been used extensively for multilevel interconnect in sub-half-micron semiconductor processes. The major issue encountered in tungsten plug integration is contact resistance especially to the p+ Si area and via resistance. In this study, investigations were carried out on several aspects of contact cleaning, plug implant, and barrier metal deposition. The test vehicle utilized is in-house logic test chip with 0.35 micrometers design rule. Contact resistance of tungsten plug was found to be strongly correlated with contact cleaning, plug implant and Ti deposition thickness. Ar sputter clean was shown to have detrimental effect towards contact and via resistances. Plug implant was shown to be a necessary step for p+ contact resistance control. Thicker Ti deposition was also shown to be crucial in improving contact resistance.

Using functional structured ceramic multielemental composition coatings as protective ones is going to become a modern tendency. For such coatings CVD-synthesis it is necessary to use precursors gas mixture that are potentially able to educe several condensed compounds. Then, under certain synthesis conditions `hard solution' type complex compounds (oxicarbides, oxinitrides, carbonitrides etc.) are produced as a result of a heterogeneous reaction, proceeding on active centers, macroscopically continuously and evenly distributed all over the surface. Different synthesis conditions result in different composition condensed products deposition (different elements correlation). The synthesis conditions changing during the deposition process lead to layer-by-layer coating composition changing, that is to an in situ structured coating obtaining. In the present work the `hard solution' type variable composition compounds CVD obtaining possibility is considered with the SiNC- coatings synthesis as an example.

Industrial Engineering is fairly new to the semiconductor industry, though the awareness to its importance has increased in recent years. The US semiconductor industry in particular has come to the realization that in order to remain competitive in the global market it must take the lead not only in product development but also in manufacturing. Industrial engineering techniques offer one ofthe most effective strategies for achieving manufacturing excellence. Industrial engineers play an important role in the success of the manufacturing facility. This paper defmes the Industrial engineers role in the IC facility, set the visions of excellence in semiconductor manufacturing and highlights 10 roadblocks on the journey towards manufacturing excellence. Keywords: industrial engineering, semiconductor, manufacturing, productivity improvement, modeling, design