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Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Editor(s): Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann

*This item is only available on the SPIE Digital Library.

Volume Details

Volume Number: 2874
Date Published: 12 September 1996

Table of Contents
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Statistical metrology: understanding spatial variation in semiconductor manufacturing
Author(s): Duane S. Boning; James E. Chung
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Inter- and intra-die polysilicon critical dimension variation
Author(s): Brian Stine; Duane S. Boning; James E. Chung; David A. Bell; Edward Equi
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Real-time determination of interconnect metrology
Author(s): Shadi Alex AbuGhazaleh; Phillip Christie
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Metrology automation reliability
Author(s): Elizabeth E. Chain
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Determination of critical process steps for enhanced yield improvement
Author(s): J. B. Duluc; Thomas Zimmer; N. Lewis; Jean Paul Dom
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Correlation between particle defects and electrical faults determined with laser scattering systems and digital measurements on checkerboard test structures
Author(s): Christopher Hess; Larg H. Weiland; Guenter Lau; Rainer Hiller
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Accurate prediction of kill ratios based on KLA defect inspection and critical area analysis
Author(s): Akiva Elias; Andrzej J. Strojwas; Wojciech P. Maly; Raman K. Nurani
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Fast failure analysis and yield enhancement: an integrated approach
Author(s): Fourmun Lee; Nam Doan; Lisa H. Liu
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Role of RIE in microchip bond pad corrosion
Author(s): Rickey Brownson; Kevin Butler; Sally Cadena; Mark Detar; Ivan Johnson; Lonnie McCoulloch; Jim McCoulloch; Brajendra Mishra; Jerry T. Healey; Karen Honcik; Tony T. Phan; Todd Sterif; H. Stevens; Anita Tovar
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Characterization of intrinsic thin silicon dioxide breakdown under static and dynamic stress
Author(s): Prasad Chaparala; John S. Suehle
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Plasma-etching-induced oxide degradation: effects upon device performance and circuit yield
Author(s): Scott T. Martin; Guann-pyng Li; Eugene Worley; Joe White
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Time reduction of MCM-D prototype realization by process control and modeling
Author(s): Helene Fremont; C. Ahrens; E. Saint Christophe; B. Enoeckl; M. Fathi; G. N'kaoua; C. Pellet; Ruediger Ferretti; Yves Danto
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Using IDD to analyze analog faults and development of a sensor
Author(s): Yvan Maidon; Yann Deval; Helene Fremont; Jean Paul Dom
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Built-in self-test for high-speed integrated circuits
Author(s): Udo Jorczyk; Wilfried Daehn
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Design of the UltraSPARC-I microprocessor for manufacturing performance
Author(s): Lynn Youngs; Greg Billus; Anjali Jones; Siva Paramanandam
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Defect mapping and repair in UltraSPARC-I microprocessor memories
Author(s): Siva Paramanandam; Lynn Youngs
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Sampling-based yield prediction for ULSI
Author(s): Gerard A. Allan; Anthony J. Walton
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SAS: a yield/failure analysis software tool
Author(s): Susana de Jong Perez
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Advanced software system for yield improvement on manufacturing fab
Author(s): Miguel Recio; Almudena Fernandez; Victorino Martin Santamaria; Maria J. Peman; Gerardo Gonzalez; J. R. Hoyer; Steve Whitlock; David James; Mark Hausen
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Source drain leakage: a potential problem in submicron CMOS devices
Author(s): Yeoh Eng Hong; Ali Keshavarzi; Martin Tay
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Back side emission microscopy for failure analysis
Author(s): Nevil M. Wu; Kenneth Tang; James H. Lin
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Analysis of stress-driven delamination in contact vias
Author(s): Martha Small; Doug Crook; Eric Nikkel; David Buck
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Rapid integrated circuit delayering without grass
Author(s): William E. Vanderlinde; Christopher J. Von Benken; Addison R. Crockett
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Laser chemical vapor deposition of Cu and Ni in integrated circuit repair
Author(s): Seppo Leppaevuori; Janne Remes; Hannu Moilanen
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Reliability issue on pipeline defects in CMOS memory devices
Author(s): So Youn; Kyle Terrell; Chau-Chin Wu; Paul Shy; Chuen-Der Lien
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Fault isolation with fanin tree technique
Author(s): Kang Siong Ng
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Rapid debug of yield and performance bottlenecks within the UltraSPARC-I microprocessor
Author(s): Aswin Mehta; Greg Billus
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Automated collection of yield and performance analysis data during UltraSPARC-I microprocessor production test
Author(s): Matt Koeppen; John Moore
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UltraSPARC-I microprocessor yield and performance analysis
Author(s): Derek C. Wrobbel; Kevin L. Walker
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Defect analysis and classification in process control using an SEM and EDX review station
Author(s): Pascal Perret; Vincent Zinssner
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Plasma-induced oxide contamination in a 0.35-um CMOS process
Author(s): Martin P. Karnett; Jingrong Zhou; Sumanta Ghosh; Danny Echtle; L. Fritz; Martin Manley; Gregory S. Scott
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Defect detection and control in an analog CMOS process
Author(s): Franz Taucher; Ivor R. Evans
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Multifractal point defect clusters in subsurface damaged layer of semiconductor wafers
Author(s): Alexander P. Fedtchouk; Ruslana A. Rudenko; A. A. Fedtchouk
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Modern concept of focused ion beam techniques for reliability analysis in VLSI manufacturing
Author(s): Dumitru Gh. Ulieru
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Productivity improvement through industrial engineering in the semiconductor industry
Author(s): Doron Meyersdorf
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Wire length and via reduction for yield enhancement
Author(s): Venkat K. R. Chiluvuri; Israel Koren
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High contact resistance heavily doped silicided p+ junctions
Author(s): Michael S. Twiford; F. A. Stevie; E. B. Prather; Morgan J. Thoma; William T. Cochran
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