We compare the capacitive transimpedance amplifier (CTIA) to two other IR detector interface circuits using data compiled from hybrid FPAs in various formats from 8 X 8 to 1024 X 1024. The CTIA generally offers the best overall performance characteristics including read noise as low as 27 e- at signal bandwidths compatible with TV-type frame rates, low power dissipation (in some cases significantly less than 200 nW per pixel), and sufficiently low MOSFET self-emission for background-limited sensitivity at scene backgrounds significantly less than 10⁹ photons/cm²- s. The alternative schemes should, however, be considered especially when very high transimpedance is needed at moderate bandwidths or when radiometric linearity is not required.

Modern focal plane arrays (FPAs) are being driven to lower cost, higher resolution, and more features. The complexity and requirements of such FPAs overwhelm traditional design approaches. An all encompassing design methodology that includes the requirements process, a tightly integrated test capability, an extensive modeling capability, and a detailed understanding of the foundry and FPA fabrication processes is required. Santa Barbara Focalplane's overall design methodology is presented as an approach to managing current and future FPA complexity.

Data collection for Earth resources applications requires sensors with high sensitivity, moderately high scan rates, large dynamic range, and excellent calibratability and stability. In addition, multispectral or hyperspectral capabilities are highly desirable to enhance scene discrimination, chemical species identification, and temperature measurement performance. These sensors must also have small size, light weight, low power, reduced thermal load, and simple electronic interface characteristics for improved mission performance. A collection of focal plane technologies is currently being developed to meet these requirements: (1) High-speed (18 kHz) 224-channel scanning InSb sensor chip assembly with 52 in TDI. (2) On-SCA 450- channel, 24-kHz, 12-bit A/D converter. (3) 208-color SWIR- MWIR hyperspectral and 3-color SWIR-MWIR multispectral solid-state spectrometers. (4) Cryogenic digital optic data links. Prototype components have been fabricated. Initial performance measurements have successfully demonstrated the feasibility of these emerging focal plane technologies.

We report the performance of InGaAs and HgCdTe FPAs using multiplexing readouts having gate modulated interface to the infrared detectors. Gate modulation enables extremely high sensitivity via self-adjusting current gain and concomitant high transimpedance. At operating temperatures where the detector current was dominated by photocurrent, gate modulation current gain is > 40,000 and yield input- referred read noise of < 2 e-. Key highlights include D^* exceeding 10¹³ Jones at room temperature and 10¹⁶ Jones at 170 K with a 1.68 micrometers InGaAs FPA.

Pressures to increase resolution, achieve compact packages, and lower costs continue to drive focal plane readout circuits to highly complex designs with lowered yields in cutting edge processes. By designing a set of signal processing electronics into a 3D structure, cost and performance goals can be met while using higher yielding readouts and existing focal plane hybrids. The approach described in this paper allows existing designs from 480 X 4 through 480 X 640 to be used in compact sensor designs in a wide variety of applications. The demonstration of the approach uses an existing InSb photovoltaic hybrid array in a 120 X 160 configuration. Functions for non- uniformity correction, memory, and analog-to-digital conversion have been incorporated into a structure compatible with conventional dewar assemblies for military and commercial applications. The technology for these 3D focal planes is applicable to sensor functions for non- uniformity correction, analog-to-digital conversion, spatial and temporal filtering, fovea vision, event-driven multiplexing, data compression and coding, and pattern recognition.

Monolithic arrays of InP JFET switches and InGaAs detectors have been demonstrated with unprecedented JFET leakages below 20 pA. Improvements in the JFET dark current resulted from reduced device geometry along with the use of a novel reversed bias p-n junction. Successful devices have been made both with OMVPE and gas source MBE crystal. Other impressive results with column-switched 16 X 16 element arrays include detector leakages below 1 nA, 70 percent quantum efficiency from 1.0 - 1.65 micrometers and ON/OFF ratios beyond 70 db.

Design and operation of high-gain (> 1000), low-power (< 75 (mu) W), ultra low-noise amplifier arrays are presented. The amplifier array is operated in self-biased mode, such that all amplifiers are biased irrespective of threshold mismatches, and operate with low reset noise. The amplifiers are designed for possible incorporation as pixels of hybrid solid-state photon-counting sensor. The cell pitch is 30 micrometers in 1.2 micrometers CMOS technology. Design and experimental results from small arrays of the two most promising amplifier circuits are reported. Design issues for obtaining sub-electron input-referred noise from these in- pixel amplifiers are discussed. A performance summary is incorporated.

A circuit for readout of LWIR photodiode in area FPA is suggested and simulated. It is expected, that the combination of a dynamic current mirror and the buffered direct injection input (DCM-BDI) will be capable of a hundred-fold dark current and background current suppression, and perfect, within a few millivolt over FPA, detector biasing. The estimates are made of which improvement in detectivity the novel readout scheme can bring. To realize fully the benefits of the DCM-BDI readout, the buffer amplifier 1/f-noise should be made as small as 100 nV/Hz^1/2 at 1 Hz.

An on focal plane digital readout development suggested by the Army Night Vision & Electronics Sensors Directorate is proceeding under a combined program with the development of two color HCT detector arrays. The on focal plane A/D process is based on the Amain patented multiplexed oversample A/D, MOSAD, technology. In the first year of the program, prototype on focal plane analog to digital converters for both staring arrays and scanning arrays were built and demonstrated. The prototypes included a 2 loop double ended switched MOSAD and a 1 loop single ended MOSAD. Results from the original experimental prototypes showed conclusively that better than 14 bits could be achieved and that well capacity could be increased to support high background HCT needs approaching 10⁹ electrons. In the second year, a 64 X 64 staring array for HCT LWIR detectors, 50 micron centers, was built based on these original prototype designs. The layout of the per pixel MOSAD A/D staring array used Orbit 1.2 micron CMOS process and achieved a pixel size of 40 microns with a well capacity of 1.9 X 10⁸ electrons. Integration capacitors were built using Orbit's normal double poly capacitors with a standard buffered direct inject TIA detector interface configuration. Preliminary testing has been completed indicating complete functionality. Fermionics LWIR HCT detectors with cutoff at 9 microns have been built for attachment to the readout but indium bumping was not completed in time to report system level testing results. However, some noise tests have been performed using on array current mirrors. These tests indicate that better than 12 bits has been achieved, but lower noise current sources will be required for a more accurate measurement.

This paper discusses CMOS readout for an uncooled 2D IR array of resistance bolometers. Factors influencing the architectural choice and detailed noise considerations for the pixel select switch are covered. A parallel readout concept using one ADC per column is the suggested architecture for an uncooled CMOS IR array. In order to meet the requirement on speed and resolution a new ADC principle had to be developed. The ADC is however of general interest where resolution above 10 bits at medium speed and low cost are desired. High linearity is obtained utilizing the first- order delta-sigma converter technique, while resolution and speed is enhanced by a successive approximation of the delta-sigma integrator residual voltage. An experimental 16 X 16 infrared bolometer detector array has been designed where a row-by-row readout operation of the bolometer array is supported by a column-wise 16-bit A/D conversion. The 16- column preamplifiers and ADC structure has been implemented in a standard 0.8 micrometers CMOS process with 40 micrometers column pitch. Measured results of the experimental array is presented, including both electronics and detectors.

Two 8 bit successive approximation analog-to-digital converters (ADC), an 8 bit single slope ADC and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The 20.4 micrometers and 40 micrometers pitch successive approximation test chip designs are compatible with active pixel sensors (APS) column parallel architectures. A 64 X 64 photogate APS with this ADC integrated on-chip was fabricated in a 1.2 micrometers N-well CMOS process and achieves 8 bit accuracy. A 1 K X 1 K APS with 11 micrometers pixels and a single slope ADC in each column was fabricated in a 0.55 micrometers N-well CMOS process and also achieves 8 bit accuracy. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. It consumes 800 (mu) W at a 5 KHz conversion rate.

Superconducting Analog-to-Digital Converters (ADCs) are attractive for use on cryogenic focal plane arrays because of their ultra-low power consumption and their ability to operate at cryogenic temperatures. We have developed a 12 bit ADC based on Nb thin film superconducting integrated circuit technology which dissipates less than 0.44 mW while in operation at 4.2 K. Extensions of this deign to lower junction critical currents would allow the production of an ADC which dissipates less than 0.1 mW when fully biased. The ADC had at least 9.75 effective bits of resolution for 20 kHz input signals, limited by the harmonic distortions of the signal source. We estimate that the ultimate resolution of this ADC can be greater than 20 bits at 10 MHz bandwidth with our current 2.5 micron fabrication process. Potential applications for this device include focal plane array read out electronics for low temperature (4.2 K and below) imaging arrays, such as those being used on the SIRTF mission being planned by NASA. Other applications include high precision instrumentation for metrology uses.

Gallium arsenide junction field-effect transistors (GaAs JFETs) can be made immune to carrier freeze-out, allowing them to operate normally from room temperature down to 4 K. This makes GaAs JFETs attractive for the readout of detector arrays that operate at deep cryogenic temperatures (< 10 K). Typical IR readout applications, however, require transistors with very low noise and extremely low input leakage current, and until recently the leakage current of cryogenic GaAs devices was too high for many IR readout applications. By using a recently developed HF-based etchant for GaAs that is highly isotropic, etched GaAs JFETs have been fabricated that have a gently tapered edge. This reduces edge fields, which consequently reduces the edge tunneling current, the dominant source of leakage current at 4 K. JFETs with gate leakage currents below 10^-15 amps at 4 K have been fabricated. The fabrication technique, including the isotropic etchant, is discussed. The leakage current and noise of these JFETs are presented and compared with previous devices using a conventional etch.

Higher resolution and wider IR spectral coverage is needed to improved infrared sounding instruments. The Atmospheric Infrared Sounder (AIRS), chosen by NASA to fly on the Earth Observing System, addresses these needs with advanced PV HgCdTe detector arrays designed to cover the spectral range from 3.7 micrometers to 13.6 micrometers with an average resolution of (lambda) /(Delta) (lambda) equals 1200. High performance detectors and advanced readout integrated circuit electronics make it possible to meet mission requirements. For convenience, the AIRS focal plane has been partitioned into four MWIR modules spanning the spectral range from 3.7 micrometers to 8.22 micrometers , and six LWIR modules for wavelengths above 8.8 micrometers . This paper focuses on the AIRS readout device and recent developments in p-on-n heterojunction detector technology at Loral. The detector arrays, operating at 60 K, readily satisfies the requirements of the AIRS instrument. Detector arrays with 4.7 micrometers cutoff wavelength at 60 K and 20 mV reverse bias have RdAs typically greater than 10¹⁰ (Omega) (DOT) cm², with dark signals less than 0.6 fA and detector capacitances less than 0.6 pf for a 50 micrometers by 10 micrometers detector. AR coated MW arrays exhibit quantum efficiencies of greater than 80 percent. Reverse breakdowns are more than -150 mV. Module data for 15.1 micrometers detectors with anti-reflection coating exhibit quantum efficiencies greater than 70 percent and dark currents less than 8 nanoamps at 20 mV reverse bias. Also, excellent module linearity meeting the AIRS stringent requirements is achieved. Of course, measurements of MW detectors require extremely high gain transimpedance amplifiers. The AIRS MWIR readout structures prove to be exceptional in their ability to characterize these high impedance detectors. The charge sensitive input amplifiers on these readout devices utilize an equivalent input integration capacitor of less than 10 fFd to achieve ultrahigh transimpedance gain, and reset noise is suppressed with on focal plane correlated double sampling. LWIR readouts use ultralow noise buffered direct injection preamplifiers. The readouts have a robust architectures with differential input and outputs to minimize EMI and built in redundancy for survivability. Description of the readout device is presented, as well as linearity measurements of both the readout and complete modules.

ISC has developed an unique form of bump bonding based on a plug and socket concept which allows high density reflow solder array interconnects. Solder bumps with diameters of 50 microns and heights of 15 microns are plugged into sockets of photo definable polyimide 75 microns in diameter and 10 microns high. The technique is used to flip chip bond infrared detector arrays to Z-technology modules without the need for complex aligner-bonder tooling. The same method has been used for die interconnection bonding to substrates and motherboards, module to module interconnect array bonding and die to module bonding. The inherent self-alignment which occurs during reflow of an array of solder bumps has been shown useful in obtaining precise, 1 micron range, alignment accuracy between electro-optical components, such as gallium arsenide light emitting diodes and polymer waveguides deposited on a silicon substrate. The same plug and socket technology is being extended for applications using compliant polymer bumps.

Limitations inherent to the linear optical field assumption are discussed. A modified time-to-crash detector conception is proposed. The main features of our approach are a logarithmic compression of image in space, differentiation of the logarithm of light intensity in space and time, detecting local expansion using a nearest-neighbor logical circuitry, and an automatic choosing of the contour for the time-to-crash estimation. Keywords: optical flow, smart sensor, CMOS image sensor, motion sensor

Limitations inherent to the linear optical field assumption are discussed. A modified time-to-crash detector conception is proposed. The main features of our approach are a logarithmic compression of image in space, differentiation of the logarithm of light intensity in space and time, detecting local expansion using a nearest-neighbor logical circuitry, and an automatic choosing of the contour for the time-to-crash estimation.