Particles from process equipment have serious effects on the yield and profitability of a manufacturing facility. With a more advanced inspection tool, more particles are detected, but it is too costly to try to eliminate them all. It is necessary to identify the sources of the highest yield-killing defects to prioritize the efforts for effective yield improvement. This paper reviews the causes of process equipment particle and discusses the strategies and methodologies to achieve the goal of particle reduction for effective yield improvement.

Improvements in defect reduction of semiconductor processes and equipment have realized higher wafer sorts yield but have typically limited analysis and inspection of the edge of wafers by several millimeters. Sort yield on production wafers has been observed to be reduced by glass flaking and other undesired structures created on wafer edges which defect inspection typically excludes and process equipment overlooks their effect. We have taken a systematic approach to characterize integrated wafer edge processing such as size and tolerance of clamping during film deposition and plasma etching. Characterization of wafer edge processing is further refined through the use of process simulations. This modeling allows for predictive effects of changes in edge schemes as well as effects of gradual process equipment deviations such as varying clamp size during target lifetime in PVD equipment. By characterizing and modeling wafer edge processing we are able to circumvent defects that are generated by processing conditions unlike what is called for by design rules.

This paper summarized a collection of work and experimentation on detecting, classifying and reducing post developer defects. Various experiments demonstrate the effects of substrate priming, pH shock at rinse, resist hydrophobicity, rinse methods and developer surfactants in reducing post develop defects.

TiW has been used extensively as the barrier metal in submicron metallization. However, TiW has also drawn much attention as the source of defect generation contributing to functional yield loss. Usually, the defects are in the form of flakes which can be detected by either using light scattering metrology tools or naked eye in severe situations. In this paper various manufacturing techniques will be presented which reduce defect during the TiW sputtering process. Both arc-sprayed process kit (chamber shield and clamping ring) and TiW paste at fixed intervals have been proven to be effective in reducing TiW particles. Implementation of these two techniques is relatively simple and has been used very successfully in Chartered's 6 inch wafer fab. Another study shows that by reducing the process kit thermal cycling through continuously having the bake-out lamp turned on is effective for particle control. Effect of the grain size of TiW sputter target and the application of Particle Gettering (PG) foil will also be discussed in detail as other means of particle reduction.

This study provides a means of estimating the factory cost savings from defect reduction and yield improvement programs for wafer fabrication equipment. The process flow and toolset for a 0.25 micron design-rule factory manufacturing high performance logic devices are analyzed using SEMATECH's cost models. Scenarios with different sets of defect densities are evaluated and results are compared for cost per die, number of die produced, and probe yield. The various parameters analyzed and compiled are probe yield, die cost, and die cost by tool group. The defect density values are generated using SEMATECH's yield model. A Pareto analysis is provided to under stand cost benefits and prioritize potential equipment improvement programs. This effort allows SEMATECH and equipment manufactures to identify the most cost-effective defect reduction programs, thus improving capital productivity.

An advanced in-line patterned wafer defect detection system has been developed in a Joint Development Project (JDP) with Tencor Instruments and SEMATECH. The JDP, known as J101, was initiated due to critical needs identified in a SEMATECH Phase 4/5 (0.25 micrometers ) Workshop. The goal of the workshop was to identify the most suitable and cost-effective technology to meet the in-line monitoring needs specified in the National Technology Roadmap for Semiconductors (NTRS), also known as the SIA technology roadmap. This paper will review the inspection requirements identified in the SEMATECH Phase 4/5 (0.25 micrometers ) Workshop, specify the objectives and milestones of the JDP, provide a technology overview of the system, and show results obtained by using the system during alpha and prototype characterization.

Improving yield and reliability while reducing fabrication cost is a constant challenge in the semiconductor industry; in this context, while evaluating new fabrication equipment for a 3 inch fabline, unexpected physical defects occurred during reliability test at elevated temperature (300 degree(s)C): they consisted in a degradation of the 2^nd TiPtAu interconnect level, accompanied by localized cracks and peel-off of the final SiN passivation layer. This paper describes the work undertaken to find out the origin of the observed defects, to set proper process conditions and to optimize the process. Design of experiments (DOE) has been used to find out that a SiO₂ isolation layer was responsible for the occurrence of the observed defects. Then, it has also been used to model the effect of the deposition parameters as a function of the main properties of this isolation layer: uniformity, internal stress, deposition rate, etch rate in aqueous solution, refractive index, and of course generation of the above mentioned defects. Finally, making use of the model, we have achieved the optimization of the PECVD process with the following constraints: total disappearance of the mentioned defects, including reliability tests at elevated temperature, minimum internal stress of the layer compatible with best uniformity and dielectric density. The new deposition conditions have been validated through electrical measurements made on metal-insulator-metal capacitances before and after reliability test performed at elevated temperature (300 degree(s)C).

Low yield of dies near the wafer flat edge were observed for the production wafers with tungsten plug structures. All these low yield lots were processed in the specific tungsten etch back etcher (LAM RAINBOW 4720 etcher) and the total yield drop is approximately 30%. The precision cut cross section SEM picture and KLA scanning result indicate the low yield is caused by the particles fallen on the wafer surfaces during and after the tungsten etch back process. The FTIR techniques were utilized to analyze the particle contents. The particle source had been identified to be originated from the thermal degradation and recombination of the grease applied around the gap housing quad seal region in the RAINBOW 4720 etcher. The temperature near the gap housing is 15 degree(s)C higher than the set point. The high temperature environment increase the degradation and recombination reaction rate for the grease and thus generate enormous amount of particles in the etching chamber.

The impact of the defect size distribution on yield forecasting is discussed in this work. The fitting parameter p used in traditional defect size distribution modeled at X^-p was studied as a function of the process layer and process time. The importance of an accurate on-line defect size measurement is also discussed.

A method is presented for predicting the CD distribution and CD-limited yield of a photolithographic process using well established lithography modeling tools. The lithography simulator PROLITH/2 is used to generate a multi-variable process response space of final resist critical dimension (CD) versus focus, exposure, maximum resist development rate, and resist thickness. Sources of error are characterized for an actual 0.6 micron i-line process. By correlating the input error distribution with the process response space, a final simulated CD distribution is generated. This simulated CD distribution is compared with the actual CD distribution of the process. By implementing CD specifications, values of CD-limited yield metrics are calculated for the actual process and the simulated data.

In the ULSI era, 200 mm vertical furnaces are used to achieve better uniformity across the wafer and provide a smaller footprint in the clean room. The arrival of these new furnaces also brings new challenges to the diffusion area. One of them is the Negative Bias-Temperature Instability (NBTI) problem related to processing conditions during the growth of silicon dioxide. The symptom is a Flatband Voltage (V_fb) shift in the negative direction after negative bias temperature stress (this shift is in the opposite direction from a mobile ion caused V_fb shift). While NBTI has been known for many years, the exact cause and its impact upon the reliability of MOS transistors was not well understood. In this work, a set of systematic experiments varying the oxidation process conditions was performed. The focus of the experiments was on eliminating NBTI. It was observed that the wafer temperature and ambient during withdrawal from the furnace was the critical factor. Using the results of this study, the electrical field and temperature dependence of this problem are illustrated and an empirical model is established. Finally, the impact of this problem to PMOS device reliability is addressed and optimum processing conditions recommended.

The experiments confirm that the charge to breakdown Q_BD, often used for oxide monitoring, is closely related to the positive space charge formed in the bulk of the oxide layer during electron injections. The results are justified by assuming that breakdown occurs when a critical net and effective number of charges per unit area, N_C equals 5 10¹² cm^-2, is reached in SiO₂ layers. An interpretation of breakdown induced by a positive charge is proposed, based on the polarization/relaxation process previously used to explain the electron charge induced breakdown process.

In this paper, we report the case of burn-in failure due to mismatch of two structurally paired long channel N-MOSFETs (W/L equals 15 micrometers /10 micrometers ). The mismatch was attributed to substrate hot-electron induced positive threshold voltage shift under certain stress conditions. The rate of threshold voltage shift was found to be sensitive to device geometry, bias condition and stress temperature. In contrast to the channel hot electron effect, long channel devices showed large shift and the short channel device (L equals 0.8 micrometers ) was found to be stable under the same stress conditions. In addition to gate and drain bias, a positive source voltage is required to cause the shift. A large shift was observed when gate, drain and source were all biased positively. The shift was also found to increase with the stress temperature. From the MEDICI simulations, it is revealed that the rate of shift is correlated to the vertical electrical filed int eh channel deletion region with a large shift for a high vertical electrical filed. The enhanced degradation at elevated temperature suggests that the thermally generated electrons in the substrate is the source of hot electrons.

Today, electromigration-the transport of metal caused by electrical current-is one of the major reliability problem. It is well known, the grain boundary is the main diffusion path in polycrystalline lines, but do not exist in bamboo lines. The new metallizations using barrier and cap layers generate a new diffusion path at the metal interfaces. In this paper, wafer-level electromigration tests were performed on TiN/AlCu/TiN/Ti lines. The activation energy and the lifetime are extracted for three linewidths with bamboo (0.7 micrometers ) and non-bamboo structures (3 micrometers and 5 micrometers ). The values are ranged between 0.91 eV (0.7 micrometers wide line) highlighting the interfacial diffusion and 0.67 eV (3 micrometers wide line) revealing the grain boundary diffusion. The extrapolated lifetimes are calculated. The bamboo line shows a lifetime dramatically higher than the non-bamboo lines. Finally, the failure locations are determined. They are randomly distributed for the widest lines, but the failures are always located near the cathode end segment in the bamboo line. This failure location is explained by the relation between the main diffusion path and the ion flux divergence.

High-quality CVD stacked oxynitride gate dielectrics have been fabricated by in-situ rapid thermal multiprocessing. Bottom thin oxynitrides were formed by RTP of Si in the NO or N₂O ambient, followed by RT-CVD deposition of SiO₂ films using SiH₄ and N₂O. The stacked dielectrics were then subjected to in-situ rapid thermal annealing in an O₂ ambient. Results show that CVD stacked oxynitride gate dielectrics have improved endurance to interface state degradation, higher charge to breakdown values, and significantly reduced defect densities compared to control thermal gate oxide.

One of the main factors determining the lifetime of laser diodes (LD) based on A³B⁵ materials is degradation of the surface of radiation output. Rather informative for evaluation of radiating surface degradation characteristics is a so called recombination parameter S (DOT) L, where S is the rate of surface recombination and L - surface diffusion length. There were performed accelerated tests (at 70 degree(s)C) for forty five GaAs-GaAlAs LD, obtained by the process of liquid-phase epitaxy (LPE), which showed that LD's with recombination parameter S (DOT) L < 0.7 cm²/s assure lifetime of 100000 hours. Recombination parameter was estimated from LD's I-V characteristics measured in the current range 10^-9 - 10^-5 A. The following regularities were revealed: (1) Reducing of the LPE active area thickness ranging from 0.3 micrometers to 0.1 micrometers bring about reduction of the parameter S (DOT) L to the value of 3.5 (DOT) 10^-1 cm²/s; (2) LD's based on SQW-SC heterostructures with the active area thickness of 0.01 - -0.015 micrometers , have recombination parameters 5 - 6 (DOT) 10^-2 cm²/s; (3) Reducing of doping level in LPE-heterostructures active area also leads to decreasing of S (DOT) L to 5 - 6 (DOT) 10^-2 cm²/s.

N-channel field inversion leakage in multi-level-metal CMOS precesses is one of the adverse effects of back-end-of-line (BEOL) processing. In particular, using certain combinations of nitride passivation films, Spin-On-Glass (SOG), and TEOS planarization was shown to be very detrimental to the stability of CMOS circuits because of the induced leakage under field oxides. This work reports on a new field inversion leakage that is totally due to silicon oxynitride passivation. The SOG film used to planarize the inter-metal dielectric (IMD) layers did not have a significant role in the field inversion leakage as we were able to induce and suppress the leakage currents by only controlling the oxynitride passivation deposition conditions (with and without the SOG). In particular it is shown that a high oxynitride deposition temperature induces sever parasitic leakage currents while a low deposition temperature diminished the leakage.

The maintenance of consistent transistor threshold voltages is critical to the optimal performance of modern microelectronic devices. Such devices frequently have two levels of polysilicon. The doping processes associated with each polysilicon layer results in a series of highly doped structures on the surface of the wafer. Because they are exposed during subsequent thermal processes, these doped structures can also result in unintended auto-doping of associated regions on the wafer's surface. Such auto-doping can cause threshold voltage variation and is highly undesirable. This paper describes a problem encountered with a 0.8 micron double-level metal, double-level polysilicon device which exhibited erratic lot-to-lot threshold voltage variation. The device featured transistors on both levels of polysilicon, but only the second- level devices displayed the threshold voltage shift. It was postulated the voltage shift resulted from an auto-doping phenomenon caused by Phosphorous out-gassing from the doped first level of polysilicon as well as from the doped backside of the wafer. A series of experiments were conducted to confirm this hypothesis. In addition, the development of a process modification involving a barrier oxide which eliminated the auto-doping is presented. This process modification is robust, reliable, and has resulted in uniform lot-to-lot threshold voltages and improved yield.

Metallization systems, especially vias are a critical part of any VLSI chip. For the reliability prediction of vias it is important to get information on the temperature- and current density distributions in the metallization structure. Numerical methods like the finite element method FEM, give a better understanding of local heating and current crowding. With a user routine the calculation of the mass flux and mass flux divergences is possible and out of the simulations the weakest link in the structure can be determined. A qualitative comparison of the electromigration resistance between different structures can be done. A via filling with conventional techniques can lead to poor step coverages. An occurrence of shadowing effects during the sputter process of the second metallization can decrease the step coverage in the via as well and can lead to an inhomogeneous step coverage of the metallization material in the via. For a conventional aluminum via structure without barrier layers the current density and temperature distributions as well as the maximum mass flux divergences depending on the step coverage were investigated by finite element simulations. A phenomenological investigation of the influence of different inhomogeneous step coverages in the via on the mass flux divergence was done, and compared with the homogenous normal step coverage. The dependence of the overlap of the second metallization and the via aspect ratio as well as the applied current density from the maximum mass flux divergence will be investigated and the main influences determined.

A systematic study of the degradation of MOSFETs performance and reliability caused by various reactive ion etching (RIE) process steps are conducted. It is found that the polysilicon RIE process significantly increases the electron trapping as an active damage, thus causing higher initial V_t and lower initial G_m of NMOSFETs. In addition, while NMOSFETs with via antenna structures show largest RIE- induced degradation compared to other antenna devices. Our results also indicate Fowler-Nordheim stress results are well correlated with those from hot carrier stressing for monitoring RIE-induced latent damages, suggesting that Fowler-Nordheim stress is an efficient method to monitor RIE damage in a short time.

Many major semiconductor fabs are beginning to implement wafer-level reliability (WLR) as a means to improve both quality and yield of their product. Presently available WLR test structures provide a method for the reliability engineer to monitor the reliability of advanced state- of-the-art devices manufactured from CMOS, Bipolar, and BiCMOS technologies. However, these test structures also provide statistical parameters resulting from 'integrated', i.e., multiple processes. This paper examines how in-line testing of presently available WLR test structures can enable the process engineer to uniquely examine various process control parameters. Results in the form of tables and control charts show that implementation of WLR in the manufacturing area provide data useful to process, equipment, and reliability engineers.

Focused Ion Beam (FIB) systems have become a workhorse of the modem semiconductor Product Analysis Lab. They have proved invaluable in applications like specific area cross-sectioning for defect identification and process control, for materials analysis sample preparation, for e-beam and mechanical probing preparation and for design debug and fix prototyping. New generation FIB systems, with increased beam current and control have enabled new applications of the tool. This paper aims to discuss these new applications but the data is presented as it was gathered, as a series of case studies, where a particular problem encountered was overcome by innovative use of the FIB.

Early failures are the dominant concern as integrated circuit technology matures into consistently producing systems of high reliability. These failures are attributed to the presence of randomly occurring defects in elementary objects (contacts, vias, metal runs, gate oxides, bonds etc.) that result in extrinsic rather than intrinsic (wearout-related) mortality. A model relating system failure to failure at the elementary objective level has been developed. Reliability is modeled as a function of circuit architecture, mask layout, material properties, life-test data, worst-case use-conditions and the processing environment. The effects of competing failure mechanisms and the presence of redundant sub-systems are accounted for. Hierarchy is exploited in the analysis, allowing large scale designs to be simulated. Experimental validation of the modeling of oxide leakage related failure, based on correlation between actual failures reported for a production integrated circuit and Monte Carlo simulations that incorporate wafer-level test results and process defect monitor data, is presented. The state of the art in IC reliability simulation is advanced in that a methodology that provides the capability to design-in reliability while accounting for early failures has been developed; applications include process qualification, design assessment and fabrication monitoring.

A radiation treatment is used often to manufacture of semiconductor chips. Their surface layers excited by this way have the important role in reliability of produced devices. Thus, a response of the surface on the radiation affection is necessary to test. The problem may be solved using a method providing information about point defects inserted due to the considered treatment. Exoelectron spectroscopy (ES) has been developed to hit this target, taking into account an evaluation of the single imperfections concentration and their relaxation processes.

A manufacturable, directly ion implanted 0.6 micrometers GaAs metal- semiconductor field-effect transistors (MESFET) and metal-semiconductor- metal (MSM) based opto-electronic integrated circuit (OEIC) process has been developed and optimized for low cost optical data link applications. Key steps in the OEIC process have been identified and statistically quantifiable process modules have been obtained to optimize the circuit performance and achieve high process yield. The statistically significant transfer characteristics of each process module was obtained through design of experiment (DOE) and response surface modeling (RSM), by utilizing both experimental data and data from experimentally calibrated process simulators. This paper discusses the PECVD Si₂N₄ process module optimization and the backgating effects in GaAs ICs.

A comprehensive process characterization was performed at the Motorola plastic package assembly site in Selangor, Malaysia, to document the current fine pitch wire bond process capability, using state-of-the-art equipment, in an actual manufacturing environment. Two machines, representing the latest technology from two separate manufacturers, were operated one shift per day for five days, bonding a 132 lead Plastic Quad Flat Pack. Using a test device specifically designed for fine pitch wire bonding, the bonding programs were alternated between 107 micrometers and 92 micrometers pad pitch, running each pitch for a total of 1600 units per machine. Wire, capillary type, and related materials were standardized and commercially available. A video metrology measurement system, with a demonstrated six sigma repeatability band width of 0.51 micrometers , was utilized to measure the bonded units for bond dimensions and placement. Standard Quality Assurance (QA) metrics were also performed. Results indicate that state-of-the-art thermosonic wire bonding can achieve acceptable assembly yields at these fine pad pitches.

Wafer temperature in high rate and low bias RF boltage SiO₂ deposition process was monitored by pulse modulated infrared laser interferometric thermometry. With RF bias, wafer temperature sharply rose to more than 600 degree(s)C due to poor thermal conductivity between a silicon wafer and cooling stage which led to no SiO₂ deposition on silicon trenches. However, after improving the thermal conductivity, silicon trenches were successfully filled. Also, temperature dependence of fluorocarbon film deposition on a chamber wall in C₄F₈/H₂ inductively coupled plasma process was investigated. The result implies that wall temperature should be controlled over 300 degree(s)C in order to maintain CFx radical supply on SiO₂ surfaces.

With the cost of each new technology generation increasing at an alarming rate, it has become imperative that technologies which provide for process simplification and material cost reduction be seriously investigated. Many of the next generation technologies for logic as well as memory applications have incorporated some vertical modulation of the well dopant concentration. This type of structure can provide process simplification and an improved isolation strategy, but with more aggressive engineering of the substrate dopant concentration and the current gain of the parasitic bipolar transistors that exist in the CMOS structure superior, latch-up immunity has been demonstrated on both simulated and actual devices. Devices with an aggressive 2 micron P⁺ to N⁺ spacing were built with this innovative well structure and have been shown to provide outstanding latch-up performance (4X improvement in measured trigger current) as compared to that of devices built with a standard diffused well process. In addition to providing an analysis of the latch-up performance of the advanced well structure, results of an investigation of the impact of high energy implantation on the gate oxide quality, junction quality and bulk material properties is discussed.

Degradation of the electrical breakdown characteristics of SiO₂ after exposure to the silicon selective epitaxial growth (SEG) ambient is studied with a view to understand the effect on the sidewall spacers of elevated source/drain MOSFET devices. The effects of the SEG process at 850 degree(s)C-900 degree(s)C on the sidewall dielectric have been evaluated using capacitors with thermally grown or deposited SiO₂ gate dielectrics (oxide thicknesses from 15 nm to 30 nm) on polysilicon. Very little degradation of the electrical breakdown characteristics is observed after anneals in a hydrogen ambient indicating that structural void formation due to interfacial reaction between Si and SiO₂ does not occur at a rapid rate at these temperatures. Significant degradation is observed when 0.6% DCS is added to the growth ambient, which may be related to the reaction with the Si growth precursors at the SiO₂ surface. These results are confirmed by AFM measurements. After anneal in 0.6% DCS in H₂ at 1000 degree(s)C, a significant increase in roughness and in the density of etch pits at the SiO₂/Si interface is observed compared to similar anneals in a pure hydrogen ambient. Experimental results are also presented comparing the different dielectrics and the impact of Si₃N₄ spacers.

Process-induced damage to SRAM poly-load resistance have been clearly observed during photoresist ashing in an H₂O plasma which is commonly acknowledged as an effective corrosion-prevented treatment after metal etching in a chlorine-rich environment. The resistance degraded to about three order in the H₂O plasma than in the conventional O₂ plasma. Different ratios of H₂O to O₂ plasma have been studied by using the well-designed pattern to understand the basic mechanisms of the problems which occurred in the photoresist ashing process. Experimental results showed that the higher concentration of H₂O, the more damage to the SRAM products, resulting in the lower resistance of poly-load. Hydrogen ions generated from H₂O plasma are speculated to be the major culprit. Different types of plasma sources (microwave and inductively coupled plasmas) for H₂O-plasma photoresist ashing process have also been investigated and found that the damage effects to SRAM poly-load resistance in the inductive-type plasma source (such as Transformer Coupled Plasma) is more severe than that in the microwave-type plasma at the similar operation conditions. This may because inductive-type plasma has higher degree of ionization which generated more hydrogen ions inside the H₂O plasma.

The high demand for advanced, high speed and lower power MPU/ASIC and memory products has boosted the volume and revenue growth of the whole semiconductor industry during the past several years. The evolution of semiconductor technology is also gaining a lot of momentum due to the requirement/competition of the device performance advancement, power supply scaling and the breakthrough of key process equipment and technology. It used to be that memory products drove the new generations of technology. Recently, it is seen that MPU and logic products are driving the performance and density even faster than memories. All products are taking advantage of the technology and equipment advancements to shrink the device for cost reduction and performance enhancement. These new products are being introduced with high speed to the market and to volume production. This fast growing and fast changing environment will provide many challenges to the business management. Some key issues like business environment changes, technology scaling, mass production and management leadership requirements will be discussed in detail.