Only a few years ago, the primary method of cost reduction and productivity improvement in the semiconductor industry was increasing manufacturing yields throughout the process. Many of the remarkable reliability improvements realized over the past decade have come about as a result of actions that were originally taken primarily to improve device yields. Obviously, the practice of productivity improvement through yield enhancement is limited to the attainment of 100% yield, at which point some other mechanism must be employed. Traditionally, new products have been introduced to manufacturing at a point of relative immaturity, and semiconductor producers have relied on the traditional `learning curve' method of yield improvement to attain profitable levels of manufacturing yield. Recently, results of a survey of several fabs by a group of University of California at Berkeley researchers in the Competitive Semiconductor Manufacturing Program indicate that most factories learn at about the same rate after startup, in terms of both line yield and defectivity. If this is indeed generally true, then the most competitive factor is the one that starts with the highest yield, and it is difficult to displace a leader once his lead has been established. The two observations made above carry enormous implications for the semiconductor development or manufacturing professional. First, one must achieve very high yields in order to even play the game. Second, the achievement of competitive yields over time in the life of a factory is determined even before the factory is opened, in the planning and development phase. Third, and perhaps most uncomfortable for those of us who have relied on yield improvement as a cost driver, the winners of the nineties will find new levers to drive costs down, having already gotten the benefit of very high yield. This paper looks at the question of how the winners will achieve the critical measures of success, high initial yield and utilization of other cost reduction levers.

Aluminum-germanium-copper (Al-Ge-Cu) alloy is a promising material for interconnections to fill contact holes and vias using low temperature reflow sputtering due to its lower melting point than conventional Al alloys. The reflow temperature for contact- and via-filling decreases as the Ge concentration in Al increases. The suitable Ge concentration for reflow sputtering at around 400 degree(s)C is 1 wt.% of Ge. The electromigration characteristics for the Al-1%Ge-0.5%Cu alloy are investigated. It becomes clear that electromigration lifetime for Al-1%Ge-0.5%Cu is similar to that for Al-1%Si-0.5%Cu. The activation energy and n value are 0.56 eV and 3.4 for Al-1%Ge-0.5%Cu, and 0.64 eV and 4.7 for Al-1%Si-0.5%Cu. It is also found that intermetallic compounds of Al-Ti-Ge are formed at grain boundaries after reflowing.

The thermal stability of multilayered TiN/AlCu/TiN interconnect metallization and its impact on electromigration reliability performance has been investigated. Upon heat treatments at 450 degree(s)C, a monotonic increase in sheet resistance of the metal structure was observed. The test results on samples with different structures, including single-layered AlCu, AlCu/TiN(cap), TiN(bottom)/AlCu, and TiN(bottom)/AlCu/TiN(cap), showed that the sheet resistance increase due to heat treatment effect occurred only for the last two structures which had a TiN barrier. This indicates that the observed sheet resistance increase resulted from occurrence of some intermetallic reactions between AlCu and the underlying TiN barrier, but similar reactions did not occur between AlCu and the TiN in the capping layer. The result was further verified by cross sectional TEM and RBS analysis on samples with heat treatments. The heat treatment effect on electromigration performance was found to be significant leading to lifetime variations over an order of magnitude. A bell-shaped relationship between electromigration lifetime and the metal sheet resistance was found on samples receiving varying cycles of heat treatments. The observed effect is believed to be due to doping effect of Ti diffusing from the underlying TiN barrier into AlCu. It is concluded that a good control over the cumulative thermal budget is essential to assure electromigration reliability for TiN/AlCu/TiN metallizations, which is especially critical for multilevel metallizations.

A subpopulation model is used to provide a quantitative measure of the early failures in VLSI interconnects resulting from the presence of defects. Defects are attributed to processing flaws caused by particulates, improper etching, saturated stress voids, or similar causes. The model includes the effect of defect severity, grain size distribution and linewidth. To validate the model, life-tests were conducted using aluminum alloy interconnect test structures with and without a TiW barrier underlayer. Test structures included interconnects which contained lithographically introduced subtractive defects of various severities. The model and the supporting data show that greater voids in smaller grained and wider lines cause early failure with greater probability. An important conclusion of this work is that the study of the exact nature of electromigration failure distribution (Weibull or lognormal or multilognormal) is not as important as the study of defect related failures that dominate the very early failures.

A study was performed to reduce TiW particle contamination in a dc magnetron sputtering system. Significant accomplishments were obtained through simplification of shielding for the process chamber and the use of improved materials of construction. Through the implementation of this enhanced hardware, maintainability benefits were obtained in the areas of shield use (66% reduction), equipment downtime (30% reduction), and maintenance labor (> 3 hours/shield change). In addition to these, overall particle counts were reduced significantly. Lastly, improvements in film uniformity across a wafer were improved by 0.5%, 1 (sigma) , based upon sheet resistivity contour maps.

Electron beam probing is a powerful technique for analyzing failures in integrated circuits. This technique has been modified and different automation techniques such as IDA, FACE and analysis techniques have been added to analyze complex circuits. However, with increasingly small geometries and multi levels of metallization none of these techniques can work satisfactorily unless the e-beam can manage to obtain signals from the bottom metal layers. In this paper we present a successful method which has been used with a 4 metal layer process to probe up to metal 1. As geometries shrink it is absolutely necessary that after removal of intermediate dielectric no residue remains, otherwise there could be intermetallic shorts. RIE has been used successfully for failure analysis. In this paper we present a method of selectively removing inter-metal dielectric using RIE and doing e-beam probing. RIE is so optimized that there is no `RIE grass' and 3/4 metal layer ASICs with 0.5 micrometers minimum geometry function electrically. Using special fixtures and optimizing the gas flow, gas pressure and power, the removal of dielectric was so optimized that: (1) The amount of intermediate dielectric removed can be varied just by time. This is necessary to stay compatible with different technologies using different metal layers and dielectric thickness. (2) There is no `RIE grass.' (3) Devices function electrically even after removal of intermediate oxide and metal 1 is exposed. After the dielectric is removed the parts are exercised electrically using an ATE for instance ASIX or LT and measurements are taken using the e- beam tester IDS5000+. This paper discusses in detail the RIE process, fixtures, and the usage of the e-beam tester on multilayer 0.5 micrometers process.

A simple deposition model of evaporated species into quarter-micron contacts on an 8-inch diameter wafer, considering the scattering by gas molecules, predicted that the narrow angular distribution of evaporated species and deposition under low vacuum pressure are essential conditions for sufficient coverage of the contacts. An ionized cluster beam (ICB) technique satisfies these essential conditions. Furthermore, computer simulation revealed that rotating the wafer and setting the ion sources off-axis of the wafer center are required in order to obtain bottom coverage uniformity within an 8-inch diameter wafer. The bottom coverage of TiN barrier film deposited under a nitrogen pressure of less than 10^-2 Pa into contacts with an aspect ratio of 3.5 was improved to about 30% and the bottom coverage uniformity was about +/- 5% within the wafer. The crystal structure of the film formed by ICB was confirmed to be (111) orientation, which is necessary to from a preferentially oriented aluminum layer with a high durability against electromigration on TiN barrier film. The contact resistance and the leakage current of contact with 0.5 micrometers diameter and 1.5 micrometers depth processed by ICB were lower than 50 (Omega) and 10^-10 A respectively at the bias voltage of 10 V.

Contamination control is a major issue in VLSI fabrication. Particle control, in particular, is crucial to the success and profitability of the manufacturing process. While most production lines have a particle monitoring system, the direct correlation between defect level and device yield is not always obvious, and therefore prioritizing quick yield improvement efforts can be difficult. This paper discusses a solution with the total particle control system which has provided a practical method for yield enhancement.

A very high selectivity is required in most of the plasma etching processes for the fabrication of subhalf micron devices. One of the most critical steps is the polysilicon etch, in which the etch stop layer is a thin oxide of 50 angstrom to 100 angstrom. An extended overetch is generally required to remove polysilicon stringers at the bottom corner of the topological steps. During this overetching step microtrenching can become a problem when the thin oxide film at the bottom corner of the polysilicon structure is removed. In the contact etch a very high selectivity is also required due to the increased aspect ratio and depth variation of the contact holes. High selectivity to the silicon substrate or to the thin silicide layer insures minimal loss of substrate silicon or silicide in the shallow contact region. In spacer etch, especially when dealing with SOI devices using an ultrathin silicon layer, a substantial amount of silicon can be lost if selectivity is not high enough, causing uncertainty in the composition and thickness of the silicide layer formed in the subsequent silicidation step. Oftentimes the problems in these plasma etch processes can not be detected until the device is tested after the completion of the metallization step. Due to the time lag, it is difficult to trace the real causes of the problems. This can represent a significant monetary loss especially when dealing with larger diameter wafers. An inline monitoring method is very essential especially in a high volume production environment. Analytical techniques such as TEM cross sectional work or even high resolution SEM work is difficult to implement as an in-line monitoring method. Controlling the etch processes by measuring the etch selectivity may be very troublesome. Determining a slight change of thickness of the etch stop layer in a highly selective process is quite difficult. Also, in most cases the structure on the test wafers is very different from the actual devices. Important parameters such as percentage of resist coverage or effect of line width and spacing, etc., are mostly ignored.

Field-programmable ASICs have been implemented using a variety of programmable circuit elements, including SRAM, EPROM, E²PROM, and antifuse cells. Amorphous silicon (a-Si) antifuse cells offer greater packing densities and superior performance compared to cells based on memory elements, and they can be integrated into conventional multi-layer integrated circuits with the addition of several process modules. Despite their advantages, a potential yield issue with a-Si antifuses is that their electrical characteristics can be affected by damage from manufacturing processes. In this study, it is found that the programming voltage is reduced when a solvent-based post-resist strip solution is applied to the bottom electrode layer of TiW. Atomic-force microscopy (AFM) shows that the resist strip solution increases the micro-roughness of TiW films. It is also found that the `off-'state leakage current increases when the solution is applied to the a-Si antifuse layer. The amount of the leakage current increase is related to the amount of a-Si loss due to the strip solution.

One of the major sources of particles today is from processing equipment. As die size continues to shrink, more effort needs to be placed in defect detection and elimination. A defect of 1 - 2 microns in size, while barely noticeable 5 years ago, can now destroy an entire die. Even with redundancy, a metal defect 1 micron in size will result in excess leakage due to an array short. While missing metal may be repairable, metal flakes from sputtering machines, for example, result in nonrepairable die. The objective of this paper is to show how backend defect reduction and yield enhancement can be improved with the use of the newer defect detection tools. We discuss three defect problems at different process levels which were discovered and eliminated with this work. The term `process induced defects per wafer pass' (PIDPWP) is demonstrated.

New giant-far-action lateral phenomenon (GFALP) in ion/laser beam semiconductor microstructure fabrication is observed to be the initial cause of defects mobility activation in microelectronic devices, device microstructures mutual influence and contamination of working areas of elements by defects of processing origin within a whole device crystal. The giant-far-action lateral phenomenon consists in point defects generation at local crystal surface modification by any means (for example: ion/laser beam or diamond incisor) and deep sideways penetration of defects (vacancies and interstitials) out into the initially clean material under the pressure of mechanical strains that occur at the boundary of the modified region. In case of high implantation dose (10¹⁶ ions/cm²), laser solid state diffuse doping, laser beam annealing of implanted semiconductor surface, or laser beam /mechanical scribing of wafer surface the scale of GFALP lateral effect exceeds 1 mm. Besides, at heavy implantation dose, point defects concentration exceeding 10¹⁸ defects/cm³, a phase transition of vacancy to dislocations in the gaseous phase of point defects was observed to occur with consequent dislocation sliding at a distance of more than 150 micron aside the boundary of the implanted zone.

Exoelectr on anal yzes C EAD of poi nt defects both i n crystalline and amorphous semiconductors is considered. The below concentrati on threshol ds of poi nt defects and Ion—implanted impurities that may be estimated by this method are 17 -3 13 1 -310 .. . 10 cm and 10 . . . 10 cm , correspondingly. Keywords: point defects, testing, semiconductors, exoelectron anal yzes.

Plasma etching degrades the gate oxide in scaled down MOS transistors and therefore affects the device low frequency noise behavior. The effects of plasma etching induced gate oxide damage on MOSFETs 1/f noise have been studied on devices fabricated with different field plate perimeter to gate area ratio antennas on various metal levels. The correlation between plasma etching induced gate oxide damage and device 1/f noise has been observed. The plasma etching introduces oxide trap centers near Si/SiO₂ interface, which give rise to an abnormal shoulder in device 1/f noise spectrum. This is confirmed by reproducing the abnormal noise spectrum on device which initially received less damage during plasma processing by means of performing Fowler-Nordheim stress and forming gas annealing. The correlation between hot-carrier injection degradation and device abnormal 1/f noise was also observed, implying that plasma etching causes abnormal 1/f noise. The physical properties of the traps were studied by the gate bias and temperature dependence of the device 1/f noise.

A new wafer cleaning procedure has been developed for ultra-thin thermal oxidation process (<EQ 50 angstrom). This involves a modified RCA clean and a two-step dip, first in diluted HF and then in a methanol/HF solution, with no final DI water rinse. Ultrathin thermal oxides (48 angstrom) and oxynitrides grown in N₂O (42 angstrom) were prepared using this new cleaning and other commonly used cleaning methods to investigate the effects of surface preparation on dielectric integrity. It has been found that this two-dip method produces dielectrics with reduced leakage current and stress-induced leakage current, which are believed to be the critical parameters for ultrathin oxides. Furthermore, this new cleaning procedure improves both intrinsic and defect-related breakdown as well as the uniformity of the current- voltage characteristics across a 4-inch wafer. The methanol/HF dip time has also been optimized. The improvement is believed to be due to enhanced silicon surface passivation by hydrogen, the reduced surface micro-roughness and the absence of native oxide.

In order to guarantee oxide quality for non-volatile memory devices, it is important to be able to monitor defectivity at end-of-line parameter testing. This is the only place where we can screen out the intermediate defectivity which electrical testing cannot detect on all wafers processed. The traditional reliability monitors cannot address this application due to their small sample size, long test time and high cost. In this work, an end-of-line monitor using four scribe line capacitors is proposed. Two gate oxide and two interpoly dielectric structures can be easily measured at parameter testing. Both protected and unprotected capacitors are used to separate out charging effects. These structures can be measured in line after gate definition and can be used to supplement standard gate oxide monitors (GOMs). Using this approach we can quickly detect and correct any deviations in the process that determine oxide quality.

The purpose of this work was to reduce isolation oxide defect density and improve gate oxide integrity by modification of wet oxide strip and pre-diffusion clean. Work was done on 1.0 micrometers and 0.8 micrometers M²CMOS twin-well technology. Twin-wells are defined by local oxidation process using nitride layer. Active area is also defined by local oxidation. MOS gate is built of POCl₃ doped polysilicon on top of 185A oxide.

The impact of two different quartzglass materials, electric fused (E-material) and flame fused (F-material) on silicon and silicon devices has been investigated, by performing a test process consisting of oxidation, well drive-in and gate oxide. Thereby silicon wafers had direct contact (boat-simulation) and proximity contact (tube-simulation) with the quartz. Metal contamination induced defects have been evaluated using photocurrent imaging (Elymat) for bulk recombination centers and near-surface precipitates together with E-ramp breakdown on gate oxides. The results of both tests indicate a significantly lower impact of flame fused quartzglass material on bulk as well as on surface of silicon and properties of silicon and silicon test devices.

Constant current Fowler-Nordheim electron injection experiments were performed on Si/SiO₂/poly-Si structures with and without a TiSi₂ superlayer. It has been shown that phosphorus atoms implanted into the 3500 A thick poly-Si to a dose (3-9)*10¹⁵ cm² followed by the 850 degree(s)C - 950 degree(s)C post implantation anneal lead to the deterioration of electrophysical characteristics of the MOS-capacitors on the one hand and on the other hand result in an improvement of the endurance against hot electron injection. Sintering of 200 A Ti at various (700 degree(s)C - 850 degree(s)C) temperatures to form TiSi₂ leads to the decrease (about three times) in the sheet resistance of polycide gate and does not effect the metal-semiconductor work function. To explain these phenomena we consider two mechanisms of electronic defects appearing and disappearing. The first mechanism is connected with the Si-P bonds creation that have a larger binding energy than the Si-Si, Si-H, Si-OH bonds. The other one takes into account H-ions generation at the poly-Si/SiO₂ interface and either the Si defects possivation or the Si-Si and Si-O bonds cleavage by them.

The continuing trend toward smaller device feature sizes and the increasing demand for ever greater levels of reliability has resulted in an increased level of interest in the problem of low- level current leakage. Not only do previously acceptable levels of leakage become problematic at smaller device geometries, but a low-level of current leakage is a good overall indicator of device defectivity, and thus reliability. Experiments have been conducted in which a specific HF clean was observed to significantly reduce leakage in polysilicide CMOS devices. It is theorized that the HF clean removes contaminants located in the top 100 angstrom of the gate oxide over the source/drain regions. These contaminants are driven into the gate oxide during subsequent thermal processing and result in the creation of low-level current leakage sites. This paper describes the character of a current leakage problem encountered on a polysilicide CMOS device which has an extremely low current leakage specification (< 600 nA). The development and optimization of a process modification involving screen oxide and an HF clean which eliminated the source of low-level current leakage is presented. This process modification is currently in use in an industrial environment, is robust, reliable, and has resulted in a substantial increase in yield.

Low frequency noise measurements of n-p-n polyemitter bipolar transistors showing an increasing base current 1/f noise amplitude spanning seven orders of magnitude and increasing exponential dependence on biasing current between Ib and Ib² with increasing emitter interfacial oxide continuity and decreasing emitter junction depth are described. Coupled with corresponding variations in linearized and large signal device characteristics, these trends lead to base voltage noise intensities that can both increase and decrease with increasing biasing current within the moderate 0.6 V < Vbe < 0.8 V biasing range. This behavior has not been previously attributed to the combination of fundamental base current noise and its noise voltage transfer function explicitly, but has importance to the assessment and accurate modeling of polyemitter transistor noise performance in shallow emitter transistors. The large range and high resolution of these features also imply that low frequency noise may be useful in characterizing the structure of the broken emitter interfacial oxide layer and its electrical properties.

Plasma-induced gate oxide degradation has been investigated using CMOS device structures, as well as single-channel MOSFETs. The plasma process induces both interface states and oxide charges in n-ch and p-ch MOSFETs. Although forming gas anneal recovers or masks most of the damage, the damage reappears in the form of reduced hot carrier reliability. The study of dual-gate MOSFETs, in which an antenna aluminum-pad is shared by n-ch and p-ch MOSFETs, shows that the plasma charges collected by the antenna are equally divided between n-ch and p-ch MOSFETs. This indicates that the nature of the plasma stress acting on MOS devices is more like a current source. It was also found that a floating well structure used for CMOS does not protect MOSFETs from plasma damage.

This paper presents some novel fault localization techniques for a memory LSI by using an EB tester. Effective techniques for applying pulse combinations of input signals and acquiring images are put forward. Excellent voltage contrast images are acquired on the passivated devices without degradation of voltage contrast from charge up. Signal lines are back-traced by comparing good and bad images to identify the failure point. Application to the failure analysis of DRAMs is successfully performed with minimal time requirements.

One commonly used method for identification of defect contributions from different processing steps is micropartitioning. Micropartitioning allows one to evaluate the total number of defects that are added at a single process step or from a series of process steps. One can then perform a pareto analysis of the defect sources to determine the key area(s) in need of defect reduction. In general this methodology works fine, but it does not take into account whether or not the defects are electrically active. By using a similar methodology to micropartitioning, with the addition of an electrical test pattern, it is possible to identify the sources of electrically active defects. This study demonstrates a methodology for identification of the sources of electrically active defects, and compares these results to the results of micropartitioning of process modules using defect detection tools.

Progressively censored data obtained from accelerated life time tests on contact chains of individual contact interconnect (CI) systems connected by probe pads were compared to simulated complete data sets. Depending on stress conditions, the time required to gain 1% of precision (95% confidence) of low percentiles, t_prec, can be as low as 2% of that required for complete data. As progressive censoring allows for the start of experiments with a high number of objects, simultaneous failures of CI systems are observable. It turned out that ignoring these `multiple failures' (`MFs') can lead to a considerable overestimation of reliability, if `MFs' are accumulated at early failures. A new test structure allowing for automated testing of individual CI systems in series is proposed. Several methods of evaluation of data obtainable from the test structure are discussed in detail using maximum likelihood estimation of simulated data. A `1 out of X' assumption of detected failed subparts of the test structure turned out to be sufficient in most cases of possible accumulations of `MFs.' Life time is overestimated if early `MFs' are ignored. The problem of assessing normality of complete, and progressively censored data is discussed.

Mechanical stresses change energy gap in semiconductors. Thus, a photoelectric work function is dependent on this effect. In such a view surface layers elastic deformations are recorded by measuring of photoelectron emission quantum yield.

As geometries continue to shrink, the reduction of alkali ion contamination in integrated circuits is imperative. A Motorola factory established a goal to achieve greater than an order of magnitude reduction in alkali ion levels through characterization and elimination of the sources. Various teams contributed to the overall goal by identifying sources and focusing on reducing or eliminating the alkali ion levels. Reliability improvements have been accomplished over the past three years utilizing this methodology.

As integrate circuit geometries, capital for defect detection equipment, and process cycle time decrease simultaneously, prioritizing continuous yield improvement activities becomes essential. One approach for achieving this goal is to integrate yield enhancement resources. The resources available for integration have been failed bit map analysis, inline defect monitoring, molecular contamination detection, and failure analysis. The analytical systems chosen to support these activities have included a scanning electron microscope (JEOL 840FE), an energy dispersive x-ray system (EDAX), a focused ion beam mill (Micrion), a secondary ion mass spectrometer (Cameca IMS3F) -- as well as inspection systems equipped with laser based scanning for pattern anomalies and surface contamination (Tencor Surfscan 7XXX). Combining these techniques and tools facilitates efficient manufacturing process partitioning and root cause analysis leading to continuous improvement.

The new nondestructive contactless method of analyzing plane distribution of some electrophysical parameters of silicon wafers is proposed for discussion. This method makes possible the easy control of the volume lifetime, oxygen precipitates density and resistivity variation on plates square with a laser spot diameter resolving. In the experiment the microwave photoconductivity kinetics curves were obtained at 1000 points on the area 7.5 X 1.875 mm. Each of these curves was one of two types -- the exponential decay (with two parameters: time and amplitude) and decay with the long tail (in rough description with four parameters). As it was shown in preliminary studies from exponential decay it's possible to obtain information about volume lifetime variation (or after additional experiment -- about the surface quality) while from nonexponential decay the additional information about oxygen precipitates concentration can be obtained. The fundamentally new opportunity which becomes possible due to mapping is the obtaining of the resistivity variation picture. Roughly speaking, this picture can be obtained from the analyzing of the amplitude of exponential decay. As the lifetime is measured independently and microwave device tuning is not changed drastically from point to point -- so one can obtain the picture of wafer resistivity from computer processing of pictures of amplitude and time constant of exponent.

Electron beam probing is a powerful technique for analyzing functional failures in integrated circuits. A common approach used for isolating defects is to trace a bad signal on a failing pin through the circuit. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. This method has several limitations which are discussed in this paper -- most notably, it is often an extremely time consuming process. Scan- path designs have been introduced which increase the observability and controllability of internal circuit nodes. The use of ASIC scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional failures. In this paper we present a successful method of defect isolation using scan-path testing in conjunction with electron beam probing. Using this method, a fault area or node is identified using a test datalog, and the defect is precisely located using an electron beam probe station. This paper discusses in detail the integration of scan testing with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements.

With growing complexity of VLSI designs and shrinking device geometries, diagnosis and characterization efforts require more powerful tools. To improve the yield, it is essential to be able to quickly locate failures. The `standard' way for analyzing device failures has been to locate the failing cell schematics, simulate all nodes of the cell and compare the results to mechanical probing measurements. This process can be very time consuming, cumbersome, and destructive to the device. In this paper we describe how LPISEM (LSI Logic's photoemission, ion-mill & e-beam system) addresses the ASIC diagnosis problems. The photon detection system in the LPISEM allows the designer to `zoom' into the leakage sites in the unit under test (UUT). The non-destructive nature of LPISEM allows the comparison of simulated versus measured results interactively and visual inspection of the area of the leakage site. In addition, a schematic driven navigational interface helps the user to locate and probe the suspected area as follows: (1) Use the photon detection system to locate the leakage site. (2) Display the leakage site area on the SEM window where it can be probed and visually inspected. (3) Highlight the node of interest on the layout window (Calma Database). This automatically locates the net. (4) The actual and simulated waveforms for the suspected node are displayed on the scope tool. (5) Focussed ion beam can be used to identify and verify failures. The LPISEM consists of the following components: a KLA-EMMI (emission microscope for multilayer inspection), a Schlumberger IDS5000+ E-Beam prober, LSI Logic's Concurrent modular design environment simulation and verification tools, and SEIKO SMI8300 ion miller and VLSI tester. The integration of these components provides unique and uniform interface for users.

A Monte-Carlo reliability simulator for integrated circuits that incorporates the effects of process-flaws, material properties, the mask layout and use-conditions for interconnects is presented. The mask layout is decomposed into distinct objects, such as contiguous metal runs, vias and contacts, for which user-defined cumulative distribution functions (cdfs) are used for determining the probability of failure. These cdfs are represented using a mixture of defect- related and wearout-related distributions. The failure distributions for nets, which are sets of interconnected layout objects, are obtained by combining the distributions of their component objects. System reliability is obtained by applying control variate sampling to the reliability network which is comprised of all nets. The effects of series, parallel and k-out-of-n substructures within the reliability network are accounted for. A Bayesian approach to incorporating burn-in data with simulated estimates is also presented. A program that interfaces directly with commercially used CAD software has been implemented. Results provide a qualitative verification of the methodology and show that predictions which incorporate failures due to process flaws are significantly more pessimistic than those obtained by following current practice.

Metal-organic chemical vapor deposition (MOCVD) is an important fabrication process used to grow thin epitaxial films on solid substrates. The development of an accurate and efficient model for this technique is therefore quite desirable from a manufacturing standpoint. In this paper, semi-empirical modeling of TiO₂ film growth by MOCVD using a hybrid neural network is introduced. This hybrid model combines the best aspects of physical models and purely empirical methods. The model was constructed by characterization of the deposition rate of TiO₂ films under various operating conditions. A modified back-propagation neural network was trained on the experimental data to determine the value of three critical unknown parameters of the physical model. Using this approach, comparison with measured data showed that the hybrid model is capable of predicting the TiO₂ deposition rate with a high degree of accuracy.

This paper presents a new dynamic dispatching rule to improve delivery. The dynamic dispatching rule named `SLACK and OTD (on time delivery)' is developed for focusing on due date and target cycle time under the environment of IC manufacturing. This idea uses traditional SLACK policy to control long term due date and new OTD policy to reflect the short term stage queue time. Through the fuzzy theory, these two policies are combined as the dispatching controller to define the lot priority in the entire production line. Besides, the system would automatically update the lot priority according to the current line situation. Since the wafer dispatching used to be controlled by critical ratio that indicates the low customer satisfaction. And the overall slack time in the front end of the process is greater compared to that in the rear end of the process which reveals that the machines in the rear end are overloaded by rush orders. When SLACK and OTD are used the due date control has been gradually improved. The wafer with either a long stage queue time or urgent due date will be pushed through the overall production line instead of jammed in the front end. A demand pull system is also developed to satisfy not only due date but also the quantity of monthly demand. The SLACK and OTD rule has been implemented in Taiwan Semiconductor Manufacturing Company for eight months with beneficial results. In order to clearly monitor the SLACK and OTD policy, a method called box chart is generated to simulate the entire production system. From the box chart, we can not only monitor the result of decision policy but display the production situation on the density figure. The production cycle time and delivery situation can also be investigated.

Statistical metrology seeks to assess the sources and magnitude of variation in semiconductor manufacturing. The methodology emphasizes electrical measurements resulting from short process flows, statistical design of experiments and analysis of data, and close coupling to technology computer aided design tools for the interpretation of data. In this paper, we apply statistical metrology to interlevel dielectric thickness variation. Capacitive test structures, in conjunction with resistive line width structures and two-dimensional capacitance simulations, are used to estimate ILD thickness for a variety of layout and process factors in a poly-metal BPSG planarization process. The methodology is successful in highlighting the key factors, including underlying structure line width spacing,and finger length that impact ILD thickness. Future work will examine other planarization processes, including chemical mechanical polishing.

In lead-on-chip (LOC) packaging technology, the lead fingers are auached directly to the surface of the chip using a double-side adhesive tape. This method of chip attachment naturally leads to concerns about stress on the polyimide coated chip surface. Device failure related to fracture in the passivation layers and the Al-Si metal has been observed in temperature cycle tests. To investigate the effect of material characterization on the surface damage, devices were fabricated with different types of molding compounds, tapes and polyimides. This paper describes the optimum material properties, the assembly process parameters, and the experimental and simulated results of the surface damage. Keywords: surface damage, LOC package, polyimide, tape, mold compound, simulation

Wafer level reliability (WLR) was envisioned as an upstream tool to be applied within the wafer fab process to avoid or detect reliability problems before they can reach the fmished product. To demonstrate a practical application of this approach, the development, execution and results of a WLR qualification and production control plan for an advanced, sub-micron, triple-level metal CMOS process is provided. The WLR qualification evaluated the following reliability concerns: oxygen precipitation, contact integrity, hot carrier reliability, mobile ion contamination, dielectric integrity, electromigration, stress voiding, via integrity, and corrosion susceptibility. The production control plan describes a statistical process control (SPC) program which monitors input process parameters and electrical parameters measured prior to fmal test that are used to disposition lots. Keywords: wafer level reliability, building-in reliability, designing-in reliability, process control, qualification.

A methodology to include cost and yield estimation in a comprehensive TCAD model of semiconductor processing is presented. The underlying idea is that a process recipe used to drive TCAD simulators contains a complete set of information about the process. If it is combined with empirical equipment data, a set of models can be constructed to describe cost as a function of the process recipe and equipment data. This paper presents a user-configurable cost modeling tool tightly integrated with TCAD simulators, enabling the user to study related and important questions of cost and yield not covered by traditional TCAD tools.