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Microelectronics Manufacturability, Yield, and Reliability
Editor(s): Barbara Vasquez; Hisao Kawasaki

*This item is only available on the SPIE Digital Library.

Volume Details

Volume Number: 2334
Date Published: 14 September 1994

Table of Contents
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Yield: it's now an entitlement
Author(s): Bill George
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Electromigration characteristics for Al-Ge-Cu
Author(s): Kuniko Kikuta; Takamaro Kikkawa
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Effect of heat treatments on electromigration performance for TiN/AlCu/TiN interconnect
Author(s): Larry L. Ting; Qi-Zhong Hong
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Subpopulation model for void-related early failure in VLSI interconnects
Author(s): Satish S. Menon; Kelvin F. Poole
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Improved PVD TiW manufacturability using advanced chamber shield design
Author(s): Jay N. Sasserath; Ron Yenchik
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Defect isolation using electron-beam probing RIE in multilevel high-density ASICs
Author(s): Sharad Prasad; Grant Lindberg; Hong Zhang
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High-coverage barrier-film formation by ionized cluster beam
Author(s): Hiroyuki Ishii; Yoichi Hashimoto; Hisashi Tsukazaki; Masahiro Hanai; Hiroki Ito
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Yield enhancement with particle defects reduction
Author(s): Kiyoshi Mori; Nam Nguyen; Dewey Keeton; Ross Burns
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Monitoring of highly selective plasma etch processes
Author(s): Jer-Shen Maa; Lynn R. Allen; Dave Evans; Tzu Yen Hsieh; Bruce D. Ulrich; Sheng Teng Hsu; John M. Grant; Greg Stecker
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Effects of resist strip processing damage on the electrical characteristics of 0.8-um a-Si antifuse circuit elements
Author(s): Felix Fujishiro; Landon B. Vines; K. S. Ravindhran; Yu-Pin Han; Danny Echtle; Annette Garcia; Brian Richardson; Milind Weling; James Hickey; Ying-Tsong Loh
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Yield enhancement through monitoring of real-time manufacturing processes
Author(s): Neil Bryan Henis; Michael J. Satterfield; Edward O. Travis; Carol Gelatos
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New phenomenon in ion/laser beam semiconductor microstructure fabrication: impact on reliability
Author(s): Sergei Yurievich Sokolov
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Exoelectron emission testing of technology inserting point defects into semiconductors
Author(s): Yuri Dekhtyar
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Effects of plasma-etching-induced gate oxide degradation on MOSFET's 1/f noise
Author(s): Chun Hu; Scott T. Martin; Eugene Worley; Joe White; Ray Kjar; Guann-pyng Li
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Surface cleaning effects on reliability for devices with ultrathin oxides or oxynitrides
Author(s): Kafai Lai; Ming-Yin Hao; Wei-Ming Chen; Jack C. Lee
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In-line monitoring of thin oxide on production wafers using large scribe line capacitors
Author(s): Luca Perego; Martin Duncan
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Yield enhancement by modification of wet oxide strip processes
Author(s): Israel Rotstein; Eitan N. Shauly
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Influence of quartz glass on silicon wafers during thermal processing
Author(s): Dietmar Hellmann; Thomas Falter; Rudolf Berger; Edmund Burte
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Effects of P+-implanted poly-Si gate with and without TiSi2 on the injection degradation of thin film oxides
Author(s): Victor M. Ivkin; Valentin V. Baranov
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Reduction of low-level current leakage in CMOS devices
Author(s): George Y. Kong; Jerry T. Healey
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Characterization and modeling of base current in n-p-n polysilicon emitter bipolar transistors using low-frequency noise analysis
Author(s): David Quon; Yang Hua Chang; Gregory J. Sonek; Guann-pyng Li
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Plasma-induced gate oxide degradation and its impact on oxide reliability for CMOS FETs
Author(s): Ko Noguchi; Koichiro Okumura
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Memory failure analysis using EB voltage contrast image
Author(s): Hiroyuki Hamada; Tohru Tsujide; Kazuo Nakaizumi
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Methodology for identification of process-induced electrically active defects
Author(s): Loren C. Krott
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Progressive censoring: an efficient method to reduce time consumption of accelerated lifetime tests
Author(s): Hans-Dieter Hartmann
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Emission local testing of mechanical stresses in surface layer of silicon
Author(s): A. Balodis; Yuri Dekhtyar; G. Sagalovich
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Reliability improvement of integrated circuits through alkali contamination reduction in dielectric films
Author(s): Carrie Lundquist; Tara Allen; Rafael Delgado; S. Dunnigan; J. Cadenhead; Karl E. Mautz; Jim Peterson; H. Stevens
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Integrated approach to yield enhancement
Author(s): Martha A. Cockerill; Neil Bryan Henis; Carrie Lundquist; Elizabeth D. Marshall; Gus Raad
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Mapping of silicon wafers on shallow, middle, and deep level centers
Author(s): Vadim A. Nikitin
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Defect isolation using scan path testing and electron beam probing in multilevel high-density ASICs
Author(s): Grant Lindberg; Sharad Prasad; Kaushik De; Arun Gunda
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Faster approach to ASIC diagnosis: LPISEM
Author(s): Sharad Prasad; Upendra Brahme
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Reliability simulator for improving IC manufacturability
Author(s): Mohamod S. Moosa; Kelvin F. Poole
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Semi-empirical MOCVD modeling using neural networks
Author(s): Ziba Nami; Ahmet Erbil; Gary Stephen May
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New methodology for dynamic lot dispatching
Author(s): Wei-Herng Tai; Jiann-Kwang Wang; Kuo-Cheng Lin; Yi-Chin Hsu
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Statistical metrology for interlevel dielectric thickness variation
Author(s): Duane S. Boning; Tinaung Maung; James E. Chung; Keh-Jeng Chang; Soo-Young Oh; Dirk Bartelink
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Temperature-cycle-induced chip surface damage in lead-on-chip packages
Author(s): Masazumi Amagai
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Practical application of a wafer-level reliability control program
Author(s): Jeff S. May; Javier Saenz; Hoang Huy Hoang
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Cost and yield estimation in a virtual IC factory
Author(s): Valery Axelrad; Yuri Granik; Victor V. Boksha; J. G. Rollins
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