Single wafer multiprocessors generally in the form of cluster tools are gaining increasing importance in commercial semiconductor product manufacture. This paper describes potential cost-related and timerelated advantages that could come from the multipmcessors. Next hypothetical conventional and clusterbased fabs are simulated. The simulations results are discussed in terms of their evidence for the cost and time advantages of the fabs. One general conclusion is that cluster tools can be used to achieve very short throughput times at a premium cost per wafer. Finally based on the potential advantages and the simulation results three areas of non-process issues are discussed which will determine the extent of the multiprocessors'' economic utility. These areas are cost time and fab management related. 1

Silicon processing makes ever-increasing demands on the capabilities and quality of processing equipment. Rapid thermal processing (RTP) enables the use of thermally activated processes with the minimum thermal budget. Multi-chamber systems minimise turn around time whilst providing a high quality processing environment. This paper seeks to identify the issues associated with the use of RTP in multi-chamber systems from the reasons for considering it to the further work required to optimise it. 1.

Rapid thermal alloying and sintering of metal ohmic contacts such as AuBe PtTFi and W to InP-based materials is shown to perform with better electrical properties than the same contacts heated by means of conventional furnace. The metalsemiconductor interfacial reactions induced by the rapid thermal processing were much shallower than those formed during the conventional heating cycle at the same temperature however with a negligible influence on the overall stresses developed in the film. These results demonstrate the superiority of the rapid thermal processing over the conventional furnace heating in sintering the metal electrical contacts and its potential while integrated into the overall manufacturing process sequence of the InP based photonic devices.

Rapid isothermal processing (RIP) based on incoherent sources of light is emerging as a reduced thermal budget (product of processing time and temperature) processing technique. As compared to a stand alone annealing unit the integration of RIP with other processing units leading to integrated RIP systems is very attractive for the next generation of devices and circuits. From cost and performance point of view the integrated rapid isothermal processing of these devices offers several advantages compared to their exsitu rapid isothermal annealed and furnace annealed counterparts. We have used an integrated RIP system for the insitu rapid isothermal surface cleaning of InP and GaAs substrates and insitu metallization of InP and GaAs Schottky diodes. As compared to exsitu annealing insitu rapid isothermal cleaning of InP and GaAs surfaces prior to metallization followed by insitu annealing results in improved electrical characteristics. We have also integrated a plasma source with a RIP system and studied the thermal oxidation of Si at 300C followed by an insitu rapid isothermal anneal. In this paper we also show that photo effects play a significant part in RIP. I.

A low-temperature (600-750C) dry surface cleaning process has been developed for in-situ removal of native oxide layers and other surface contaminants. The cleaning process chemistry consists of a mixture of germane (Ge114) and hydrogen (112) gases with very low germane-tohydrogen flow ratio (10-20 ppm). The process parameters (e. g. temperature pressure and CeH4:H2 gas flow ratio) were adjusted in order to prevent deposition or surface nucleation of germanium during the thermal cleaning process and to minimize the stacking fault densities in the epitaxial silicon layers deposited following the in-situ germane-assisted cleaning steps. The insitu dry surface cleaning processes developed in this work also include associated Ge114/112-based chemistries with a halogen-containing additive gas such as llCl and/or HF. These surface cleaning processes can be easily integrated with various thin film growth and deposition processes such as epitaxial growth gate dielectric formation and polycrystalline or amorphous silicon deposition for MOS and bipolar device fabrication.

Manufacturing of advanced integrated circuits requires extreme control of ''wafer processing" induced defects from process tools manufacturing environment and manufacturing disciplines. In order to minimize handling induced defects several processing steps can be clustered into one central wafer handler with environmentally isolated wafer transfer between process modules. Unique features of Rapid Thermal Chemical Vapor Deposition (RTCVD) technology can be utilized to perform more than one processing step in a single process chamber. A number of process steps can also be clustered together to provide an application specific tool. Each process module must be effectively isolated from the wafer transfer area to eliminate cross contamination. In this paper the applications of integrated processing technology using RTCVD for MOS and bipolar based devices are discussed. The technological and economical advantages of integrated processing with a cluster tool approach are addressed. Finally the equipment requirements for such a tool in a production environment are defined. 2.

In this paper we report a systematic and comprehensive study of the chemical and electrical properties of rapid thermally nitrided (RTN) and reoxidized nitrided (RTO) thin oxides and reliability of MOSFETs with these materials as gate dielectrics. The chemical properties of the RTN oxides are studied using AES and VFIR techniques. The nitridation mechanism is discussed and a model is proposed to explain the widely reported nitrogen and oxygen distribution in RTN oxides. Electrical properties of RTN oxides such as dielectric constant conduction mechanism fixed charge and interface state density charge trapping and hot electron and radiation hardness are investigated and are correlated with their chemical characteristics. Post nitridation anneals were performed on the nitrided oxides in 02 d N2 ambients. Charge trapping and hot electron and radiation hardness of the resulting films are studied and compared. Finally the MOSFETs with reoxidized nitrided oxides as gate dielectrics are fabricated and their performance and reliability are studied. 1.

Rapid thermal annealing of GaAs and InP within enclosed SiC-coated graphite susceptors is shown to eliminate slip formation during implant activation treatments and to provide much better protection against surface degradation at the edges of wafers compared to the more conventional proximity method. Two different types of susceptor were investigated-the first type must be charged with As or P prior to the annealing cycles while the second type incorporates small reservoirs into the susceptor which provide a continuous overpressure of the group V species. Degradation-free annealing of patterned metallized wafers is possible using the latter type of susceptor. The activation of Si and Be implants in GaAs by RTA is also discussed.

Silicon ion iniplantation on GaAs through tantaluni silicide film is investigated. The rapid thermal annealing is used to activate the dopant and to provide the abrupt shallow junction. After annealing process the carrier mobility ideality factor and barrier height of Ta5Si3/GaAs Schottky diode were measured. The carrier profiles were determined by C-V and differential Hall methods. The Rutherford back scattering and photoreflectance were performed in order to study the interdiffusion and internal field near the surface. Our experiments show the through-film (tantalum silicide)-implantation is the promising process in SAG technology. 1.

Twostep rapid thermal diffusion (RTD) of phosphorus using a solid diffusion source has been described. Phosphorus profiles in silicon measured by SIMS show two distinct regions which are i) constant concentration region near the surface where the phosphorus concentration exceeds the solid solubility and ii) exponentally decaying region forming the diffusion tail. For the quantative analysis of the RTD process two correction terms for the diffusion time have been introduced. The first correction term incorporates the temperature transient cycle and the second term is due to the point defect life time during the cooling. From the BoltzmannMatano analysis we have found that the correction term due to the supersaturated point defects during the cooling is 3 sec. Also concentration dependent diffusivity of phosphorus in RTD has been extracted. The diffusivity at low concentrations is similar to the conventional furnace diffusion but the diffusivity at high concentrations is much higher than the furnace diffusion case. The solid solubility and precipitation of PSi binary system have been discussed. It has been found that the chemical concentration exceeds solid solubility near the surface in the predeposition process due to the codiffusion of phosphorus and oxygen. The high diffusivity in the high concentration region in the RTD has been explained as the precipitation enhanced diffusion. 1.

Rapid Thermal Processing (RTP) has shown promise as a tool that will reduce the thermal budget presently used in the manufacture of advanced ULSI devices. Because of the rapid rates of temperature rise and fall coupled with inherent system temperature non-uniformities of RiP systems plastic deformation has been identified to occur in RTP- processed wafers. Concern over these types of process-induced defects has brought about the identification of various methods of uniformity characterization of RiP-processed wafers. In this study 150 mm p-type wafers (with no screen oxide) were first implanted on a batch implanter with conditions of 5E15 of arsenic at 80 keY. After implantation the wafers were rapid thermally annealed for 10 seconds at the temperatures ranging from 900 to 1250 C. Each wafer was then measured by several techniques: wafer warpage measurements optical imaging inspection (magic mirror method) X-ray transmission topography and thermal wave modulated-optical reflectance. This presentation summarizes the measured results of wafer defects and damage due to the RTP processing. 1.

In recent years rapid thermal processes (RTPs) have been widely studied to replace conventional processing. The use of this technique which is less time and energy consumption than classical thermal treatments can be widespread if in one hand the origin of process induced defects can be clarified and in the other hand the gettering of impurities in silicon can be effective. Up to now the RTP introduced defects was inherently correlated to the " quenching" step due to the fast cooling rate (typically around 100C/s) and the time duration of the order of seconds to tens of seconds was generally considered to be inappropriate to increase by gettering the purity of materials in the active region. The reason involved was the time scale which would not allow the impurities to migrate to the gettering sites given the diffusity values observed and measured in conventional diffusion studies. In our study we will present results showing that Deep Level Transient Spectroscopy (DLTS) is particularly efficient to identify the origin of RTP related defects. We found that they are mostly related to residual impurities present in the as-grown silicon wafers or unintentionally introduced during high-temperature processing steps. For one particular material an activation of a specific residual metallic-impurity was observed in the temperature range 800-1000C. This impurity can be returned to an electrically inactive precipitated form by classical thermal annealing (CTA) with a slow

Rapid Thermal Processing (RTP) technique finds its success in microelectronics due to shorter time and energy cosumption than conventional furnace processing. There is no further impurity redistribution which is of great interest for VLSIs researchers. This is mainly because of shorter time scale. Rapid heating and cooling in the process may give rise to defects. These RTP-induced defects have been first time probed by Positron Annihilation Technique(PAT). Positron annihilation methods have been proved as a powerful tool for studing defects in solids. The increasing interest in technique stems from its defects sensitive and non destructive nature. Positron lifetime measurements on samples silicon dioxide grown by furnace methods and RTA are presented and discussed. The data obtained from PAT gives information regarding nature of defects in material. 1 .

New chemical vapor deposition (CVD) processes controlled by light irradiation are studied and applied to 111-V semiconductor device technology. The interactions between the incident photons of and the gas-substrate system are either photolytic (UV lamps) or pyrolytic (JR lamps). In the first case the process is cold and in the second one it produces fast thermal ramping. The technique is thus compatible in both cases with the fragile semiconductor substrate and it allows in-situ processing. We report here a set ofresults involving surface and interface studies in order to prepare the deposition of thin film materials and thin dielectric film deposition using " flash" CVD or UVCVD. The aim of this work is to propose alternative technologies for Ill-V semiconductors. 1 .

Isotype heterojunctions using low pressure rapid thermal chemical vapor deposition (RTCVD) of germanium on silicon have been fabricated and incorporated into a Kelvin structure to study the contact resistivity of the stacked structure. Germanium films were deposited at 400C and 3 Torr in a tungstenhalogen lamp heated rapid thermal processor utilizing a water cooled stainless-steel process chamber. In this work germanium is considered as a buffer layer to prevent silicon consumption over source/drain regions of MOS transistors during silicidation anneals to form low resistivity silicided contacts. We report here the results of our work with a germanium/silicon heterostructure and the potential advantages of this approach. Experimental results were compared against theoretical calculations and show that the Al/Ge/Si structure can lead to substantially lower contact resistivities than the Al/Si structure especially at lower substrate doping levels. This is especially pronounced in p-type contacts where 19 improvement in the contact resistance to silicon has been observed. Native oxide removal during the initial stages of germanium growth may play a key role in this reduction in contact resistivity.

Rapid thermal processing chemical vapor deposition (RTPCVD) has received considerable attention because of its ability to reduce many of the processing problems associated with thermal exposure in conventional chemical vapor deposition while still retaining the ability to grow high quality epitaxial layers. We have used RTPCVD to grow epitaxial films of undoped Si in-situ doped Si and Ge1Si1. Both bare Si substrates and Si-on-insulator (SOl) substrates were used. We have also demonstrated selective epitaxial growth (SEG) of Si using oxide masks. Our results show that RTPCVD is capable of growing high quality epitaxial layers with sharp concentration transition profiles. 1.

Oxygen levels in epitaxial Sii_Ge films grown by rapid thermal chemical vapor deposition (RTCVD) have been reduced to under 2 x 1018 cm3 and the source of oxygen in films with higher oxygen concentration has been identified. Films with low oxygen levels have minority carrier lifetimes in the us range and Si/Sii_Ge/Si heterojunction bipolar transistors (BET''s) fabricated with low oxygen levels have near-ideal base currents which do not depend on the base composition.

Low pressure chemical vapor deposition (LPCVD) of polycrystalline SixGei. . x alloys in a cold-wall lamp heated rapid thermal processor was studied. SiGei. . alloys were deposited using the reactive gases GeHz and SiH2C12 in a hydrogen carrier gas. The depositions were performed at a total pressure of 2. 5Ton and at temperatures between 500C and 800C using GeH : SiH2C12 ratios ranging from 0. 025 to 1. 00. An enhancement in the deposition rate due to the addition of GeH was observed in agreement with earlier reports. The activation energy for deposition in the surface reaction limited regime varied from 20-30 Kcal/mole with the gas flow ratios used in this study. Results showed that SiGei. . alloys could be deposited selectively on silicon with no nucleation on Si02. Selective depositions were obtained when the GeH:SiH2Cl2 gas flow ratio was greater than 0. 2 regardless of the deposition temperature corresponding to a Ge content of 20 or higher in the films as determined by Auger Electron Spectroscopy (AES). Enhancement of the selectivity was attributed to the formation of highly volatile GeO. It was also shown that selectively deposited alloys could be used as diffusion sources to form very shallow ( 1000 A) pLn junctions in silicon by ion-implantation and rapid thermal annealing. 1.

The combination of noninvasive in-situ monitoring sensors single-wafer processing modules vacuum-integrated cluster tools and computer-integrated manufacturing (CIM) can provide a suitable fabrication environment for flexible and high-yield advanced semiconductor device manufacturing. The use of in-situ sensors for monitoring of equipment process and wafer parameters results in increased equipment/process up-time reduced process and device parameter spread improved cluster tool reliability and functionality and reduced overall device manufacturing cycle time. This paper will present an overview of the main features and impact of noninvasive in-situ monitoring sensors for semiconductor device manufacturing applications. Specific examples will be presented for the use of critical sensors in conjunction with cluster tools for advanced CMOS device processing. A noninvasive temperature sensor will be presented which can monitor true wafer temperature via infrared (5. 35 jtm) pyrometery and laser-assisted real-time spectral wafer emissivity measurements. This sensor design eliminates any. temperature measurement errors caused by the heating lamp radiation and wafer emissivity variations. 1. SENSORS: MOTIVATIONS AND IMPACT Semiconductor chip manufacturing factories usually employ well-established statistical process control (SPC) techniques to minimize the process parameter deviations and to increase the device fabrication yield. The conventional fabrication environments rely on controlling a limited set of critical equipment and process parameters (e. g. process pressure gas flow rates substrate temperature RF power etc. ) however most of the significant wafer process and equipment parameters of interest are not monitored in real

Rapid Thermal Processing (RTP) is becoming a popular approach for future ULSI manufacturing due to its unique low thermal budget and process flexibility. Furthermore when RTP is combined with Chemical Vapor Deposition (CVD) the so-called RTP-CVD technology it can be used to deposit ultrathin films with extremely sharp interfaces and excellent material qualities. One major consequence of this type of processing however is the need for extremely tight control of wafer temperature both to obtain reproducible results for process control and to minimize slip and warpage arising from nonuniformities in temperature. Specifically temperature measurement systems suitable for RiP must have both high precision--within 1-2 degrees--and a short response time--to output an accurate reading on the order of milliseconds for closedloop control. Any such in-situ measurement technique must be non-contact since thermocouples cannot meet the response time requirements and have problems with conductive heat flow in the wafer. To date optical pyrometry has been the most widely used technique for RiP systems although a number of other techniques are being considered and researched. This article examines several such techniques from a systems perspective: optical pyrometry both conventional and a new approach using ellipsometric techniques for concurrent emissivity measurement Raman scattering infrared laser thermometry optical diffraction thermometry and photoacoustic thermometry. Each approach is evaluated in terms of its actual or estimated manufacturing cost remote sensing capability precision repeatability dependence on processing history range

Infrared absorption in silicon has been investigated at elevated temperatures. The fundamental absorption process in lightly to moderately doped silicon at 1. 3 and 1. 55 zm have been identified as band-to-band and free carrier mechanisms respectively. The effects of heavy substrate doping on absorption at elevated temperature have also been studied. Significant deviations (10) from transmission vs. temperature as used to measure ternperature in a Rapid Thermal Processing system begin to occur with substrate doping levels of cm3.

The emissivity of silicon wafers was measured for two specfic conditions. Firstly the emissivity of silicon wafers below 700 C was studied. Also the influence of front-side and back-side implantation on the emissivity was studied. It was found that a highly doped wafer or an epi-wafer with a higly doped bulk have a high emissivity which is independent of temperature. Secondly the influence of back-side roughness on emissivity was measured. It was shown the the intrinsic emissivity for a silicon wafer (outside the chamber) is merely changed for moderate roughnesses. On the other hand the effective emissivity inside a reflective chamber is sensitive to back-side roughness even for moderate roughnesses. Finally it was shown that wafers with an anti-reflective back-side layer (e. g. quarter wavelength oxide or oxinitride) behave like a nearly perfect black-body at the pyrometer wavelength. 1.

A model is described which determines pyrometer measurements of the temperature of silicon wafers. The wafers may have any combination of silicon polysilicon and 2 on it. The inputs to the model are the wavelength range of the pyrometer temperature film thicknesses and order doping levels and polysilicon grain size. Experimental data provides qualitative agreement to the model. Since the emissivity of the wafer is shown to generally vary with radiation wavelength conventional multi-wavelength pyrometry does not have any obvious ways of compensating for measurement differences due to varying wafer structures. However there may be an empiricalbased alternative for multi-wavelength corrections. 1 Background As rapid thermal processors find their way into commercial applications they are likely to face increasingly tighter requirements in the control of the transient and steady state temperature of the wafer. To achieve this level of control accurate closed loop temperature control is necessary for many commercial applications of rapid thermal processing. The temperature measurement tool usually employed in these closed loop control systems is one or more pyrometers. Pyrometers determine the temperature of the wafer by measuring the magnitude of the radiation being emitted from the wafer. The relationship between temperature and spectral radiant exitance can be expressed as follows: [7] M (1) where M is the spectral radiant exitance of the wafer Mb is the spectral exitance of a black body (both measured in Watts/rn3) and

Time Resolved Reflectivity (TRR) is first applied to the measurement of the solid phase epitaxial growth rate of As (60 keY 4. 1015 cm2) implanted (100) Si wafers. The thermal cycles consist of a fast heating phase (125C/s) followed by an isothermal plateau ranging between 520 and 624C. An activation energy of 2. 8 eV is found. TRR is then applied to temperature calibration vs. Germanium thin film melting point : it is demonstrated that reproducible results are given by the method and that it can replace thermocouples for optical pyrometer calibration. 1.

This paper presents innovative software developed to help generate a temperature calibration curve and to mathematically manipulate and combine multi-point wafer maps. The software automatically applies the calibration curve to a map of film parameters to provide a quantitative map of temperature uniformity. Several process examples are presented to demonstrate the flexibility and convenience of the software. 1.

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Temperature non-uniformity caused by patterned layers during RTP is studied experimentally in six RTP-systems from different vendors. Rapid thermal oxidation and annealing are used to indirectly measure temperature non-uniformity. A good correlation is seen with theoretical predictions. The effect of a real-live pattern with LOCOS isolation is evaluated during the growth of a thin oxide by rapid thermal oxidation. The presence of thickness variations of the grown RTO oxide in the patterned areas and at the edge of the patterned region is discussed. 1.

PD (Proportional Integrated Derivative) controllers applied to temperature regulation in a rapid thermal processor are first presented. The setting method of the control parameters together with the corresponding experimental results is given. Evidence in favour of parameter dynamic adjustment is demonstrated. A new algorithm based upon parameter scheduling and providing enlarged control capability is then presented and tested with various wafers and processors. At last insights about closed loop self-tuning using Generalized Predictive Control algorithm are given and the corresponding results discussed. 1.

A numerical solution of temperature and thermally induced stress in a wafer during rapid thermal processing(R. T. P) is obtained and an analysis of onset of slip is performed. Some results are compared with experiment. In this R. T. P system one side of threeinch silicon wafer is irradiated steadily for 1015 sec in the temperature rangefrom 1100 to 1150 OC by using tungsten halogen lamp as the heat source. In order to obtain the temperature distribution of a wafer in R. T. P system twodimensional heat conduction equation that incorporates radiative and convective heat transfer is proposed and the equation is solved numerically using alternating direction implicit(A. D. I) method. In dealing with the. radiative heat transfer a partially transparent body that absorbs the radiation energy is assumed and this partially transparent body undergoes multiple internal reflections and absorptions. Twodimensional (assuming plane stress and anisotropy) thermoelastic constitutive equation is used to calculate the thermal stress induced in a wafer and a finite element method is employed to solve the equation numerically. In order to predict the slip the stress resolved on the slip planes in the slip directions of silicon is compared with the yield stress of silicon which is the function of strain rate temperature and initial dislocation density. The numerical result shows that the wafer temperature at which slip occurs is affected by the heating rate of the

When introduced in 1982 rapid thermal anneal (RTA) equipment was primarily used for the rapid turn-around of wafers used in qualification of ion implanters. Early on-line process characterization of these implanted and subsequently annealed wafers was made by the four-point probes. With the introduction of the appropriate software evaluation of implanted wafers by sheet resistance contour mapping quickly became the standard. This technique was easily applicable to the conductive thin films and became but one of the many different techniques used for complete uniformity characterization of these films. This paper will review the presently available mapping techniques commonly used for uniformity characterization of rapid thermal processor thin films. These techniques include ellipsometry reflectometry four-point probe Fourier Transform Infrared Spectrometry (VFIR) modulated-optical reflectance and reflective-optical inspection. Sample wafer measurements (i. e. contour and uniformity maps) from several of these instruments on thin film processes such as silicon dioxide titanium nitride and epi-siicon will be presented. 1.

Ion implanted polysilicon is a key material in CMOS BICMOS and bipolar processing. The evolution of these devices toward the submicron regime has raised new challenges for the technologies of ion implant and rapid thermal processing (RTP) to provide p+ gates and p+ shallow junctions. Rapid thermal annealing of high dose boron implanted polysilicon provides solutions for major problems related to p+ shallow junction formed by furnace and RTP activation of direct implants into single crystal silicon. This work demonstrates how supersaturated polysilicon films with high conductivity fabricated with I/I and RTP can provide uniformly doped p+ gates interconnects and diffusion sources for abrupt shallow p+ junctions. It is an elaboration of earlier work and is covered by a patented technology 16 1.

Silicon (100) films deposited by CVD and amorphized by ion implantation on (1102) sapphire wafers have been recrystallized by the use of Rapid-Isothermal-Processing at temperatures between 873 K to 1073 K for periods of 45to 540 S. The characterization of the regrowth was monitored by optical and infrared spectrometry. The crystallization was clearly observed in the above time range only for temperatures close to 1073 K. At this temperature for 2800 A films the measured crystallization rate was 10. 3 A/s. SIMS profile measurements showed that no diffusion of the impurities detected in the as-deposited film (such as 02 Al Mg Si30 C and Na) occurred in the film after the RIP regrowth. 1.