This PDF file contains the front matter associated with SPIE Proceedings Volume 11329, including the Title Page, Copyright Information, Table of Contents, Author and Conference Committee lists.

We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes, the fabrication of multi-layer films requires the precision of atomic scale XY CD controllability in complex hole patterns. In order to solve the requirement, we have developed Advanced Quasi- Atomic Layer Etching (ALE) technology which achieved X-Y CD control in oval patterns, along with a wider X-Y CD control margin. Furthermore, in the memory fabrication process, it is required to vertically etch the organic film mask pattern in high aspect ratio (A/R) feature. Therefore, we have developed a new approach that combines atomic layer deposition (ALD) technique and organic film etch process. With this method, we are able to achieve the vertical mask profile. Thus, we will show that these new process technologies have a significant potential to solve critical challenges in the various processes in advanced nodes.

We performed molecular dynamics (MD) simulation to study the evaluation of silicon germanium alloy (SiGe) damage with oxidation behavior after plasma gas treatments. Our study provides a fundamental understanding of the atomistic/ molecular level of SiGe behavior after plasma etching of a contact etch stop layer (CESL). We found that simulation results are very good agreement with experimental data from Secondary ion mass spectroscopy (SIMS) and Transmission Electron Microscope (TEM)/ Energy-dispersive X-ray spectroscopy (EDS) and the detailed atom and bond analysis are obtained to study the surface reaction during the plasma process

Maximizing yield in a modern semiconductor fab requires proper optimization of the design (layout), process technology, and fab process tool recipes. For the past decade the prevalence of systematic defects tied to design or design-process interactions have predominated over random defect sources. Previously Resolution Enhancement Technology (RET), Design For Manufacturability (DFM), and Design-Technology Co-optimization (DTCO) techniques were the successful response to eliminating systematic yield limiting patterns. Machine learning, with its ability to find trends and make predictions based on large volumes of data, provides a unique path towards further reduction in systematic defect levels. This talk will present methods based on the use of design and process info with machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling and OPC, and improve the productivity and accuracy of fab defect detection and diagnostics. This paper will present methods to improve EPE control and reduce systematic hotspots through both supervised and unsupervised machine learning. Specifically we will focus on 3 areas: - identifying and yield limiting patterns in the design phase. - improving the accuracy (EPE control) of mask generation with machine learning assisted etch and resist modeling and OPC. - improving the productivity and accuracy of fab defect detection and diagnostics with machine learning.

Predictive modeling of the pitch-walk variance from multistep coupled processes, such as SAQP using experimental metrology observables, has the potential to give both deep understanding and a control mechanism for pitch-walk variance. In this study, with the Bayesian dropout approximation, a methodology using Bayesian inference via use of stochastic neural networks was employed to both model and predict the SAQP pitch-walk variance distribution. Bayesian neural networks were implemented as variational ensembles of networks with hidden layers, where the neural net training uses conventional dropout, while the forward solves employ a dropout Bayesian vector methodology previously developed by Gal and Ghahramani.^{1, 2} An important distinction here is that the forward propagations effectively sample the network to make a prediction, resulting in a distribution of outputs achieving the best model, not just a single expectation value. A complete dataset of fin module OCD metrology measurements per chip at top mandrel, bottom mandrel, and final fin reveal were used. Since the measured dataset was limited to small number chip locations, data augmentation with the highly efficient method of the volume of simplex was used to generate 30K samples. The synthetic data and the experimental data were used for neural network calibration and validation, respectively.

We present a model-based experimental design methodology for accelerating 3D etch optimization with demonstration on 3D NAND structures. The design and optimization of etch recipes for such 3D structures face significant challenges requiring costly and time-consuming experiments in order to achieve the required tolerances. 3D NAND memory devices additionally require accurate nanofabrication of high aspect ratio trenches and isolation slits, which are challenging to manufacture reliably within specifications. Our model efficiently captures the relevant physical and chemical processes, which allows them to be calibrated using a limited number of experimental samples and can reproduce realistic 3D etch of multilayer materials, including bowing, necking, and tapering. Since our GPU-powered simulations run in a matter of minutes, the relevant process parameter space can be explored extensively in a short amount of time. The calibrated physics-based model can be used to train adaptive machine-learning-based heuristics which enable near-instant queries, for example for data visualization and analytics. With this approach, we show a rapid methodology for locating optimal windows in the process parameter space for etching 3D structures. Optimality metrics under consideration include both conformances to specified tolerances as well as robustness against process parameter variations. These techniques can reduce cost and time to market for complex multi-layer three-dimensional device designs and improve semiconductor device yields.

Due to ever decreasing device dimensions and the introduction of 3D device architectures, it is challenging to operate within a narrow processing window using conventional plasma etching. One method to address the demands of the next-generation of devices is atomic layer etching (ALE) which provides high fidelity, selectivity, and directionality, and layer-by-layer removal. Plasma-assisted ALE has been extensively studied for a variety of materials, including Al2O3, HfO2, Si, and Si based dielectrics. Plasma-assisted ALE of SiO2 or SiNx typically uses two sequential steps in a cyclic fashion: CFx deposition from a C4F8/Ar plasma followed by an Ar plasma activation step. However, the surface chemistry during plasma ALE is not well understood. In this study, we used in situ attenuated total reflection Fourier transform infrared (ATR FTIR) spectroscopy and in situ four-wavelength ellipsometry during ALE to monitor the surface reactions, film composition, as well as the net film thickness. Similar to area-selective atomic layer deposition, we show that surface functionalization prior to ALE can be used to alter the etch per cycle. Using this methodology, we will discuss how selective functionalization of SiO2 or SiNx can be used to alter the selectivity during plasma-assisted ALE. Acknowledgement: We would like to acknowledge our collaborators at Lam Research for funding this work.

The etching of silicon nitride spacers is one of the most challenging steps of transistor fabrication. It requires anisotropy to preserve the sidewalls and a high etch selectivity over the underlying substrate to achieve a high surface quality. Recently, an interesting approach using a two step-process was proposed for the etching of silicon nitride spacers with high anisotropy and minimal induced damage [1]. The first step uses an H₂ implantation to selectively modify the horizontal SiN surfaces over the vertical ones, while the second step selectively removes the modified layer either via HF exposure or via a remote plasma (RP). This paper explores a new route to implement those two steps in a cycling process achieved in the same plasma reactor chamber. The reactor has the capability to produce both a capacitive plasma discharge (CCP) for the implantation step and a remote discharge for the removal step. This study demonstrates that the remote plasma process, whose etching mechanisms are driven by reactive neutrals, is highly sensitive to the material surface state and consequently an incubation time exists before the etching starts when exposed to neutrals. The modifications induced by the first implantation step shortens the incubation time offering a process window with infinite etch selectivity between horizontal implanted and vertical non-implanted surfaces. Based on this understanding a two-step cycling process was developed and applied successfully to the etching of Si₃N₄ spacer patterns for imager applications.

Stochastic defects in the photoresist profile are one of the main yield limiters in EUV lithography patterning. These stochastic defects can be, for example, local resist loss, resist profile footing, or resist scumming. A subset of these defects is transferred through the hardmask open (HMO) patterning, leading ultimately to electrical opens and shorts. We use on-wafer data and process recipes to inform a physical etch model of the HMO process. This model is tested and confirmed by comparison to additional on-silicon data. The established model provides a visualization of the defect transfer through individual process steps and highlights critical patterning steps that may limit electrical yield. For example, a change in in-situ deposition time is observed to be more sensitive than oxide open or planarization film open times both in the model and on-wafer. This provides us the insight to focus tuning deposition step times to reduce defectivity and improve process performance. Furthermore, this model provides insight into the type of defects which are eliminated during specific patterning steps, and the type of defects which are persistent and ultimately lead to electrical opens and shorts. To characterize these defects, we plant intentional defects with varying dimensions and study which ones stay through the entire HMO process and which ones are eliminated. This insight helps better understand the HMO process, which may lead in the future to further process improvements.

Performance demands for many devices has driven feature dimensions to reduce to sub nm scale. Whilst new, and complex combinations of materials have increased the importance of interface effects at the atomic scale. Many of the macro-market dynamics such as Internet of Everything, increased volume in data traffic and energy efficiency require III-V based devices eg GaN, SiC. The combination of new materials and dimensions means that new etch solutions are required to achieve the accuracy and low damage needed for optimized device results. Low damage etching of AlGaN, GaN and SiN layers were studied using the PlasmaPro100 Cobra300 system from Oxford Instruments Plasma Technology, configured with ICP-RIE, RIE and ALE plasma etching modes. These techniques were used to etch shallow depths of between 5 and 100 nm in both SiN, AlGaN and GaN substrates and the resultant etched surface layer quality was measured using Atomic Force Microscopsy (AFM). ALE of SiN and GaN showed etch rates of 2.5 nm/min and 2 nm/min respectively. Using a conventional ICP-RIE process a GaN etch rate of 50 nm/min with a selectivity to AlGaN of 25:1 was achieved.

Emerging memory technologies such as Resistive Memory (RRAM) have gained a lot of attention to meet the requirements of a potential analog computing element, due to its non-volatile characteristics, scalability and energy efficiency. An RRAM device typically consists of a resistive switching layer (e.g. HfO2) sandwiched between two metal electrodes. Since oxygen vacancies are critical to the functioning of the device, it is desirable to achieve residue free etching using oxygen-less plasmas, and preferably minimize exposure to ambient environment. In this work, we discuss the RRAM patterning challenges and their impact on the device characteristics including the switching/forming voltage.

FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industry since N20 node onward. Contact Poly Pitch (CPP) scaling used to be the main driving force in extending Moore’s law. However, severe limitations are foreseen from N3 node in terms of electrical performance, process requirements and manufacturing complexity. At N3 node, both fin and gate pitches are expected to reach their ultimate values, respectively 21 nm and 42 nm. Therefore, complex plasma etching processes using advanced plasma pulsing modes or atomic layer etching (ALE) are deployed to achieve high aspect ratio patterning capability with a detrimental effect on both process control and throughput. As an alternative, device architecture innovation will become the main scaling driving force for N3 node and beyond. 2D scaling like horizontal Gate-All-Around (GAA) devices, such as nanosheet (NS) and forksheet (FS) have demonstrated the potential for further device performance improvement [1,2]. The major NS patterning challenges are the SiGe lateral etch in the Si/SiGe superlattice stack and severe depth micro-loading due to the etch rate difference of SiGe and Si. In addition, 3D hybrid device architectures like Complementary FET (CFET) and Surrounding-Gate-Transistors (SGT) are proposed as revolutionary innovations to scale the devices in the vertical direction. For CFET devices, the N/P separation is moved to the vertical direction by stacking nMOS on top of pMOS or vice versa to achieve aggressive device scaling. This requires extremely high aspect ratio fin and gate patterning compared to horizontal-GAA NS devices. For SGT device, the channel is switched to the vertical direction, which can decouple the Gate length (Lg) from CPP scaling and eliminate the diffusion break to deeply scale the cell size. High aspect ratio vertical nanowire (NW) and direct metal gate etching with tight pitch are the new FEOL patterning challenges for the fabrication of SGT vertical devices.

The parallelism of optics and the miniaturization of optical components using nanophotonic structures, such as metasurfaces, present a compelling alternative to electronic implementations of convolutional neural networks. The lack of a low-power optical nonlinearity, however, requires slow and energy-inefficient conversions between the electronic and optical domains. Here, we design an architecture that utilizes a single electrical to optical conversion by designing a free-space optical frontend unit that implements the linear operations of the first layer with the subsequent layers realized electronically. Speed and power analysis of the architecture indicates that the hybrid photonic–electronic architecture outperforms a fully electronic architecture for large image sizes and kernels. We also explore the ways the nonlinearity can be implemented in optical domain, and analyze the performance of a degenerate cavity for nonlinear image processing.

R&D on transistor fabrication and scaling for current and future technology nodes involves various 3D-device architectures like the established finFET (fin “Field Effect Transistor”), and newer architectures like GAA (Gate All Around) which may include VFET (vertical FET), CFET (complimentary FET), etc. These new architectures are being investigated as potential solutions to enable further CMOS area and performance scaling and continue Moore’s law. Typically node to node area scaling is achieved through pitch reduction of critical layers such as contacted poly pitch (CPP) and fin pitch in FEOL, and Mx pitch in the BEOL. For such advanced nodes, at the device level, the CPP reduction translates to a stronger drive for shorter gate length (Lg) and so, for improved electrostatics control (Ion, Ioff, Tinv, etc.). Integration schemes for such advanced 3D architectures must deliver excellent process control and uniformity, especially for critical device features such as gate length and channel dimensions, and demand self-aligned multi-patterning schemes to address edge-placement accuracy, overlay, multiple mask sets, etc. A frequently encountered etch step in such integration schemes is the trimming of Si features made of mono, polycrystalline, or amorphous Si. Some key applications are listed here: fin trimming for (1) lateral transport finFET and for (2) vertical transport VFET, (3) final gate trim for lateral transport finFET, GAA/CFET, etc. (4) amorphous gate mandrel trim for lateral transport FETs (multi-patterning).

Plasma etch residue formation and its removal from silicon nitride (SiN) films deposited at 200ºC, 480ºC and 700ºC is explored. X-Ray Photoelectron Spectroscopy (XPS) measurements showed that SiN contains more nitrogen (N) and less oxygen (O) with increasing deposition temperature. SiN films were etched in an Inductively Coupled Plasma (ICP) reactor in a halogen/hydrofluorocarbon (H:HFC) gas mixture; the carbon (C) containing species in the resulting residue films were studied as a function of the H:HFC ratio in the plasma. Post-plasma etch cleaning methods of the SiN surface were compared, these included: wet treatment with diluted hydrofluoric acid (dHF), sputtering with argon (Ar) plasma, and combined dHF and Ar plasma. After etch, Secondary Ion Mass Spectroscopy (SIMS) and XPS data showed formation of fluorocarbon (FC) films on SiN. FC film thickness after etch was estimated from XPS to reach up to 2 nm. Ultimately the SiN etch rate was shown to drop with increasing deposited C thickness while the lower nitrogen content in the SiN film (i.e. 200ºC) led to higher etch rate, which is in good agreement with literature. Ar plasma sputter turned out to be the most effective way of cleaning C residues: C surface content after Ar sputter was reduced to or below the reference data (unetched sample). In terms of wet treatment, an optimized chemistry was identified (AltChem) and post-RIE cleaning was more efficient than dHF in reducing C surface concentrations.

As the logic industry marches toward the 5nm technology node, multiple patterning schemes are intensively used to achieve sub-193nm lithography resolution for line and space definition. Several sources are reporting the need to use Self Aligned Dual Patterning (SADP) with EUV lithography. Implementing those spacer-based pitch splitting techniques is not trivial; they require major design changes and restrictions along with the additional patterning steps. They also increase manufacturing cost and process complexity. A faster, cost-effective option would be advantageous. Spin-on-carbon (SOC) is a promising candidate for first mandrel formation compared to alternatives such as Chemical Vapor Deposition (CVD) materials due to its lower cost and high-throughput. There are several benefits of using SOC as a first mandrel for SADP such as minimal recess in the floor during mandrel formation and high selectivity during the spacer etch and mandrel pull process. However, during the deposition of the spacer material, usually oxide or nitride, the carbon mandrel can be eroded, and the shape can be distorted, affecting the shape of the spacer in the next step. To enable the use of SOC for first mandrel, mandrel treatment and spacer shape optimization need to be addressed. In this paper, we will investigate a method to protect and preserve the shape of the carbon mandrel by using a direct current superposition (DCS) on a capacitively-coupled plasma (CCP) chamber. Then, we will review spacer etch development to reach the required final shape. Finally, we will perform a step-by-step roughness analysis and consider additional smoothing options.

Extreme ultraviolet (EUV) lithography is the technology for high volume manufacturing (HVM) of semiconductor ICs for photoresist patterns smaller than 75nm pitch¹. A persistent challenge of the EUV scanner is to supply a high contrast image with enough photons to the photoresist (PR) to meet HVM productivity targets with acceptable dimensional and defectivity control. Local stochastic variability in dimension and placement dominates the total dimension control budget and reducing that variability by increasing the exposure dose comes at the cost of scanner throughput. Our objective is to deliver holistic patterning solutions by co-optimization of patterning film stack, lithography, and subsequent etch processes to transfer the patterns to the target layer with CD and placement control of order 1nm or less! This synergistic approach enables circuit fabrication customers to manage the tradeoff between stochastic defects and productivity in EUV patterning.

The integration of new materials in the next generation of optoelectronic devices leads to several challenges. For instance, the etching of indium tin oxide (ITO, In₂O₃:Sn) faces the issue of the low volatility of In- and Sn-based etch products at room temperature. This is challenging for the etching process itself, but even more problematic when the inductively coupled plasma (ICP) reactor must be cleaned after etching: since the reactor walls are bombarded by low energy ions only, the removal of In- and Sn-based products redeposited on the walls can be very long and laborious. Therefore, we have investigated several plasma chemistries to find the most efficient reactor cleaning process suitable for ITO plasma etching. The results show that after ITO plasma etching the walls are indeed contaminated by indium. At the low temperature at which the reactor walls are regulated, BCl₃/Cl₂ cleaning plasma is ineffective to remove this deposit while HBr and CH₄/Cl₂ chemistries provide promising results.

We present a machine learning-based metrology pipeline for electron microscope imagery in the semiconductor industry. The pipeline is targeted to reduce the time spent by Process Engineers during research and development, by automating measurements of features according to their instructions in the form of a “measurement recipe”. Specifically, we present the principles and functionality of tools to measure Fin and 3D Memory structures based on edge finding algorithms, including through direct modelling of the SEM acquisition process to better capture blurred-appearing features.

As the critical dimensions (CDs) of etch profiles continue to decrease, precise control of plasma etch processing becomes increasingly important. Achieving this control requires optimizing etch recipes, which is time consuming and expensive as an extensive amount of experiments must be performed. Here we present a method for the prediction of process windows to achieve target CDs for high aspect ratio trenches using model-based experimental design. A reduced-order model of the physics and chemistry of the etch is used to identify the best experiments to perform to calibrate the model. The model is then used to efficiently explore the process parameter space to identify the largest ranges of process parameters that achieve desired ranges of CDs. The methodology is practically demonstrated on a three-step trench etch through three layers of material consisting of spin-on-glass, spin-on-carbon and silicon. It is found that this physics-model based method requires less than half as many experiments to identify the optimal etch recipe than full-factorial design of experiments.

The etch induced on-product overlay performance across wafer has received quite some attention recently. Global wafer overlay penalties have been observed by realizing that the etch direction is not always perpendicular to the wafer surface and may vary slightly as a function of the wafer radius due to the geometry and plasma parameter settings of the etch tool. In particular close to the wafer edge, for radii in between 130-mm and 150-mm, the etch direction may change even more strongly and is not constant over time. This is due to a consumable part inside the etch tool, the so-called focus ring. Control solutions based on optical overlay metrology have been developed and have found their way into tunable focus rings. The general concept is to keep the etch direction perpendicular to the wafer surface throughout the life-time of the focus ring. The general belief is that these global etch induced overlay penalties can be mitigated by applying these newly developed hardware control solutions. In this experimental work, we go one level deeper and consider the more local etch induced overlay penalties. This time etch effects on length scales on the order of exposure field and/or die level are addressed. The intra-field etch induced overlay penalties are characterized by considering the overlay measurement after resist development (ADI) and after etch (AEI). Surprisingly, the observed penalties are on the order of ~1-nm within each individual exposure field despite the fact that away from the wafer edge the etch direction is considered to be close to perpendicular to the wafer surface. In this experimental work, etch tool parameters like low frequency (LF) power and pressure have been varied to reveal the nature of these die-level overlay penalties. Based on the experimental results, we present a hypothesis of the underlying mechanism that explains the etch induced intra-field overlay penalties and provide solution directions to mitigate these kinds of overlay penalties.